Contact layer for SPAD and preparation method thereof, and SPAD and preparation method thereof

Abstract

The present invention relates to a contact layer for a single-photon avalanche photodiode SPAD, which is an N-level coaxial symmetrical step structure formed by the upper surface of the barrier layer of an epitaxial wafer, which is gradually recessed from both sides to the middle. The present invention also relates to a method for preparing a contact layer for SPAD, which comprises: etching the barrier layer of an epitaxial wafer N times to obtain a contact layer. The thickness of the contact layer provided by the present invention gradually decreases from both sides to the middle, so that in the process of preparing the pn junction of SPAD, only one zinc diffusion is needed to obtain a zinc diffusion morphology with a diffusion depth at the edge of the active area less than that in the middle area and a larger radius of curvature, thereby achieving effective prevention of edge pre-breakdown while enhancing the lateral electric field component and reducing the impact of the charge persistence effect on the single-photon performance of the SPAD. In addition, the present invention also relates to a SPAD and a method for preparing it.

Description

Technical Field

[0001] The present invention belongs to the technical field of photodiodes, and in particular relates to a contact layer for a single-photon avalanche photodiode and a preparation method thereof, as well as a single-photon avalanche photodiode and a preparation method thereof. Background Art

[0002] Single photon avalanche photodiodes (SPADs) are currently widely used in quantum secure communications, quantum imaging, laser radar, biomedicine, and integrated circuit detection. When SPAD enters Geiger mode, the external circuit provides a reverse bias voltage V r Higher than the device breakdown voltage V br , at this time, the instantaneous response current of the device to extremely weak light can reach the mA level, that is, the SPAD has the ability to detect single photons. The single-photon detection efficiency PDE is an important parameter that characterizes the detection capability of the SPAD. Usually, the improvement of PDE can be achieved by increasing the over-bias voltage applied to both ends of the device. However, under the effects of thermal excitation, inter-band tunneling, and defect-assisted tunneling, the dark counts formed by the self-sustaining avalanche caused by dark carriers also increase with the increase of over-bias voltage. For SPAD, the dark count rate under the premise of meeting a certain PDE is the core indicator of single-photon performance, which determines the degree of extractability of single-photon avalanche signals. Therefore, reducing the dark count rate is a key technology to achieve high-performance SPAD.

[0003] Usually, for planar SPAD or other avalanche photodiodes APD, since the surface of the wafer epitaxy (i.e., the contact layer) is flat, the pn junction can only be prepared through the traditional secondary zinc diffusion process, that is, on the surface of the wafer epitaxy, under the action of the first photolithography mask, the first zinc diffusion is carried out to obtain a shallow diffusion with a larger area, to prevent the front edge of the diffusion area around the active area from changing abruptly to improve the final edge curvature of the diffusion and avoid pre-breakdown of the edge; under the action of the second photolithography mask, the second zinc diffusion is carried out to obtain a deep diffusion with a smaller area, to define the active area of ​​the photosensitive surface and the thickness of the multiplication layer. These two parameters determine the final DC photoelectric characteristics of the device (turn-on voltage, breakdown voltage, dark current, etc.). However, the secondary zinc diffusion process has the following disadvantages:

[0004] (1) The secondary zinc diffusion process still has poor effect in preventing edge breakdown. In the actual process, it is found that the diffusion depth at the edge of the active area is deeper than that in the center (edge ​​enhancement effect). In the Geiger mode, the avalanche probability in the center area may still be lower than that in the edge area, resulting in the device needing to load a larger over-bias voltage to achieve the PDE that meets the application, which increases the dark count rate of the SPAD.

[0005] (2) The secondary diffusion process is difficult to achieve further optimization and control of the edge curvature. When there is non-ideal light absorption in the area surrounding the active region to generate holes, it is impossible to reduce the charge persistence effect by enhancing the lateral electric field component in the absorption layer, thereby reducing the dark count rate. Summary of the invention

[0006] In view of the defects existing in the prior art, the technical problem solved by the present invention is: to provide a contact layer for SPAD and a preparation method thereof, as well as a SPAD and a preparation method thereof, which can effectively prevent edge pre-breakdown while enhancing the lateral electric field component in the absorption layer, reducing the charge persistence effect, and lowering the dark count rate to obtain a high-performance SPAD.

[0007] In a first aspect, the present invention provides a contact layer for a single-photon avalanche photodiode SPAD, wherein the contact layer is an N-level coaxial symmetrical step structure formed by the upper surface of a barrier layer of an epitaxial wafer, which is gradually recessed downward from both sides to the middle; wherein N≥1.

[0008] In a second aspect, the present invention further provides a method for preparing a contact layer for a SPAD, the preparation method comprising: etching a barrier layer of an epitaxial wafer N times to obtain a contact layer; wherein N≥1.

[0009] Preferably, the preparation method specifically comprises the following steps:

[0010] A mask window is formed on the surface of the barrier layer to etch the barrier layer to form a contact layer having a coaxially symmetrical step;

[0011] The contact layer obtained each time is used as a barrier layer, and the above steps are repeated to make a mask window and etch until a contact layer containing N levels of coaxially symmetrical steps is formed;

[0012] The diameter of the latter mask window is smaller than the diameter of the previous mask window.

[0013] Preferably, the material of the barrier layer is In 1-x Ga x As y P 1-y ; where 0≤x≤1, 0≤y≤1.

[0014] Preferably, the material of the barrier layer is In with different compositions. 1-x Ga x As y P 1-y A composite material formed by stacking up and down layers; wherein the y value gradually decreases from top to bottom, and the difference in y values ​​between two adjacent layers is ≥0.2; 0≤x≤1, 0≤y≤1.

[0015] Preferably, the specific step of making the mask window includes: depositing a dielectric film on the surface of the barrier layer, and making the mask window by photolithography and reactive ion etching; the specific step of etching the barrier layer includes: dry etching the barrier layer.

[0016] Preferably, the specific step of making the mask window includes: directly defining the mask window on the surface of the barrier layer by photolithography; the specific step of etching the barrier layer includes: using H 2 SO 4 , H 2 O 2 The barrier layer is wet-etched by an etching solution mixed with deionized water.

[0017] In a third aspect, the present invention further provides a SPAD, comprising a cap layer and a contact layer disposed above the cap layer.

[0018] In a fourth aspect, the present invention further provides a method for preparing a SPAD, the method comprising:

[0019] Etching the barrier layer of the epitaxial wafer N times to obtain a contact layer;

[0020] A mask diffusion window is made on the surface of the contact layer, zinc is diffused to a target depth, and the mask is removed.

[0021] Preferably, the specific steps of making a mask diffusion window on the surface of the contact layer include: depositing a dielectric film on the surface of the contact layer, making a mask diffusion window by photolithography and reactive ion etching, and the diameter of the mask diffusion window is greater than or equal to the diameter of the mask window made before the first etching of the barrier layer.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] (1) The contact layer for SPAD provided by the present invention has a coaxial step-symmetrical structure, and its thickness gradually decreases from both sides to the middle, so that in the process of preparing the pn junction of the planar SPAD, only one zinc diffusion is required to obtain a zinc diffusion morphology in which the diffusion depth at the edge of the active area is smaller than that in the middle area and the curvature radius is larger, thereby effectively preventing edge pre-breakdown while enhancing the lateral electric field component, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0024] (2) The method for preparing the contact layer for SPAD provided by the present invention obtains a contact layer including an N-level coaxially symmetrical step structure by etching the upper surface of the barrier layer multiple times, so that in the process of preparing the pn junction of the planar SPAD, only one zinc diffusion is required to obtain a zinc diffusion morphology in which the diffusion depth at the edge of the active area is smaller than that in the middle area and the radius of curvature is larger, thereby effectively preventing the edge from being pre-broken, while enhancing the lateral electric field component, reducing the charge persistence effect, and lowering the dark count rate to obtain a high-performance SPAD; moreover, the above-mentioned preparation method has a simple process and is convenient to operate, and can more easily obtain the ohmic contact of the P-type electrode, thereby obtaining a high-performance and long-life SPAD.

[0025] (3) The SPAD provided by the present invention has a zinc diffusion morphology in which the diffusion depth at the edge of the active region is smaller than that in the middle region and the radius of curvature is larger. Compared with the SPAD made by the traditional secondary zinc diffusion process, under the condition of the same multiplication layer thickness, the peak value of the electric field component in the horizontal direction of the lateral electric field increases by about 40-80%, thereby reducing the charge persistence effect, reducing the dark count rate, and improving the performance of the SPAD. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic structural diagram of a contact layer according to an embodiment of the present invention;

[0028] Figure 2 A process flow chart for preparing a contact layer according to an embodiment of the present invention;

[0029] Figure 3 A process flow chart of preparing a contact layer according to another embodiment of the present invention;

[0030] Figure 4 This is a process flow chart for preparing SPAD according to an embodiment of the present invention;

[0031] Figure 5 This is a simulation calculation diagram of the horizontal electric field component distribution cross section of a SPAD according to an embodiment of the present invention, where the horizontal and vertical coordinates are the horizontal distance positions relative to the central axis of the device;

[0032] Figure 6 This is a simulation calculation diagram of the horizontal electric field component distribution cross section of the SPAD prepared by the traditional secondary zinc diffusion process. The horizontal and vertical axes in the figure are the horizontal distance positions relative to the center axis of the device.

[0033] In the figure: 1-barrier layer, 11-In 0.53 Ga 0.47 As barrier layer, 12-In 0.73 Ga 0.27 As 0.63 P 0.37 Barrier layer, 13-In 0.83 Ga 0.17 As 0.39 P 0.61 Barrier layer, 100-contact layer, 111-first step, 112-second step, 113-third step, 2-cap layer, 3-first mask layer, 31-first mask window, 4-second mask layer, 41-second mask window, 5-third mask layer, 51-third mask window, 6-diffusion mask layer, 61-diffusion mask window, 7-zinc diffusion morphology. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0035] In a first aspect, an embodiment of the present invention provides a contact layer for a SPAD.

[0036] Reference Figure 1 , Figure 1 The contact layer 100 is a schematic diagram of the structure of the contact layer of the embodiment of the present invention. The contact layer 100 is an N-level coaxial symmetrical step structure formed by the upper surface of the barrier layer 1 of the epitaxial wafer, which is gradually recessed from both sides to the middle; wherein N≥1.

[0037] The contact layer in the embodiment of the present invention has a concave coaxial symmetrical step structure, so that the thickness of the contact layer gradually decreases from both sides to the middle. Since the contact layers of different thicknesses have different effects on the diffusion rate of zinc (the thicker the contact layer, the slower the diffusion rate of zinc), during the downward diffusion of zinc, the diffusion rate of zinc in the thin contact layer area is fast and the diffusion rate of zinc in the thick contact layer area is slow. The diffusion edge morphology is fine-tuned by this rate difference, forming a zinc diffusion morphology in which the diffusion depth of the active area edge is smaller than that of the middle area and the curvature radius is larger.

[0038] Since the diffusion depth at the edge of the active area of ​​the improved zinc diffusion morphology is smaller than that in the middle area, there is no edge enhancement effect, thus effectively preventing edge pre-breakdown; at the same time, the curvature radius of the improved zinc diffusion morphology is larger, which can enhance the lateral electric field component, thereby accelerating the lateral drift speed of photogenerated carriers in the absorption layer, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0039] Therefore, compared with the contact layer with a planar structure in the prior art, the contact layer with a concave coaxially symmetrical step structure in the present embodiment enables the planar SPAD to obtain a zinc diffusion morphology in which the diffusion depth at the edge of the active area is smaller than that in the middle area and the curvature radius is larger, while effectively preventing edge pre-breakdown, enhancing the lateral electric field component, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0040] In a second aspect, an embodiment of the present invention further provides a method for preparing a contact layer for a SPAD.

[0041] The preparation method comprises: etching the barrier layer of the epitaxial wafer N times to obtain a contact layer; the contact layer is an N-level coaxial step symmetrical structure formed by the upper surface of the barrier layer of the epitaxial wafer being gradually recessed from both sides to the middle; wherein N≥1.

[0042] The preparation method provided in the embodiment of the present invention obtains a contact layer including an N-level coaxially symmetrical step structure by etching the upper surface of the barrier layer multiple times, so that during the preparation process of the pn junction of the planar SPAD, only one zinc diffusion is required to obtain a zinc diffusion morphology in which the diffusion depth at the edge of the active area is less than that in the middle area and the curvature radius is larger, thereby effectively preventing edge pre-breakdown while enhancing the lateral electric field component, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0043] Moreover, the above preparation method has a simple process and is easy to operate, and can more easily obtain the ohmic contact of the P-type electrode, and the ohmic contact of the P-type electrode can significantly improve the life and performance of the SPAD. Therefore, the above preparation method can more easily obtain a high-performance and long-life SPAD.

[0044] Preferably, the method for preparing a contact layer for SPAD specifically comprises the following steps:

[0045] S1: preparing a target epitaxial wafer, the surface of which is a barrier layer, which is equivalent to a contact layer with a flat morphology in the prior art;

[0046] S2: making a mask window on the surface of the blocking layer;

[0047] S3: etching the barrier layer to form a contact layer having a first-level coaxial step symmetrical structure;

[0048] S4: using the contact layer obtained each time as a barrier layer, repeating steps S2 and S3 to make a mask window and etching, until a contact layer having an N-level coaxial step symmetrical structure is obtained.

[0049] Preferably, the material of the barrier layer is In1-x Ga x As y P 1-y , the value range of y can be 0.3≤y≤0.5; or the material of the barrier layer is In with different compositions 1-x Ga x As y P 1-y The composite material formed by stacking up and down has a y value that gradually decreases from top to bottom, and the difference in y values ​​between two adjacent layers is ≥ 0.2. Among them, 0≤x≤1, 0≤y≤1.

[0050] The barrier layer of this embodiment uses In 1-x Ga x As y P 1-y Materials, In 1-x Ga x As y P 1-y It is necessary to make a P-type ohmic contact with Ti / Pt / Au. Compared with the prior art that uses InP selectively grows SAG as a barrier layer and needs to make a P-type ohmic contact with Pd / Zn / Pd / Au, the ohmic contact in this embodiment is easier and the process is more mature. 1-x Ga x As y P 1-y P-type ohmic contact with Ti / Pt / Au is made because the electrode contains Ti on SiO 2 Better adhesion on the passivation layer.

[0051] In addition, when the barrier layer material is composed of various In 1-x Ga x As y P 1-y When the composite material is stacked up and down, the difference in y value between two adjacent layers is set to ≥0.2, so that the difference in corrosion rate of each layer is large, thereby improving the consistency and repeatability of the etching process.

[0052] Preferably, when the material of the barrier layer is In 1-x Ga x As y P 1-y When the barrier layer is made of In with different compositions, the thickness of the barrier layer is 300~480nm; 1-x Ga x As y P 1-y When a composite material is stacked up and down, the thickness of each layer (that is, the thickness of each step) is 100~120nm.

[0053] Preferably, when the material of the barrier layer is In 1-x Ga x As y P 1-y When the mask window is formed, the specific steps include: depositing a dielectric film on the surface of the barrier layer, and forming the mask window by photolithography and reactive ion etching (RIE); the specific steps of etching the barrier layer include: dry etching the barrier layer.

[0054] The dry etching adopted in this embodiment can more accurately control the thickness of each step, thereby improving the consistency and repeatability of the preparation process.

[0055] Preferably, the dielectric film deposited on the surface of the barrier layer is SiO 2 The dielectric film has a thickness of 100-200 nm, and the deposition methods of the dielectric film include plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like.

[0056] Preferably, when N≥2, the diameter of the mask window produced in the latter process is 2-6 μm smaller than the diameter of the mask window produced in the previous process.

[0057] Preferably, the dry etching is performed by an inductively coupled plasma (ICP) device. The dry etching of this embodiment can be performed by conventional methods in the art.

[0058] Preferably, when the material of the barrier layer is In composed of a plurality of different compositions 1-x Ga x As y P 1-y When the composite material is stacked up and down, the specific steps of making the mask window include: directly defining the mask window on the surface of the barrier layer by photolithography; the specific steps of etching the barrier layer include: using H 2 SO 4 , H 2 O 2 The barrier layer is wet-etched by a corrosive solution mixed with deionized water (DIW).

[0059] Preferably, when the mask window is defined by photolithography, the diameter of the mask window produced in the latter process is smaller than the diameter of the mask window produced in the previous process, and the difference between the two diameters is 2-6 μm.

[0060] Preferably, H 2 SO 4 :H 2 O 2 : The molar mass ratio of DIW is 1:1:10. According to the set contact layer thickness and barrier layer material, the corrosion time is set. When y=1 (i.e. the material is In 0.53 Ga0.47 When y≠1 (i.e. the material is a ternary material), the corrosion time is 10~30s; when y≠1 (i.e. the material is a quaternary material), the corrosion time is 1~15min.

[0061] The method for accurately controlling the etching depth in the present application includes: making a corresponding pattern by photolithography, and measuring the thickness H of the pattern photoresist PR before etching by a step meter. 1 ; The barrier layer is corroded, and the step profiler measures the sum of the PR thickness after corrosion and the thickness of the target material after corrosion H 2 +H 3 ; Remove glue, step meter measures the depth of corrosion H 3 , and record the time t consumed by the corrosion depth H3; calculate the material corrosion selectivity (H 3 / (H 1 -H 2 )) and material corrosion rate (H 3 / t); select the PR spin coating thickness H according to the above calculation results and the designed contact layer thickness in the structure 1 The corrosion depth of the contact layer can be precisely controlled by the corrosion time T. The corrosion time can be slightly longer to ensure that the step is completely corroded (the corrosion rate of the lower layer is significantly slower, so the influence of slight over-corrosion can be ignored).

[0062] This embodiment uses a barrier layer of a composite material formed by stacking N layers of materials with different phosphorus components, and the phosphorus content gradually increases from top to bottom. Experiments have shown that the corrosion rate of the quaternary material by the etching solution decreases with the increase of the phosphorus content. In this embodiment, the barrier layer with low phosphorus content is set on the upper layer, the barrier layer with high phosphorus content is set on the lower layer, and the barrier layer with the highest phosphorus content is used as the cut-off layer. In this way, when the above barrier layer is wet-etched, the corrosion depth can be accurately controlled, so that the step is not too low to achieve the effect, and the over-etching does not form side immersion.

[0063] Unless otherwise specified, the methods used in the embodiments of the present invention are conventional methods in the art.

[0064] The method for preparing the contact layer for SPAD of the present invention is described below through two specific embodiments.

[0065] Example 1

[0066] Reference Figure 2 , Figure 2 The process flow chart of dry etching of a contact layer having a three-level coaxial step symmetric structure (i.e., N=3) is shown, which specifically includes the following steps:

[0067] S11: Prepare the target epitaxial wafer, the upper layer of the wafer is 400nm thick, In 0.73 Ga 0.27 As0.63 P 0.37 Quaternary barrier 1, see Figure 2 (a);

[0068] S12: A layer of SiO with a thickness of 200 nm is deposited on the surface of the barrier layer 1 by using plasma enhanced chemical vapor deposition (PEVCD). 2 A dielectric film is formed to form a first mask layer 3, and a first mask window 31 is manufactured by photolithography and RIE method, see (b) of 1, and the degumming and cleaning are performed;

[0069] S13: Using ICP equipment to etch the barrier layer 1, controlling the depth to be 100 nm, to obtain a contact layer including the first step 111, see Figure 2 (c);

[0070] S14: Clean the surface of the first mask layer 3 and the contact layer, and deposit a layer of SiO with a thickness of 200 nm on the above surface by PECVD. 2 The dielectric film is formed into a second mask layer 4, and a second mask window 41 is made by photolithography and RIE; wherein the diameter of the second mask window 41 is 4 μm smaller than the diameter of the first mask window, see Figure 2 of (d);

[0071] S15: dry-etching the contact layer including the first step 111, controlling the depth to be 100 nm, to obtain a contact layer including the first step 111 and the second step 112, see Figure 2 of (e);

[0072] S16: Clean the surface of the second mask layer and the contact layer, and deposit a layer of SiO with a thickness of 200 nm on the above surface by PECVD. 2 The dielectric film is formed into a third mask layer 5, and a third mask window 51 is manufactured by photolithography and RIE. The diameter of the third mask window 51 is 4 μm smaller than the diameter of the second mask window 41. Figure 2 of (f);

[0073] S17: Dry-etching the contact layer including the first step 111 and the second step 112, controlling the depth to be 100 nm, to obtain a contact layer including the first step 111, the second step 112, and the third step 113, see Figure 2 of (g);

[0074] S18: Using a buffered oxide etchant (BOE) to remove all masks, a contact layer 100 having a three-level coaxial step symmetrical structure can be obtained. Figure 2 (h).

[0075] Example 2

[0076] Reference Figure 3 , Figure 3 The process flow chart of wet etching of a contact layer having a three-level coaxial step symmetric structure (i.e., N=3) is shown, which specifically includes the following steps:

[0077] S21: Prepare the target epitaxial wafer. The upper layer of the wafer is a barrier layer 1 of three different materials. From top to bottom, the first layer is a 100nm thick In 0.53 Ga 0.47 As barrier layer 11, the second layer is 100nm thick In 0.73 Ga 0.27 As 0.63 P 0.37 The barrier layer 12 and the third layer are 100 nm thick In 0.83 Ga 0.17 As 0.39 P 0.61 Barrier layer 13, see Figure 3 (a);

[0078] S22: Define the first window using photolithography, using H 2 SO 4 , H 2 O 2 and deionized water mixture (H 2 SO 4 , H 2 O 2 and deionized water in a molar mass ratio of 1:1:10) as the etching solution for In 0.53 Ga 0.47 The As barrier layer 11 is wet-etched for 10 seconds, and then the resin is removed and cleaned to obtain a contact layer including a first step 111;

[0079] S23: Define the second window by photolithography. The diameter of the second window is 4 μm smaller than the diameter of the first window. Use the etching solution in S2 to 0.73 Ga 0.27 As 0.63 P 0.37 The barrier layer 12 is wet-etched for 2 minutes, and then the resin is removed and cleaned to obtain a contact layer including a first step 111 and a second step 112;

[0080] S24: Define the third window by photolithography. The diameter of the third window is 4 μm smaller than that of the second window. Use the etching solution in S2 to 0.83 Ga 0.17 As 0.39 P 0.61The barrier layer 13 is wet-etched for 4 minutes, and then the resin is removed and cleaned to obtain a contact layer 100 including a first step 111, a second step 112, and a third step 113, that is, a contact layer 100 including a symmetrical structure of three coaxial steps, see Figure 3 (b).

[0081] In a third aspect, an embodiment of the present invention further provides a SPAD.

[0082] SPAD includes a cap layer and a contact layer arranged above the cap layer, wherein the contact layer is an N-level coaxial step-symmetrical structure formed by the upper surface of the barrier layer of the epitaxial wafer, which is gradually recessed from both sides to the middle; wherein N≥1, the interior of the cap layer has a larger curvature radius and ensures that the diffusion depth at the edge of the active area is less than that of the zinc diffusion morphology in the middle area.

[0083] The above-mentioned SPAD of the embodiment of the present invention has a zinc diffusion morphology in which the diffusion depth at the edge of the active area is smaller than that in the middle area and the curvature radius is larger. Since the diffusion depth at the edge of the active area of ​​the improved zinc diffusion morphology is smaller than that in the middle area, there is no edge enhancement effect, and thus the edge pre-breakdown can be effectively prevented; at the same time, the curvature radius of the improved zinc diffusion morphology is larger, which can enhance the lateral electric field component, thereby accelerating the lateral drift speed of photogenerated carriers in the absorption layer, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0084] In a fourth aspect, an embodiment of the present invention further provides a method for preparing a SPAD.

[0085] The preparation method comprises: adopting the above-mentioned preparation method for the contact layer of SPAD to prepare the contact layer; etching the barrier layer of the epitaxial wafer N times to obtain the contact layer; making a mask diffusion window on the surface of the contact layer, diffusing zinc to a target depth, and removing the mask.

[0086] Preferably, the specific steps of making a mask diffusion window on the surface of the contact layer include: depositing a dielectric film on the surface of the contact layer, and making a mask diffusion window by photolithography and RIE etching, wherein the diameter of the mask diffusion window is greater than or equal to the diameter of the mask window made before the first etching of the barrier layer, so that the diffusion area covers all steps, thereby maximally adjusting the edge curvature of the zinc diffusion morphology.

[0087] The preparation method of the SPAD of the present invention is described below through a specific example.

[0088] Example 3

[0089] Reference Figure 4 As shown, this embodiment is a method for preparing a SPAD including a contact layer having a three-level coaxial step symmetrical structure, and the specific steps are as follows:

[0090] S31: Prepare the contact layer 100 prepared in Example 1, see Figure 4 of (h);

[0091] S32: Depositing a layer of SiO on the surface of the contact layer 100 2 The dielectric film is used to obtain a diffusion mask 6, and a mask diffusion window 61 is made by photolithography and RIE etching; the diameter of the mask diffusion window 61 is greater than or equal to the diameter of the first mask window 31, and the adhesive is removed and cleaned, see Figure 4 of (i);

[0092] S33: Use metal organic chemical vapor deposition (MOCVD) to perform a zinc diffusion process to the target depth, and obtain a zinc diffusion morphology with a smaller diffusion depth at the edge of the active area than in the middle area and a larger curvature radius 7, see Figure 4 of (j);

[0093] S34: Use buffered oxide etching solution BOE to remove the diffusion mask and continue the subsequent process to obtain SPAD, see Figure 4 (k).

[0094] The performance of the SPAD obtained in Example 3 is compared with the performance of the SPAD obtained by conventional secondary zinc diffusion, as follows:

[0095] The thickness of the multiplication layer of the SPAD in Example 3 is controlled to be about 1 μm, and the horizontal electric field distribution of the above SPAD is simulated and calculated (the simulation calculation is completed by computer-aided design TCAD software, which is a conventional simulation technology in this field), and the simulation calculation diagram is as follows: Figure 5 shown.

[0096] Similarly, for the SPAD prepared by the traditional secondary zinc diffusion process, the thickness of its multiplication layer is also controlled to be about 1μm, and the horizontal electric field distribution of the above SPAD is simulated and calculated, and the simulation calculation diagram is as follows: Figure 6 shown.

[0097] from Figure 5 and Figure 6 It can be seen that compared with the traditional secondary zinc diffusion process, after completing the primary zinc diffusion using the contact layer of the present invention, the peak value of the electric field component in the horizontal direction increases by about 70%, thereby reducing the charge persistence effect, lowering the dark count rate, and obtaining a high-performance SPAD.

[0098] It can be seen that the present embodiment adopts the above method to prepare SPAD. Compared with the traditional method, not only the preparation method is simple, but also the zinc diffusion morphology with a smaller diffusion depth at the edge of the active area than that in the middle area and a larger curvature radius can be obtained. Since the diffusion depth at the edge of the active area of ​​the improved zinc diffusion morphology is smaller than that in the middle area, there is no edge enhancement effect, and thus the edge pre-breakdown can be effectively prevented; at the same time, the radius of curvature of the improved zinc diffusion morphology is larger, which can enhance the lateral electric field component, thereby accelerating the lateral drift speed of photogenerated carriers in the absorption layer, reducing the charge persistence effect, and reducing the dark count rate, thereby obtaining a high-performance SPAD.

[0099] Furthermore, the present invention is not limited to the above-mentioned embodiments. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention. Contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for preparing a contact layer for a single-photon avalanche photodiode SPAD, characterized in that: The contact layer is an N-level coaxial symmetrical step structure formed by the upper surface of the barrier layer of the epitaxial wafer being gradually recessed downward from both sides to the middle; wherein N≥3; The preparation method comprises: etching the barrier layer of the epitaxial wafer N times to obtain a contact layer; The preparation method specifically comprises the following steps: A mask window is formed on the surface of the barrier layer to etch the barrier layer to form a contact layer having a coaxially symmetrical step; The contact layer obtained each time is used as a barrier layer, and the above steps are repeated to make a mask window and etch until a contact layer containing N levels of coaxially symmetrical steps is formed; Wherein, the diameter of the latter mask window is smaller than the diameter of the previous mask window; The material of the barrier layer is In with different compositions. 1-x Ga x As y P 1-y A composite material formed by stacking up and down layers; wherein the y value gradually decreases from top to bottom, and the difference in y values ​​between two adjacent layers is ≥0.2; 0≤x≤1, 0≤y≤1.

2. The preparation method according to claim 1, characterized in that The specific step of making the mask window includes: directly defining the mask window on the surface of the blocking layer by photolithography; the specific step of etching the blocking layer includes: wet etching the blocking layer by using a mixed etching solution of H2SO4, H2O2 and deionized water.

3. A SPAD, characterized in that: The SPAD comprises a cap layer, and a contact layer disposed above the cap layer and prepared by the preparation method according to claim 1.

4. A method for preparing a SPAD as claimed in claim 3, characterized in that: The preparation method comprises: Etching the barrier layer of the epitaxial wafer N times to obtain a contact layer, wherein N ≥ 3; A mask diffusion window is made on the surface of the contact layer, zinc is diffused to a target depth, and the mask is removed.

5. The method for preparing a SPAD according to claim 4, characterized in that: The specific steps of making a mask diffusion window on the surface of the contact layer include: depositing a dielectric film on the surface of the contact layer, making a mask diffusion window by photolithography and reactive ion etching, and the diameter of the mask diffusion window is greater than or equal to the diameter of the mask window made before the first etching of the barrier layer.

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