A power-on protection circuit for a fan

Abstract

The present invention provides a power-on protection circuit for a wind turbine, comprising a first switch circuit, used to connect an external power supply, and turn on / off the first switch tube circuit through the polarity of the external power supply; an optocoupler delay circuit, electrically connected to the output end of the first switch circuit, and used to delay the current of the external power supply when the first switch circuit is turned on; a clock control circuit, electrically connected to the output end of the optocoupler delay circuit, and generating a level signal; a second switch circuit, electrically connected to the output end of the clock control circuit, and according to the level signal, the second switch circuit is turned on / off, and the wind turbine is powered on / off.

Description

Technical Field

[0001] The invention relates to the technical field of motor control, and in particular to a power-on protection circuit for a fan. Background Art

[0002] At present, electric fans are a kind of mechanical device that relies on electrical energy input, which is converted into motor rotation to drive the blades to output mechanical energy, increase gas pressure and deliver gas. It is composed of controller, motor, wind tube, blades and other structures, and is widely used in ventilation, exhaust, heat dissipation and cooling in various fields. Among various types of machinery and electrical equipment in various industries in my country, the motors matched with fans account for about 60% of the national motor installed capacity, and the electricity consumed accounts for about one-third of the total power generation in the country.

[0003] The motor is the power source of the fan, and the controller is the core part of the motor drive. The quality of its internal circuit design will directly affect the working performance of the fan.

[0004] Usually, simple fan controllers use direct power supply, and there is no power-on protection circuit inside. When the system is powered on, the bus capacitor is directly charged. The defect of this design method is that when the positive and negative polarities of the power supply are reversed, or when the voltage of reverse polarity is output due to a power supply system failure, the internal circuit will be affected due to the lack of a protection circuit, causing the polarity-sensitive components inside the controller to fail. At the same time, the charging current of the bus capacitor inside the controller is too large at the moment of power-on, causing fluctuations in the power consumption of the system, which can easily cause damage to other components and affect the overall performance of the controller. In some cases, after the system voltage is established, there will be a period of voltage fluctuations. Before the voltage stabilizes, the fluctuation will cause the bus capacitor to charge and discharge rapidly, and will also generate impact current, causing component failure. Some fan controllers will issue a buffered power-on instruction through the CPU control chip, and perform delayed conduction by collecting the bus capacitor voltage. The defect is slow response and long motor startup time. At the same time, it depends on the control instructions of the CPU. Once the CPU fails, the buffered power-on effect cannot be achieved, and it cannot be applied to products that prohibit software systems. Another part of the fan controller sets the delay time through the RC charge and discharge circuit. After the system is powered on, it delays for a certain period of time, turns on the power device, and restores the normal power supply of the system. The delay time of this solution is not accurate enough. The delay system composed of the RC circuit is easily affected by environmental factors, and the system stability is poor. The delay trigger is generated by the power supply, and the delay trigger condition cannot be controlled. At the same time, due to the discharge delay of the RC circuit when the power is turned off, the power tube is slowly closed when the power is turned off, and the discharge current flows through the power tube, which cannot play the role of reducing the discharge current for power-off protection. Summary of the invention

[0005] The present invention provides a power-on protection circuit for a fan, which is used to prevent components from being damaged by reverse polarity of power supply or by impact current generated at the moment of power-on, and the protection circuit operates normally.

[0006] The present invention provides a power-on protection circuit for a wind turbine, comprising:

[0007] The first switch circuit is used to connect to an external power supply and control the first switch circuit to be turned on / off according to the polarity of the external power supply;

[0008] An optocoupler delay circuit is electrically connected to the output end of the first switch circuit and is used to delay the current of the external power supply when the first switch circuit is turned on;

[0009] The clock control circuit is electrically connected to the output end of the optical coupler delay circuit and generates a level signal;

[0010] The second switch circuit is electrically connected to the output end of the clock control circuit. According to the level signal, the second switch circuit is turned on / off, and the fan is powered on / off.

[0011] In an optional embodiment of the present invention: the first switch circuit includes: a first NMOS tube, a first resistor, a second resistor, a first capacitor and a first voltage regulator diode; wherein,

[0012] The first resistor and the second resistor are connected in series between the positive and negative power supply electrodes of the external power supply, and the connecting portion of the first resistor and the second resistor is connected to the gate of the first NMOS tube;

[0013] The source and drain of the first NMOS tube are connected in series to the negative line of the power supply, the drain is at the front end of the negative line of the external power supply, and the source is at the rear end of the negative line of the external power supply;

[0014] The second resistor, the first capacitor and the first voltage-stabilizing diode are connected in parallel, and the anodes of the second resistor, the first capacitor and the first voltage-stabilizing diode are connected to the source of the first NMOS tube.

[0015] In an optional embodiment of the present invention: the optical coupler delay circuit includes: a third resistor, an optical coupler, and a fourth resistor; wherein,

[0016] The first end of the optocoupler input terminal is connected to the positive electrode of the external power supply through a third resistor;

[0017] The second end of the optical coupler input end is connected to the source of the first NMOS tube;

[0018] A first end of the optocoupler output terminal is connected to a negative electrode of an external power supply;

[0019] The second end of the optical coupler output end is connected to the secondary power supply through a fourth resistor.

[0020] In an optional embodiment of the present invention: the clock control circuit includes: a fifth resistor, a sixth resistor, a clock control chip, and a seventh resistor; wherein,

[0021] The reset terminal of the clock control chip is electrically connected to the second terminal of the optical coupler output terminal;

[0022] The ground terminal of the clock control chip is connected to the source of the first NMOS tube;

[0023] The set end of the clock control chip is electrically connected to the output end through a seventh resistor;

[0024] The power supply terminal of the clock control chip is connected to the secondary power supply;

[0025] The fifth resistor and the sixth resistor are connected in series between the secondary power supply and the source of the first NMOS tube, and the connected part of the fifth resistor and the sixth resistor is electrically connected to the voltage dividing end of the clock control chip.

[0026] In an optional embodiment of the present invention: the clock control circuit further includes: a second capacitor, wherein both ends of the second capacitor are connected between the secondary power supply and the source of the first NMOS tube.

[0027] In an optional embodiment of the present invention: the second switch circuit includes: an eighth resistor, a ninth resistor, a triode, a tenth resistor, an eleventh resistor, a second voltage stabilizing diode, a second NMOS transistor and a twelfth resistor; wherein,

[0028] The base of the transistor is electrically connected to one end of the eighth resistor and the ninth resistor, the other end of the eighth resistor is electrically connected to the output end of the clock control chip, and the other end of the ninth resistor is electrically connected to the source of the first NMOS tube;

[0029] The collector of the transistor is connected to the positive electrode of the power supply through the tenth resistor;

[0030] The emitter of the transistor is electrically connected to the source of the first NMOS transistor through an eleventh resistor;

[0031] The second voltage stabilizing diode is connected in parallel with the eleventh resistor, and the anode of the second voltage stabilizing diode is electrically connected to the source of the first NMOS tube;

[0032] The source of the second NMOS tube is electrically connected to the source of the first NMOS tube;

[0033] The gate of the second NMOS tube is connected to the emitter of the triode;

[0034] The drain of the second NMOS tube serves as the negative input electrode of the power circuit of the fan;

[0035] The twelfth resistor is connected in parallel between the drain and the source of the second NMOS tube.

[0036] In an optional embodiment of the present invention: the twelfth resistor is a power resistor.

[0037] The present invention has the following beneficial effects:

[0038] The control circuit of the present invention uses a pure hardware method to achieve reverse polarity and power-on surge current protection, reduces the surge current through a power resistor, delays the opening of a normal current path, accurately controls the power-on protection time, and simultaneously closes the current path when the power supply is reverse polarity to protect components such as busbar capacitors and avoid damage to the components. The advantages are that it does not require the participation of a CPU control chip, improves the response speed, reduces the complexity of the system, and meets the pure hardware application conditions; it can accurately control the delay time and delay trigger conditions, the delay time can be accurate to milliseconds, and the longest delay time can reach several hours, which can fully and reliably meet the use requirements; at the same time, it can achieve power-off protection, and the system stability is better.

[0039] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0040] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0042] Figure 1 The present invention is a circuit diagram of a power-on protection circuit for a wind turbine according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0044] The circuit of the present invention is a power-on protection circuit designed for the reverse polarity of power supply or excessive power-on impact current that may be generated when power is turned on. The circuit of the present invention includes a first switch circuit, which is used to connect an external power supply and control the first switch tube circuit to be turned on / off by the polarity of the external power supply; and control the disconnection and conduction of the external power supply. The optocoupler delay circuit is electrically connected to the output end of the first switch circuit, and is used to delay the current of the external power supply when the first switch circuit is turned on, and is used to reduce the current of the external power supply, thereby protecting the circuit components. The clock control circuit is electrically connected to the output end of the optocoupler delay circuit and generates a level signal; the second switch circuit is controlled by the level signal, thereby controlling the power on and off of the fan. The second switch circuit is electrically connected to the output end of the clock control circuit, and according to the level signal, the second switch circuit is turned on / off, and the fan is powered on / off. The output end of the second switch circuit is the negative input end of the fan circuit.

[0045] When the controller power supply is reverse polarity due to a fault in the onboard power system, the internal protection circuit takes effect, the power tube remains disconnected, and there is no current path in the internal circuit, which protects the controller's rear-end circuit. When the system is powered normally, after the anti-reverse power tube is turned on, the current first flows through the power resistor to charge the capacitor. At this time, the impact current is small. After a certain delay, the capacitor is charged and the onboard power supply system is stable. The power tube is turned on to restore normal power supply. This circuit prevents the power-on impact current from being too large and causing the remaining circuits to fail.

[0046] Circuit diagram Figure 1As shown, the power-on protection circuit part includes a first NMOS tube Q1, a second NMOS tube Q2, a power resistor R12, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first voltage zener diode D1, a second voltage zener diode D2, a first capacitor C1, a second capacitor C2, an optocoupler U1 and a clock control chip U2 The first resistor R1 and the second resistor R2 are connected in series between the positive and negative electrodes of the power supply, the connected part of the first resistor R1 and the second resistor R2 is connected to the gate electrode (G electrode) of the first NMOS tube Q1, the source electrode (S electrode) and the drain electrode (D electrode) of the first NMOS tube are connected in series to the negative line of the power supply, and the drain electrode is at the front end of the negative line of the power supply (power supply end), and the source electrode is at the rear end of the negative line of the power supply (power circuit end), the first capacitor C1, the first voltage stabilizing diode D1 and the second resistor R2 are connected in parallel, and the positive electrode thereof is connected to the source electrode (S electrode) of the first NMOS tube Q1. The first end of the input end of the photoelectric coupler U1, that is, the primary side 1 pin, is connected to the positive electrode of the power supply through the third resistor R3, the second end of the input end, that is, the primary side 2 pin, is connected to the source electrode (S electrode) of the first NMOS tube Q1, the first end of the output end of the photoelectric coupler U1, that is, the secondary side 3 pin, is connected to the negative electrode of the power supply, and the second end of the output end, that is, the secondary side 4 pin, is connected to the secondary power supply 5V through the fourth resistor R4. Pin 1 (reset end) of the clock control chip U2 is connected to pin 4 (the second end of the output end) of the secondary side of the photocoupler U1; pin 2 (ground end) of the connected clock control chip U2 is connected to the source (S pole) of Q1, pin 3 (set end) is connected to pin 6 (output end) of the clock control chip U2 through the seventh resistor R7, pin 5 (power supply end) of U2 is connected to the secondary power supply 5V, the fifth resistor R5 and the sixth resistor R6 are connected in series between the secondary power supply 5V and the source (S pole) of the first NMOS tube Q1, the connected part of the fifth resistor R5 and the sixth resistor R6 is connected to pin 4 (voltage divider end) of the clock control chip U2, and the two ends of the second capacitor C2 are connected between the secondary power supply 5V and the source (S pole) of the first NMOS tube Q1. The base (B pole) of the transistor N1 is connected to one end of the eighth resistor R8 and the ninth resistor R9, the other end of the eighth resistor R8 is connected to the 6th pin (output end) of the clock control chip U2, and the other end of the ninth resistor R9 is connected to the source (S pole) of the first NMOS tube Q1; the collector (C pole) of the transistor N1 is connected to the positive pole of the power supply through the tenth resistor R10; the emitter (E pole) of the transistor N1 is connected to the source (S pole) of the first NMOS tube Q1 through the eleventh resistor R11, and the second voltage stabilizing diode D2 is connected in parallel with the eleventh resistor R11, and its positive pole is connected to the source (S pole) of the first NMOS tube Q1.The source (S pole) of the second NMOS tube Q2 is connected to the source (S pole) of the first NMOS tube Q1, the gate (G pole) of the second NMOS tube Q2 is connected to the emitter (E pole) of the transistor N1, and the drain (D pole) of the second NMOS tube Q2 is used as the negative pole output of the rear pole power circuit. The twelfth resistor R12, i.e., the power resistor, is connected in parallel between the drain (D pole) and the source (S pole) of the second NMOS tube Q2.

[0047] When the external power supply polarity is correct, the first NMOS tube Q1 is not turned on, and the current on the negative line flows through the parasitic diode of the first NMOS tube Q1 to form a path. The source (S pole) of the first NMOS tube Q1, that is, GND, establishes a 28V voltage with the positive pole of the power supply. The R1 and R2 resistors divide the 28V voltage. At this time, the potential between the source (S pole) and the drain (D pole) of Q1 is approximately equal, but a large current cannot pass. The voltage between the gate (G pole) and the source (S pole) of Q1 makes Q1 turn on. After Q1 is turned on, the source (S pole) and the drain (D pole) are approximately short-circuited, and the current can flow normally. At the same time, the 28V voltage of the primary side of the optocoupler U1 is established, generating a primary current, turning on the optocoupler secondary transformer, and the 4th pin of the optocoupler secondary transformer changes from the 5V level to the 0V level, generating a falling edge, which triggers the 1st pin of the clock control chip U2 to start delay timing. The precise delay time is determined by the resistance values ​​of resistors R5, R6, and R7. Before the delay is reached, there is no voltage output from the 6th pin of the clock control chip, the transistor collector (C) and emitter (E) are not conducting, there is no voltage between the gate (G) and source (S) of the NMOS tube Q2, and the source (S) and drain (D) are approximately disconnected, so the current generated by charging the power system flows through the power resistor R12 to form a loop. In the period before the delay is reached, the fluctuation of the system voltage will generate charging and discharging current due to the existence of the bus capacitor. If it does not flow through the power resistor, the current can reach hundreds of amperes. After selecting a power resistor with a suitable resistance value, the power-on and charging and discharging currents will be significantly reduced, which can be reduced to less than 1A, thus protecting the controller. After the delay is over, the capacitor voltage is stable. At this time, the 6th pin of the clock control chip outputs a high level, and a voltage is generated between the base (B pole) and the emitter (E pole) of the transistor, so that the collector (C pole) and the emitter (E pole) are turned on, and a voltage is established between the gate (G pole) and the source (S pole) of the NMOS tube Q2, and the source (S pole) and the drain (D pole) are turned on, short-circuiting the power resistor R12, providing a normal path for the current, and completing safe power-on.

[0048] When the system is powered off, the secondary power supply 5V disappears, there is no voltage output at pin 6 of the clock control chip U2, there is no conduction between the collector (C pole) and the emitter (E pole) of the transistor, there is no voltage between the gate (G pole) and the source (S pole) of the NMOS tube Q2, and the source (S pole) and the drain (D pole) are almost open circuited. The current generated by the discharge of the bus capacitor can flow through the power resistor R12 to form a discharge circuit in the first time.

[0049] When the external power supply has reverse polarity, the parasitic diode of Q1 does not conduct and a loop cannot be formed. No current flows through the voltage-dividing resistors R1 and R2, and no voltage can be provided to the G pole of Q1. Q1 does not conduct, which is equivalent to an open circuit. The reverse polarity voltage will not be loaded to both ends of the rear-pole power circuit, thereby protecting the circuit.

[0050] Among them, Q1 and Q2 in the scheme are MOS tubes, and other devices such as IGBT, SiC, electronic relays, etc. can also realize this function. U2 in the scheme is the clock control chip LTC6995, and other clock control chips can also realize this function. In the scheme, the delay trigger method adopts the level change of the 4th pin of the optocoupler auxiliary transformer, and other level change generation circuits can also realize this function.

[0051] The present invention uses a pure hardware method to implement the power-on protection circuit of the fan controller. The circuit protects the polarity sensitive device, and at the same time, the delay short-circuit power resistor is used to limit the magnitude of the instantaneous impact current of power-on to avoid device failure. At the same time, the pure hardware method does not require the participation of the CPU control chip, which significantly improves the response speed of the controller, and has independence, does not rely on the control instructions of the CPU, is not easily interfered, reduces the system complexity, and has a low failure rate; different from the RC charging slow power-on circuit, the circuit has a precise delay time, and can be controlled by the trigger logic (START-TIMER), is not easily affected by environmental factors, improves the stability of the system, and the delay time can be accurate to milliseconds. The longest delay time can reach several hours, and the delay is more flexible, which can fully and reliably meet the use requirements; and it can realize power-off protection, and the current size of the bus capacitor discharge during power-off can be reduced by the power resistor in the first time.

[0052] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A power-on protection circuit for a wind turbine, characterized in that: include: The first switch circuit is used to connect to an external power supply and control the first switch circuit to be turned on / off according to the polarity of the external power supply; An optocoupler delay circuit is electrically connected to the output end of the first switch circuit and is used to delay the current of the external power supply when the first switch circuit is turned on; The clock control circuit is electrically connected to the output end of the optical coupler delay circuit and generates a level signal; A second switch circuit is electrically connected to the output end of the clock control circuit, and according to the level signal, the second switch circuit is turned on / off, and the fan is powered on / off; The first switch circuit comprises: a first NMOS transistor (Q1), a first resistor (R1), a second resistor (R2), a first capacitor (C1) and a first voltage regulator diode (D1); wherein, A first resistor (R1) and a second resistor (R2) are connected in series between the positive and negative electrodes of an external power supply, and a connecting portion of the first resistor (R1) and the second resistor (R2) is connected to a gate of a first NMOS transistor (Q1); The source and drain of the first NMOS tube (Q1) are connected in series to the negative line of the power supply, the drain is at the front end of the negative line of the external power supply, and the source is at the rear end of the negative line of the external power supply; The second resistor (R2), the first capacitor (C1) and the first voltage stabilizing diode (D1) are connected in parallel, and the anodes of the second resistor (R2), the first capacitor (C1) and the first voltage stabilizing diode (D1) are connected to the source of the first NMOS tube (Q1); The optical coupler delay circuit comprises: a third resistor (R3), a photoelectric coupler (U1), and a fourth resistor (R4); wherein, A first end of the input terminal of the photocoupler (U1) is connected to the positive electrode of the external power supply through a third resistor (R3); The second end of the input end of the photoelectric coupler (U1) is connected to the source of the first NMOS tube (Q1); A first end of the output terminal of the photocoupler (U1) is connected to the negative electrode of the external power supply; The second end of the output end of the photocoupler (U1) is connected to the secondary power supply through a fourth resistor (R4); The clock control circuit comprises: a fifth resistor (R5), a sixth resistor (R6), a clock control chip (U2), and a seventh resistor (R7); wherein, The reset end of the clock control chip (U2) is electrically connected to the second end of the output end of the photoelectric coupler (U1); The ground terminal of the clock control chip (U2) is connected to the source of the first NMOS tube (Q1); The set end of the clock control chip (U2) is electrically connected to the output end through a seventh resistor (R7); The power supply terminal of the clock control chip (U2) is connected to the secondary power supply; The fifth resistor (R5) and the sixth resistor (R6) are connected in series between the secondary power supply and the source of the first NMOS tube (Q1), and the connected part of the fifth resistor (R5) and the sixth resistor (R6) is electrically connected to the voltage dividing end of the clock control chip (U2).

2. A power-on protection circuit for a wind turbine as claimed in claim 1, characterized in that: The clock control circuit also includes: a second capacitor (C2), wherein two ends of the second capacitor (C2) are connected between the secondary power supply and the source of the first NMOS tube (Q1).

3. A power-on protection circuit for a wind turbine as claimed in claim 1, characterized in that: The second switch circuit includes: an eighth resistor (R8), a ninth resistor (R9), a transistor (N1), a tenth resistor (R10), an eleventh resistor (R11), a second voltage stabilizing diode (D2), a second NMOS transistor (Q2) and a twelfth resistor (R12); wherein, The base of the triode (N1) is electrically connected to one end of an eighth resistor (R8) and a ninth resistor (R9), the other end of the eighth resistor (R8) is electrically connected to the output end of a clock control chip (U2), and the other end of the ninth resistor (R9) is electrically connected to the source of the first NMOS tube (Q1); The collector of the transistor (N1) is connected to the positive electrode of the power supply through the tenth resistor (R10); The emitter of the transistor (N1) is electrically connected to the source of the first NMOS transistor (Q1) through an eleventh resistor (R11); The second voltage stabilizing diode (D2) is connected in parallel with the eleventh resistor (R11), and the anode of the second voltage stabilizing diode (D2) is electrically connected to the source of the first NMOS transistor (Q1); The source of the second NMOS transistor (Q2) is electrically connected to the source of the first NMOS transistor (Q1); The gate of the second NMOS tube (Q2) is connected to the emitter of the transistor (N1); The drain of the second NMOS tube (Q2) serves as the negative input electrode of the power circuit of the fan; The twelfth resistor (R12) is connected in parallel between the drain and the source of the second NMOS transistor (Q2).

4. A power-on protection circuit for a wind turbine as claimed in claim 3, characterized in that: The twelfth resistor (R12) is a power resistor.

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