Method for identifying leakage paths between source and drain of a transistor, from source and drain to body, and storage device

Abstract

The application discloses a method for identifying a leakage path between source and drain of a transistor, between source and drain and a body of the transistor, and the method comprises the following steps: extracting and setting parameters to measure the number of floating gates in the leakage path to evaluate the leakage risk degree between the source and the drain of the transistor; connecting the controlled gate of the leakage path with the body of the target transistor in the test process, and extracting and using the number of the controlled gate to evaluate the leakage risk degree from the source and the drain to the body. The application also provides a storage device capable of identifying the leakage path between the source and the drain of the transistor and / or between the source and the drain and the body of the transistor by using the above method. The application can comprehensively extract the leakage path, and extract the number of the controlled gate and the number of the floating gate in the leakage path as important indexes for evaluating the risk degree of the leakage path, quantitatively represent the risk degree of the leakage path, so as to help selecting the transistor in the chip test and analyzing the abnormal value of the transistor test data.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing, and specifically relates to a method and a storage device for identifying leakage paths between the source and drain of a transistor and from the source and drain to the body. Background Technology

[0002] In the design process of test chips based on the front-end and mid-end process layers of product chips, a large number of field-effect transistors (FETs) in the product chip need to be connected to pads through vias and metal layers. Outliers in electrical test data are then used to analyze defects in the process flow. During the selection and testing of FETs, it is necessary to eliminate the influence of leakage paths between the drain / gate / source / body terminals of the device itself on the test results. Existing technologies have limited ability to extract leakage path information between the source and drain of the target transistor and from the source / drain to the body. Identifying leakage paths between the source and drain of the target transistor and from the source / drain to the body requires complex calculations, and it is also impossible to determine the number of dummy gates (floating gates) traversed in the leakage path, thus hindering further assessment of the hazard level of the leakage path. Summary of the Invention

[0003] In view of all or part of the deficiencies of the prior art described above, the purpose of this invention is to provide a method for identifying leakage paths between the source and drain of a transistor and from the source and drain to the body. This method can effectively identify leakage paths between the source and drain of a transistor and from the source and drain to the body, which can help in the selection of test transistors in a chip, facilitate the analysis of abnormal values ​​in subsequent transistor test data, and provide a corresponding storage device.

[0004] To achieve some or all of the above objectives, the present invention provides the following technical solutions:

[0005] A method for identifying leakage paths between the source and drain of a transistor includes the following steps:

[0006] Step 1: Obtain the layout. Based on the circuit connection relationship in the layout, obtain the circuit path from the source to the drain of the target transistor, denoted as loop _n (n=1, 2, 3...).

[0007] Step 2: In the loop_n, identify loop_n with floating gates in the circuit path, denoted as loop_i (i=1, 2, 3...). Determine that loop_i is a leakage path between the source and drain of the target transistor, i.e., there is a leakage risk. The number of floating gates in loop_i is negatively correlated with the leakage risk. The leakage path refers to a circuit path with leakage risk.

[0008] Preferably, a screening step 1.1 is included between step 1 and step 2:

[0009] When there are multiple source-to-drain circuit paths above the target transistor, the shortest circuit path is selected and denoted as loop_up_n (n=x).

[0010] When there are multiple source-to-drain circuit paths below the target transistor, the shortest circuit path is selected and denoted as loop_down_n (n=x).

[0011] After performing step 1.1, the loop _n in step two refers to the loop _up_n (n=x) and / or the loop _down_n (n=x).

[0012] In step two, the leakage risk of the leakage path between the source and drain of the target transistor is determined based on loop_i, as follows:

[0013] The loop_i is circular, and the closed area in the middle of the circular loop_i is denoted as loop_holes; risk parameters n1, n2, n3 and N are defined to characterize the leakage risk of the loop_i;

[0014] All gates in contact with the loop holes are denoted as loopgates, and a risk parameter n1 is defined to characterize the number of loopgates;

[0015] The gate of the target transistor in the loopgate is denoted as agate_except, and the risk parameter n2 is defined to characterize the number of agate_except.

[0016] The controlled gates in the loopgate other than agate_except are denoted as agate_control. The controlled gates refer to the gates that perform input / output control. The risk parameter n3 is defined to characterize the number of agate_controls. Generally, the controlled gates refer to the gates that perform input / output control by connecting lines, such as connecting lines such as M0P, V0, M1 to the pads.

[0017] The gates in the loopgate other than agate_except and agate_control are denoted as floating gates, and the risk parameter N is defined to characterize the number of floating gates that loop_i passes through, i.e. N = n1 - n2 - n3;

[0018] Loop_i that satisfies N > 0 and n3 = 0 has leakage risk, which is the leakage path between the source and drain of the target transistor. The magnitude of N is negatively correlated with the leakage risk, that is, the fewer the number of floating gates, the higher the leakage risk.

[0019] Risk parameters sdleakagepath, sdleakagedummygate_up, sdleakagecontrolgate_up, sdleakagedummygate_down, and sdleakagecontrolgate_down are defined to characterize the leakage risk of the target transistor. Specifically, sdleakagepath is the sum of n1 values ​​of the leakage paths between the source and drain of the target transistor, used to characterize whether there is a leakage path between the source and drain of the target transistor. 0 indicates that there is no leakage path, and other values ​​indicate that there is a leakage path.

[0020] The value of N for the leakage path between the source and drain above the target transistor is sdleakagedummygate_up, which is used to characterize the number of floating gates traversed by the leakage path between the source and drain above the target transistor.

[0021] The sdleakagecontrolgate_up is the value of n3 of the leakage path between the source and drain above the target transistor, which is used to characterize the number of controlled gates traversed by the leakage path between the source and drain above the target transistor.

[0022] The value of N for the leakage path between the source and drain below the target transistor is sdleakagedummygate_down, which is used to characterize the number of floating gates traversed by the leakage path between the source and drain below the target transistor.

[0023] The value of n3, where sdleakagecontrolgate_down is the source-drain leakage path below the target transistor, is used to characterize the number of controlled gates traversed by the source-drain leakage path below the target transistor.

[0024] A method for identifying the leakage path from the source / drain to the body of a transistor, comprising the following steps:

[0025] Step 1: Obtain the layout. Based on the circuit connection relationship in the layout, obtain the circuit path from the source to the drain of the target transistor, denoted as loop_n (n=1, 2, 3...). The loop_n is circular, and the closed area in the middle of the circular loop_n is denoted as loop_holes.

[0026] All gates that come into contact with the loop holes are denoted as loopgate;

[0027] The gate of the target transistor in the loopgate is denoted as agate_except;

[0028] The controlled gate in the loopgate, excluding the agate_except gate, is denoted as agate_control. The controlled gate refers to the gate that performs input / output control. Generally, the controlled gate refers to the gate that performs input / output control by connecting lines, such as connecting lines such as M0P, V0, and M1 to the pad.

[0029] The gates in the loopgate other than agate_except and agate_control are referred to as floating gates;

[0030] Step 2: Divide loop_n into several loop_remain segments by using agate_except and agate_control. The loop_remain segment that contacts the left side of agate_except is denoted as loop_lef, and the loop_remain segment that contacts the right side of agate_except is denoted as loop_right.

[0031] The connection line used to connect the active area is denoted as M0A;

[0032] The MOA that is in contact with the loop_left is denoted as MOA_loop_left, and the agate_control that is connected to the MOA_loop_left is denoted as agate_sd_left; and a risk parameter n4 is defined to represent the number of agate_sd_left;

[0033] The MOA that is in contact with the loop_right is denoted as MOA_loop_right, and the agate_control that is connected to the MOA_loop_right is denoted as agate_sd_right; and a risk parameter n5 is defined to represent the number of agate_sd_right;

[0034] If n4 > 0, it is determined that the target transistor has a leakage path from its left side (source / drain) to the body.

[0035] If n5 > 0, then the target transistor is determined to have a leakage path from its right side (source / drain) to the body.

[0036] Risk parameters n6 and n7 are also defined to characterize the number of floating gates traversed by the drain path from the source / drain to the body of the target transistor:

[0037] The number of agate_controls that are in contact with the loop_left, excluding agate_sd_left, agate_sd_right and agate_except, that is, the number of floating gates that the leakage path from the left side (source / drain) of the target transistor passes through, is denoted as the value of n6. The smaller the value of n6, the higher the risk of leakage.

[0038] The number of agate_controls that are in contact with the loop_right, excluding agate_sd_left, agate_sd_right, and agate_except, that is, the number of floating gates that the leakage path from the right side (source / drain) of the target transistor passes through, is denoted as the value of n7. The smaller the value of n7, the higher the risk of leakage.

[0039] Preferably, in step 1, after obtaining the circuit path from the source to the drain of the target transistor, a screening step 1.1 is also performed:

[0040] When there are multiple source-to-drain circuit paths above the target transistor, the shortest circuit path is selected and denoted as loop_up_n;

[0041] When there are multiple source-to-drain circuit paths below the target transistor, the shortest circuit path is selected and denoted as loop_down_n.

[0042] After performing step 1.1, loop_n (n=1, 2, 3...) in step 1 refers to loop_up_n and / or loop_down_n.

[0043] Define risk parameters llktoloopgate_up, llktoloopgate_down, rlktoloopgate_up, and rlktoloopgate_down to characterize the number of floating gates in the source-drain-to-body leakage path located at the top left, bottom left, top right, and bottom right of the target transistor, respectively, representing the values ​​of n8, n9, n10, and n11.

[0044] The present invention also provides a method for identifying a transistor leakage path, comprising identifying: a leakage path between the transistor source and drain, a leakage path from the transistor source and drain to the body, and a leakage path from the transistor gate to the body; wherein the leakage path between the transistor source and drain is implemented using the above-described method for identifying the leakage path between the transistor source and drain, and / or the method for identifying the leakage path from the transistor source and drain to the body includes the above-described method for identifying the leakage path from the transistor source and drain to the body.

[0045] Furthermore, the method for identifying the leakage path from the source / drain to the body of the transistor includes the following steps:

[0046] Step 1: Obtain the layout, which includes an active area layer and an active area connection layer. The graphic of the active area layer is the active area, denoted as AA; the graphic of the active area connection layer is the active area connection line, denoted as M0A, used to connect the active areas.

[0047] Step 2: Cut along the gate of the target transistor and cut the AA where the target transistor is located to obtain several AA sub-regions, which are denoted as dif_not_seed; According to the connection relationship between the layers, identify the dif_not_seed that is connected to the body electrode of the target transistor through the MOA, and denot it as err_path1;

[0048] Step 3: Define the risk parameter c1 to represent the number of err_path1; when c1 = 0, it is determined that the target transistor does not have a source / drain to body leakage path; when c1 > 0, it is determined that the target transistor has a source / drain to body leakage path.

[0049] By cutting off the active region (AA) of the target transistor, the system searches for AA sub-regions (err_path1) containing leakage paths (connected to the body of the target transistor via M0A). If the number of AA sub-regions with leakage paths is greater than 0, it is determined that the target transistor has a source / drain to body leakage path. The source-drain to body leakage path of the target transistor refers to both source-to-body and drain-to-body leakage paths. Here, a leakage path refers to a circuit path with a risk of leakage.

[0050] Based on the circuit connection relationship in the layout, identify the circuit path from the source / drain to the body of the target transistor, denoted as err_path1_hole; and denot the floating gate through which the err_path1_hole passes as err_path1_dumgate. The floating gate refers to a gate without external connection lines for input / output control.

[0051] A risk parameter c2 is defined to represent the number of err_path1_holes connected to err_path1, and a risk parameter c3 is defined to represent the number of err_path1_dumgates connected to err_path1. Risk parameters c1, c2, and c3 are used to quantify the leakage risk of a source / drain to body circuit path in the target transistor: when c1 > 0 and c1 = c2, it indicates that the target transistor has a source / drain to body leakage path, and the leakage path passes through c3 floating gates. The smaller the value of c3, the higher the risk of the source / drain to body leakage path in the target transistor. When c1 > 0 and c1 > c2, it indicates that the target transistor has a source / drain to body leakage path, and this leakage path is a direct connection from the source / drain to the body via a MOA, without passing through a floating gate. In this case, the leakage path risk is the highest.

[0052] The location of the circuit path from the source / drain to the body of the target transistor is characterized using parameter quantization. The minimum number of floating gates traversed in the circuit path from the source / drain to the body of the target transistor located to the right of the target transistor is also quantified using parameter quantization, as is the number of circuit paths from the source / drain to the body of the target transistor located to the right of the target transistor that traverse the minimum number of floating gates. Similarly, the minimum number of floating gates traversed in the circuit path from the source / drain to the body of the target transistor located to the left of the target transistor is also quantified using parameter quantization, as is the number of circuit paths from the source / drain to the body of the target transistor located to the left of the target transistor that traverse the minimum number of floating gates. Adding additional parameters to characterize the details of the target transistor, used for risk assessment, can aid in the selection of test transistors in the chip, and in the subsequent analysis of outliers in transistor test data. It can also provide information for subsequent layout verification.

[0053] Furthermore, the method for identifying the leakage path from the transistor gate to the body includes the following steps: Step 1: Obtaining a layout, the layout including at least a polysilicon interconnect layer, a via layer, an interconnect layer, and a polysilicon layer; wherein, the pattern of the polysilicon interconnect layer is denoted as M0P, used to connect the polysilicon layer; the pattern of the interconnect layer is denoted as M1; the pattern of the via layer is denoted as V0, used to connect M0 and M1; M0 includes M0P and M0A, and the pattern of the active region interconnect layer is denoted as M0A, used to connect the active region;

[0054] Based on the connection relationship between layers, M0P, V0 and M1 that are connected to the gate of the target transistor are identified, and the M0P, V0 and M1 are merged to obtain a graphic and denoted as seed_conn;

[0055] Step 2: Based on the circuit connection relationship in the layout, obtain the circuit path connected to the body of the target transistor, identify the circuit path that is connected to the seed_conn and record it as the leakage path from the gate to the body of the target transistor, and determine that there is a risk of leakage.

[0056] The beneficial effect of this technical solution is that it can fully obtain the leakage path from the transistor gate to the body based on the layout information in the early stage of chip design, identify the number of leakage paths, and assess the leakage risk of the transistor.

[0057] The method for identifying the leakage path from the gate to the body of a transistor also identifies the floating gates and their number traversed by the leakage path from the gate to the body of the target transistor; the floating gate refers to a gate without external leads for input / output control.

[0058] The method for identifying leakage paths from the gate to the body of a transistor uses the number of floating gates traversed by the leakage path as an indicator to characterize the leakage risk of the leakage path; the fewer floating gates the leakage path traverses, the higher the leakage risk. This technical solution uses the number of floating gates as an indicator to evaluate the leakage risk of a leakage path, quantitatively characterizing the leakage risk of each leakage path.

[0059] Furthermore, vector parameters are used to characterize the overall leakage current risk from the gate to the body of the target transistor. Specifically, the vector parameters { are defined. <m1> ， <m2>,…,<Mi-1>, }, where i is a positive integer not less than 1, the Let Mi be the i-th leakage path from the gate to the body of the target transistor, and its value is the number of floating gates traversed by the i-th leakage path. The advantage of this technical solution is that the vector parameter M intuitively represents the number of leakage paths from the gate to the body of the target transistor, and the number of floating gates traversed by each leakage path, i.e., the leakage risk of each leakage path. This reflects the overall leakage risk from the gate to the body of the target transistor from two dimensions: the number of leakage paths and the leakage risk of each leakage path.

[0060] The method for identifying the gate-to-body leakage path of a transistor can also define a parameter m as an indicator characterizing the overall leakage risk, where m represents the minimum number of floating gates traversed in the leakage path from the gate to the body of the i target transistors, i.e., the { <m1> ， <m2>,…,<Mi-1>, The minimum value of Mi in} represents the number of floating gates traversed by the gate-to-body leakage path with the highest leakage risk.

[0061] The method for identifying gate-to-body leakage paths of transistors can also define a parameter n as an indicator characterizing the overall leakage risk, where n represents the number of leakage paths among the i target transistor gate-to-body paths that pass through the minimum number of floating gates, i.e., the { <m1> ， <m2>,…,<Mi-1>, The number of occurrences of the minimum value in the array indicates the number of leakage paths with the highest leakage risk.

[0062] A storage device has a plurality of instructions stored therein, the plurality of instructions being adapted to be loaded by a processor and execute the method of identifying a leakage path between source and drain of a transistor described above and / or the plurality of instructions being adapted to be loaded by a processor and execute the method of identifying a leakage path from source and drain to body of a transistor described above.

[0063] Compared with the prior art, the present application has at least the following beneficial effects:

[0064] 1. The present application can comprehensively extract the leakage path between source and drain and the leakage path from source and drain to body caused by the circuit path between source and drain, and extract the number of controlled gates and the number of floating gates in the leakage path as important indicators for evaluating the risk degree of the leakage path, quantitatively represent the risk degree of the leakage path, help select the transistor for testing in the chip, and analyze the abnormal values of the transistor test data.

[0065] The method for identifying a leakage path of a transistor can comprehensively identify the leakage paths between source and drain, from source and drain to body, and from gate to body of the transistor, and comprehensively represent the leakage risk of the transistor.

[0066] 2. The present application can comprehensively extract the leakage path from source and drain to body of a transistor, extract the number of floating gates passed by the leakage path as an important indicator for evaluating the risk degree of the leakage path, quantitatively represent the risk degree of the leakage path, help select the transistor for testing in the chip, and analyze the abnormal values of the transistor test data; the present application can be automatically applied to the extraction of the leakage path from source and drain to body of a transistor in a layout file, and automatically generate a risk prompt, which is helpful for the design program of the test chip. 3. The method for identifying a leakage path from gate to body of a transistor provided by the present application acquires the leakage path from gate to body of a target transistor according to layout information, takes the number of floating gates passed by the leakage path as an indicator for evaluating the leakage risk of the leakage path, and quantitatively represents the leakage risk of each leakage path. The method for identifying a leakage path from gate to body of a transistor provided by the present application further represents the overall leakage risk of the target transistor from gate to body by setting a vector parameter, and directly evaluates the overall leakage risk level according to the values of m and n. The overall leakage risk level of the transistor can be used as a reference basis when selecting a transistor for testing in a chip, and can be used as a reference when analyzing abnormal values of transistor test data. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings needed to be used in the following embodiment description will be briefly introduced. Obviously, the drawings described below are only some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0068] Figure 1 and Figure 2 A schematic diagram of a method for identifying a leakage path between source and drain of a transistor in Embodiment One of the present application;

[0069] Figure 3 and Figure 4 A schematic diagram of a method for identifying a leakage path from source and drain to body of a transistor in Embodiment Two of the present application;

[0070] Figure 5 A flow chart of a method for identifying a leakage path from source and drain to body of a transistor provided in Embodiment Five of the present application;

[0071] Figure 6 A leakage path of Source / Drain to Body in Embodiment Six of the present application;

[0072] Figure 7 A leakage path of Source / Drain to Body in Embodiment Six of the present application;

[0073] Figure 8 A leakage path of Source / Drain to Body in Embodiment Seven of the present application;

[0074] Figure 9 A flow chart of a method for identifying a leakage path from gate to body of a transistor in Embodiment Nine of the present application;

[0075] Figure 10 A schematic diagram of seed_conn of a target transistor in Embodiment Nine of the present application;

[0076] Figure 11 A zoomed-in view of A in Figure 10 DETAILED DESCRIPTION

[0077] The technical solutions in the specific embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort also belong to the protection scope of the present application.

[0078] Embodiment One ​

[0079] In combination Figure 1 And Figure 2 As shown in the embodiment of the method for identifying the leakage path between the source and drain of the transistor, step 1: Obtain the layout, and according to the circuit connection relationship between the layers in the layout, obtain the circuit path from the source to the drain of the target transistor, denoted as loop_n, in this embodiment, there are loop_1 and loop_2; Step 2: In the loop_n, identify the loop_n in which the floating gate exists in the circuit path, denoted as loop_i, (such as Figure 1 The arrow direction in the middle) Determine that the loop_i is the leakage path between the source and drain of the target transistor, that is, there is a risk of leakage, and the number of floating gates in the loop_i is negatively correlated with the risk of leakage.

[0080] Perform the screening step 1.1, and screen the shortest circuit path above the target transistor, denoted as loop_up_i, and screen the shortest circuit path above the target transistor, denoted as loop_down_i.

[0081] As shown in Figure 2 In step two, according to the loop_i, determine the risk of leakage of the leakage path between the source and drain of the target transistor, specifically as follows:

[0082] After digging the loop_i, the intermediate loop_holes are obtained, all gates are defined as agate, all gates in contact with the loop_holes are defined as loopgate, and the loopgate in contact with the target transistor gate (G) is defined as agate_except. The loopgate in contact with the target transistor gate (G) is defined as agate_except. The loopgate in contact with the target transistor gate (G) is defined as agate_control. The number n1 / n2 / n3 of loopgate / agate_except / agate_control in contact with loop_holes is transmitted as a parameter into the gate pattern of the target transistor, (n1-n2-n3) represents the number of floating gates in the leakage path of the target transistor Source to Drain, n3 represents the number of controlled gates in the leakage path of the target transistor Source to Drain, when ((n1-n2-n3)>0) and (n3=0), it is proved that the target transistor has a Source to Drain leakage path and no controlled gate is connected out, which is easy to cause abnormal test data. And the smaller the value of (n1-n2-n3) is, the fewer the number of floating gates in the Source to Drain leakage path is, and the higher the risk of leakage is.

[0083] The parameters are set to characterize the source-to-drain leakage path risk level of the target transistor:

[0084] `sdleakagepath` indicates whether the target transistor has a source-to-drain leakage path; 0 indicates no leakage, and other values ​​indicate its presence. In this embodiment, `sdleakagepath = 2`.

[0085] `sdleakagedummygate_up` represents the number of floating gates traversed in the Source-to-Drain leakage path above the target transistor. In this embodiment, `sdleakagedummygate_up = 4`.

[0086] `sdleakagecontrolgate_up` represents the number of controlled gates in the Source-to-Drain path above the target transistor. In this embodiment, `sdleakagecontrolgate_up = 1`.

[0087] `sdleakagedummygate_down` represents the number of floating gates traversed in the Source-to-Drain leakage path below the target transistor. In this embodiment, `sdleakagedummygate_down = 0`.

[0088] `sdleakagecontrolgate_down` represents the number of controlled gates in the Source-to-Drain path below the target transistor. In this embodiment, `sdleakagecontrolgate_down = 0`.

[0089] A storage device storing a plurality of instructions adapted for loading by a processor and executing the method described above for identifying leakage paths between the source and drain of a transistor.

[0090] Example 2

[0091] Combination Figure 3 and Figure 4 The illustrated method for identifying the leakage path between the source and drain of a transistor includes the following steps: Step 1: Obtain the layout; based on the circuit connections in the layout, obtain the circuit path from the source to the drain of the target transistor, denoted as loop_n (n=1, 2, 3...). Loop_n is circular, as shown below. Figure 4 As shown, the closed region in the middle of the loop_n is denoted as loop_holes;

[0092] All gates that come into contact with the loop holes are denoted as loopgate;

[0093] The gate of the target transistor in the loopgate is denoted as agate_except;

[0094] The controlled gate in the loopgate, excluding the agate_except gate, is denoted as agate_control. The controlled gate refers to the gate that performs input / output control. Generally, the controlled gate refers to the gate that performs input / output control by connecting lines, such as connecting lines such as M0P, V0, and M1 to the pad.

[0095] The gates in the loopgate other than agate_except and agate_control are referred to as floating gates;

[0096] Step 2: Cut loop_n at agate_except and agate_control to obtain loop_remain. Define loop_remain intersecting the left side of agate_except as loop_left, and loop_remain intersecting the right side of agate_except as loop_right. Define the M0A cluster intersecting loop_left as M0A_loop_left, and the agate_control connected to it as agate_sd_left. Define the M0A cluster intersecting loop_right as M0A_loop_right, and the agate_control connected to it as agate_sd_right. Pass the number of agate_sd_left / agate_sd_right contacts of loop_holes, n4 / n5, as parameters into the gate of the target transistor. (n4>0) proves the existence of a leakage path from the controlled gate to the source / drain on the left side of the target transistor gate. (n5>0) proves the existence of a leakage path from the controlled gate to the source / drain on the right side of the target transistor gate. Meanwhile, the number of intersecting loop_left / loop_right points (agate NOT (OR agate_sd_left agate_sd_right agate_except)) n6 / n7 represents the number of floating gates traversed by the controlled gate of the leakage path from the left / right source / drain leakage path to the target transistor. Since the controlled gate of the leakage path is connected to the body of the target transistor during testing, this is equivalent to the existence of a source / drain to body leakage path, which can easily lead to abnormal test data.

[0097] Preferably, in step 1, after obtaining the circuit path from the source to the drain of the target transistor, a screening step 1.1 is also performed:

[0098] When there are multiple source-to-drain circuit paths above the target transistor, the shortest circuit path is selected and denoted as loop_up_n;

[0099] When there are multiple source-to-drain circuit paths below the target transistor, the shortest circuit path is selected and denoted as loop_down_n.

[0100] After performing step 1.1, loop_n (n=1, 2, 3...) in step 1 refers to loop_up_n and / or loop_down_n.

[0101] Risk parameters llktoloopgate_up, llktoloopgate_down, rlktoloopgate_up, and rlktoloopgate_down are defined to characterize the risk level of the leakage path of the target transistor. Specifically, llktoloopgate_up represents the number of floating gates traversed in the Source / Drain to controlgate leakage path to the left of the target transistor gate in the Source to Drain leakage path above the target transistor, plus 1; 0 indicates that none exist. In this embodiment, llktoloopgate_up = 1.

[0102] `llktoloopgate_down` represents the number of floating gates traversed in the Source / Drain to controlgate leakage path to the left of the target transistor's gate in the Source to Drain leakage path below the target transistor, plus 1. 0 indicates no floating gates. In this embodiment, `llktoloopgate_down = 0`.

[0103] `rlktoloopgate_up` represents the number of floating gates traversed in the Source / Drain to controlgate (controlled gate) leakage path to the right of the target transistor's gate in the Source to Drain leakage path above the target transistor, plus 1. 0 indicates no floating gates. In this embodiment, `rlktoloopgate_up = 0`.

[0104] `rlktoloopgate_down` represents the number of floating gates traversed in the Source / Drain to controlgate (controlled gate) leakage path to the right of the target transistor's gate in the Source to Drain leakage path below the target transistor, plus 1. 0 indicates no floating gates. In this embodiment, `rlktoloopgate_down = 0`.

[0105] A storage device storing a plurality of instructions adapted for loading by a processor and executing the method described above for identifying a leakage path from the source drain to the body of a transistor.

[0106] Example 3

[0107] A storage device, in conjunction with Embodiment 1 and Embodiment 2, stores a plurality of instructions adapted for loading and execution by a processor of the above-described methods for identifying leakage paths between the source and drain of a transistor and for identifying leakage paths from the source and drain of a transistor to the body.

[0108] Example 4

[0109] This embodiment provides a method for identifying transistor leakage paths, including identifying: leakage paths between the transistor source and drain, leakage paths from the transistor source and drain to the body, and leakage paths from the transistor gate to the body; wherein, the leakage path between the transistor source and drain is implemented using the method for identifying leakage paths between the transistor source and drain in Embodiment 1 above, and / or, the method for identifying leakage paths from the transistor source and drain to the body includes the method for identifying leakage paths from the transistor source and drain to the body in Embodiment 2 above.

[0110] Example 5

[0111] Another method for identifying the source-drain to body leakage path of a transistor is provided to more comprehensively identify the source-drain to body leakage path of the transistor. See [link to relevant documentation] for details. Figure 5 This includes the following steps:

[0112] Step 1: Obtain the layout, which includes an active area layer and an active area connection layer. The graphic of the active area layer is the active area, denoted as AA. The graphic of the active area connection layer is the active area connection line, denoted as M0A, used to connect the active areas AA.

[0113] Step 2: Cut along the gate of the target transistor, severing the active region AA containing the target transistor to obtain several AA sub-regions, denoted as dif_not_seed. That is, cut the active region AA from the gate of the target transistor to obtain dif_not_seed. Based on the connection relationship between layers, identify the dif_not_seed containing the target transistor that is connected to the body of the target transistor through the MOA (active region connection line), and define it as err_path1.

[0114] Step 3: Based on the circuit connections in the layout, identify the Source / Drain to Body circuit path of the target transistor, and define the Source / Drain to Body circuit path as err_path1_hole. Based on the circuit connections in the layout, identify the floating gate that contacts err_path1_hole, and denote the floating gate that err_path1_hole passes through as err_path1_dumgate. The floating gate refers to a gate without external connection lines for input / output control.

[0115] The parameters err_path1, err_path1_hole, and err_path1_dumgate are bundled and passed as parameters to the gate of the target device (i.e., the target transistor) connected to err_path1. Three risk parameters are defined to quantify the risk of a source / drain to body leakage path in the target transistor. Let c1 be the number of err_path1 connections to the target transistor gate, c2 be the number of err_path1_hole connections to err_path1, and c3 be the number of err_path1_dumgate connections to err_path1.

[0116] When c1 = 0, it indicates that the target transistor has no source / drain to body leakage path.

[0117] When c1 > 0 and c1 = c2, it indicates that the target transistor has a source / drain to body leakage path, and the leakage path passes through the c3 floating gate. At this time, the smaller the value of c3, the higher the risk of the source / drain to body leakage path of the target transistor.

[0118] When c1 > 0 and c1 > c2, it indicates that the target transistor has a leakage path from source to body. The leakage path is that the source / drain is directly connected to the body through the M0A (active region connection line) without passing through the floating gate. At this time, the risk of leakage path is the highest.

[0119] Based on different combinations of parameters, it is possible to determine whether a source / drain to body leakage path exists and its risk. Quantitatively characterizing the risk level of the leakage path can help in the selection of test transistors in the chip, thereby enabling the analysis of outliers in subsequent transistor test results.

[0120] Example 6

[0121] like Figure 6 and Figure 7 As shown, the parameters set characterize the source / drain to body of the target transistor (e.g., Figure 6 and Figure 7 The risk level of leakage path (marked in the body):

[0122] The location of the circuit path from the source / drain to the body of the target transistor can be characterized using parameter quantification. This can be divided into circuit paths on the left side of the target transistor's gate and circuit paths on the right side of the gate. `lblkpath` represents the number of circuit paths from the source / drain to the body on the left side of the target transistor's gate; 0 indicates that none exist. In this embodiment, `lblkpath=1`.

[0123] `lblk_mindumgate` represents the minimum number of floating gates traversed in the Source / Drain to Body circuit path on the left side of the target transistor's gate. In this embodiment, there is only one Source / Drain to Body circuit path on the left side of the target transistor's gate, and this circuit path traverses 3 floating gates, so `lblk_mindumgate = 3`.

[0124] `lblk_mindumgatepath` represents the number of circuit paths that pass through the minimum number of floating gates in the Source / Drain to Body circuit path to the left of the target transistor's gate. In this embodiment, `lblk_mindumgatepath=1`.

[0125] rblkpath represents the number of circuit paths from the source / drain to the body on the right side of the target transistor's gate; 0 indicates that none exist. In this embodiment, rblkpath = 0.

[0126] `rblk_mindumgate` represents the minimum number of floating gates that pass through in the Source / Drain to Body circuit path to the right of the target transistor's gate. In this embodiment, there is no Source / Drain to Body circuit path to the right of the target transistor's gate, so `rblk_mindumgate = 0`.

[0127] `rblk_mindumgatepath` represents the number of circuit paths that pass through the minimum number of floating gates in the Source / Drain to Body circuit path to the right of the target transistor's gate. In this embodiment, `rblk_mindumgatepath` = 0.

[0128] In other words, by setting the above-mentioned quantitative parameters, the leakage path risk of the target transistor from the source / drain to the body in Example 6 is specifically characterized.

[0129] Example 7

[0130] like Figure 8 As shown, the parameters are set to characterize the source / drain to body of the target transistor (e.g., ...). Figure 8 Risks arising from leakage paths (marked in the body):

[0131] The location of the circuit path from the source / drain to the body of the target transistor can be characterized using parameter quantification. This can be divided into circuit paths on the left side of the target transistor's gate and circuit paths on the right side of the gate. `lblkpath` represents the number of circuit paths from the source / drain to the body on the left side of the target transistor's gate; 0 indicates that none exist. In this embodiment, `lblkpath=0`.

[0132] `lblk_mindumgate` represents the minimum number of floating gates that pass through the Source / Drain to Body circuit path on the left side of the target transistor's gate. In this embodiment, there is no Source / Drain to Body circuit path on the left side of the target transistor's gate, so `lblk_mindumgate = 0`.

[0133] `lblk_mindumgatepath` represents the number of circuit paths that pass through the minimum number of floating gates in the Source / Drain to Body circuit path to the left of the target transistor's gate. In this embodiment, `lblk_mindumgatepath` = 0.

[0134] rblkpath represents the number of circuit paths from source / drain to body on the right side of the target transistor gate; 0 indicates that none exist. In this embodiment, rblkpath=1.

[0135] `rblk_mindumgate` represents the minimum number of floating gates traversed in the Source / Drain to Body circuit path to the right of the target transistor's gate. In this embodiment, there is only one Source / Drain to Body circuit path to the right of the target transistor's gate, so `rblk_mindumgate=1`.

[0136] `rblk_mindumgatepath` represents the number of circuit paths that pass through the minimum number of floating gates in the Source / Drain to Body circuit path to the right of the target transistor's gate. In this embodiment, `rblk_mindumgatepath` = 1.

[0137] In other words, by setting the above-mentioned quantitative parameters, the leakage path risk of the target transistor from the source / drain to the body in Embodiment 7 is specifically characterized.

[0138] Examples 6 and 7 involve identifying leakage paths from the source / drain to different body terminals of a target transistor within the same layout. Furthermore, the leakage risk from the source / drain to the body terminal of the target transistor in Example 6 is lower than that in Example 7.

[0139] Example 8

[0140] This embodiment provides a storage device that stores a plurality of instructions, which are adapted to be loaded by a processor and executed by the method for identifying the leakage path from the source drain to the body of a transistor as provided in Embodiments 5-7 above.

[0141] Example 9

[0142] Figure 9 This is a schematic diagram of the method flow in one embodiment of the present invention. Please refer to it. Figure 9 This embodiment discloses a method for identifying the leakage path from the gate to the body of a transistor, including the following steps:

[0143] Step 1: Obtain the layout, which includes at least a polysilicon interconnect layer, a via layer, an interconnect layer, and a polysilicon layer; wherein, the pattern of the polysilicon interconnect layer is denoted as M0P, and it is used to connect the polysilicon layers; the pattern of the interconnect layer is denoted as M1; the pattern of the via layer is denoted as V0, and it is used to connect M0 and M1; M0 includes M0P and M0A, and the pattern of the active region interconnect layer is denoted as M0A, and it is used to connect the active region;

[0144] Based on the connection relationship between layers, M0P, V0 and M1 that are connected to the gate of the target transistor are identified, and the M0P, V0 and M1 are merged to obtain a graphic and denoted as seed_conn;

[0145] Step 2: Based on the circuit connection relationship in the layout, obtain the circuit path connected to the body of the target transistor, identify the circuit path that is connected to seed_conn and record it as the leakage path from the gate to the body of the target transistor, and determine that there is a risk of leakage.

[0146] Figure 10 This is a schematic diagram of the seed_conn of the target transistor in one embodiment of the present invention. Figure 11 yes Figure 10 A magnified view of point A in the middle, shown below in conjunction with... Figure 10 and Figure 11 The method for identifying the leakage path from the gate to the body of a transistor provided by the present invention will be described in detail below:

[0147] In this embodiment, M0P, M1, and V0, which are connected to the gate of the target transistor in the layout information, are identified. M0P, V0, and M1 are merged to obtain a pattern, which is denoted as seed_conn. Based on the circuit connection relationships in the layout, the circuit path connected to the body of the target transistor is obtained. The circuit path connected to seed_conn is identified and denoted as the leakage path from the gate to the body of the target transistor. A leakage risk is determined, and the leakage path is defined as err_dio1_hole. In this embodiment, the polysilicon interconnect layer pattern (M0P) is a metal interconnect line used to connect the polysilicon layer; the interconnect layer pattern (M1) is a connecting line; the via layer pattern (V0) is a via used to connect M0 and M1. M0 includes M0P and M0A, where M0A is the active region interconnect layer pattern used to connect the active region.

[0148] Identify the floating gates and their number on the `err_dio1_hole`, and designate the floating gates connected to the `err_dio1_hole` as `err_dio1_dumgate`. Use the number of floating gates that each `err_dio1_hole` passes through as an indicator to characterize the leakage risk of that `err_dio1_hole`. For example... Figure 11 As shown, the number of err_dio1_holes in contact with seed_conn is 3. Two of these err_dio1_holes have 1 err_dio1_dumgate in contact, meaning both leakage paths pass through one floating gate. The other err_dio1_hole has 3 err_dio1_dumgates in contact, meaning this leakage path passes through 3 floating gates. The leakage path that passes through the fewest floating gates is the one with the highest leakage risk. In this embodiment, the two leakage paths that pass through 1 floating gate are determined to have the highest leakage risk.

[0149] Furthermore, set the vector parameters { <m1> ， <m2>< M1-1>,..., characterizing an overall leakage risk of the target transistor gate-to-body, i is a positive integer not less than 1, and the For the i-th leakage path of the target transistor gate to body, the value of Mi is the number of floating gates through which the i-th leakage path passes. In this embodiment, the vector parameter is {<1>, <1>, <3>}, which can simultaneously reflect the number of err_dio1_hole and err_dio1_dumgate in the target transistor, thereby quantitatively characterizing the overall leakage risk of the target transistor.

[0150] Define parameters m and n, where m represents the number of floating gates through which the leakage path with the highest leakage risk among the i target transistor gate-to-body leakage paths passes, and n represents the number of leakage paths with the highest leakage risk among the i target transistor gate-to-body leakage paths. Save the vector format parameter in the form of {<1>, <1>, <3>} in the seed_conn. Pass this parameter into the gate of the target device connected with the seed_conn, and traverse each array element in the vector format parameter, and record the minimum value m=1 in the array element and the number of times n=2 that the minimum value appears in the array element. The values of parameters m and / or n can be used as a basis for quantitatively characterizing the overall leakage risk of the target transistor gate-to-body leakage path.

[0151] A storage device having stored therein a plurality of instructions, the instructions being loaded and executed by a processor, the instructions comprising the method of identifying the transistor gate-to-body leakage path in the above technical solution. The above embodiments are only used to help understand the method and core idea of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present application. < / m1> < / m1> < / m1> < / m1>

Claims

1. A method for identifying leakage paths between the source and drain of a transistor, characterized in that, The method comprises the following steps: Step 1: obtaining a layout, and obtaining a circuit path from a source electrode to a drain electrode of a target transistor according to a circuit connection relationship in the layout, and recording the circuit path as loop_n, n = 1, 2, 3, …; Step 2: in the loop_n, identifying a loop_i in which a floating gate exists in the circuit path, recording the loop_i as loop_i, i = 1, 2, 3, …, and determining that the loop_i is a leakage path between source and drain electrodes of the target transistor, that is, there is a risk of leakage; and the number of floating gates in the loop_i is negatively correlated with the risk of leakage; According to the loop_i, the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes of the target transistor is determined, and the risk of leakage of the leakage path between the source and drain electrodes ​ ​ ​ ​ ​ ​ 2. The method of identifying a leakage path between source and drain of a transistor according to claim 1, wherein, ​ ​ ​ ​ 3. The method of identifying a leakage path between source and drain of a transistor according to claim 1, wherein, ​ The sdleakagepath is the sum of n1 values of the leakage path between the source and drain of the target transistor, used to represent whether the leakage path between the source and drain of the target transistor exists, 0 represents that it does not exist, and other numerical values represent that it exists; The sdleakagedummygate_up is the value of N of the leakage path between the source and drain above the target transistor, used to represent the number of floating gates through which the leakage path between the source and drain above the target transistor passes; The sdleakagecontrolgate_up is the value of n3 of the leakage path between the source and drain above the target transistor, used to represent the number of controlled gates through which the leakage path between the source and drain above the target transistor passes; The sdleakagedummygate_down is the value of N of the leakage path between the source and drain below the target transistor, used to represent the number of floating gates through which the leakage path between the source and drain below the target transistor passes; The sdleakagecontrolgate_down is the value of n3 of the leakage path between the source and drain below the target transistor, used to represent the number of controlled gates through which the leakage path between the source and drain below the target transistor passes.

4. A method of identifying a leakage path from a source / drain to a body of a transistor, comprising: The method comprises the following steps: Step 1: Obtain a layout, and according to the circuit connection relationship in the layout, obtain a circuit path from the source to the drain of a target transistor, denoted as loop_n, n=1, 2, 3,..., the loop_n is annular, and the middle closed area of the annular loop_n is denoted as loop_holes; The gate in contact with the loop_holes is denoted as loopgate; The gate of the target transistor in the loopgate is denoted as agate_except; The controlled gate in the loopgate except the agate_except is denoted as agate_control; the controlled gate refers to the gate for input / output control; The gate in the loopgate except the agate_except and the agate_control is denoted as a floating gate; Step 2: Cutting is performed with the agate_except and the agate_control, the loop_n is divided into several segments loop_remain, the loop_remain in contact with the left side of the agate_except is denoted as loop_left, and the loop_remain in contact with the right side of the agate_except is denoted as loop_right; The connection line for connecting the active region is denoted as M0A; M0A in contact with the loop_left is recorded as M0A_loop_left, agate_control in connection with the M0A_loop_left is recorded as agate_sd_left, and a risk parameter n4 is defined to represent the number of agate_sd_left; M0A in contact with the loop_right is recorded as M0A_loop_right, agate_control in connection with the M0A_loop_right is recorded as agate_sd_right, and a risk parameter n5 is defined to represent the number of agate_sd_right; If n4>0, it is determined that the target transistor has a leakage path from its left side to the body; If n5>0, it is determined that the target transistor has a leakage path from its right side to the body; Risk parameters n6 and n7 are also defined to represent the number of floating gates through which the leakage path from the source / drain of the target transistor to the body passes. The number of agate_control in contact with the loop_left, excluding the agate_sd_left, agate_sd_right, and agate_except, i.e., the number of floating gates through which the leakage path from the left source / drain of the target transistor to the body passes, is recorded as the value of n6, and the smaller the value of n6, the higher the risk of leakage; The number of agate_control in contact with the loop_right, excluding the agate_sd_left, agate_sd_right, and agate_except, i.e., the number of floating gates through which the leakage path from the right source / drain of the target transistor to the body passes, is recorded as the value of n7, and the smaller the value of n7, the higher the risk of leakage.

5. The method of identifying a leakage path from a source / drain to a body of a transistor according to claim 4, wherein, In step 1, after obtaining the circuit path from the source to the drain of the target transistor, a screening step 1.1 is performed: When there are multiple source-to-drain circuit paths above the target transistor, the shortest circuit path is selected and recorded as loop_up_n; When there are multiple source-to-drain circuit paths below the target transistor, the shortest circuit path is selected and recorded as loop_down_n; After performing step 1.1, loop_n in step 1 refers to loop_up_n and / or loop_down_n.

6. The method of identifying a leakage path from a source / drain to a body of a transistor of claim 5, wherein, Risk parameters llktoloopgate_up, llktoloopgate_down, rlktoloopgate_up, and rlktoloopgate_down are defined to represent the number of floating gates in the leakage path from the source / drain to the body located above and below the left and right of the target transistor.

7. A method of identifying a leakage path of a transistor, the method comprising: The method comprises identifying: a leakage path between the source and drain of a transistor, a leakage path from the source and drain of a transistor to a body, and a leakage path from the gate of a transistor to a body; wherein the leakage path between the source and drain of a transistor is identified using the method of any one of claims 1 to 3, and / or the method of identifying the leakage path from the source and drain of a transistor to a body comprises any one of claims 4 to 6.

8. A storage device having stored therein a number of instructions adapted to be loaded by a processor and to perform the method of identifying a leakage path between the source and drain of a transistor of any one of claims 1 to 3 and / or the method of identifying a leakage path from the source and drain of a transistor to a body of any one of claims 4 to 6.

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