A high-precision intelligent adjustment drive control system

Abstract

The present invention discloses a high-precision intelligent adjustment drive control system, which includes a per-cycle peak voltage detection circuit, an actual peak voltage detection circuit, a voltage rising slope reference circuit, and an adaptive compensation drive circuit. The present invention can not only use the same main control circuit to drive different power MOSFETs, but also meet the requirement that the drive capabilities of the power MOSFETs remain balanced within the full load range of the AC voltage. At the same time, it can also prevent adverse consequences such as the damage of the power MOSFET caused by the saturation of the transformer core when the external temperature is too high.

Description

Technical Field

[0001] The present invention relates to the field of primary-side feedback AC / DC switching power supplies, and particularly to a high-precision intelligent regulation drive control system. Background Art

[0002] With the increasing demand for switching power supplies, the requirements of the power supply main control chip for reducing costs, increasing functions, and optimizing performance are becoming more stringent.

[0003] The switching power supply mainly uses the power MOSFET to quickly switch between the on mode and the off mode. There is a high energy dissipation during the switching. Since the switching time is very short, the switching power supply has high efficiency, saves energy, and generates less heat. However, because the power MOSFET is in a fast switching state, the DV / DT and DI / DT change rapidly, and the instantaneous violent change of voltage and current will inevitably generate electromagnetic interference. Moreover, the EMI signal of electromagnetic interference occupies a wide frequency range and has a certain amplitude. These EMI interferences pollute the electromagnetic environment through conduction and radiation methods, causing interference to communication devices and electronic instruments. Therefore, this kind of electromagnetic interference needs to be suppressed. For the control chip, it is necessary to reduce the instantaneous violent change of the voltage and current of the power MOSFET.

[0004] To improve the working efficiency of the switching power supply, it is necessary to reduce the switching loss of the power MOSFET, and the switching speed of the power MOSFET needs to be increased. On the other hand, considering the EMI electromagnetic interference, the switching speed of the power MOSFET cannot be too fast. To balance efficiency and EMI, the driving ability and the MOSFET matching item need to be in a balanced state. Therefore, there are higher requirements for the driving ability of the power MOSFET.

[0005] On the other hand, with the enrichment of electronic products, there are more and more consumer electronic products applied in various power segments and working at different wattages. Correspondingly, there are more and more power MOSFETs with different rated working currents to meet the requirements of various powers. Obviously, the current capabilities, sizes, areas, and thus the parasitic GS capacitances of power MOSFETs with different rated working currents are different. For AC / DC switching power supplies, usually a main control circuit is used to match a power MOSFET to meet the system application. Since the rated current of the power MOSFET is different, it is necessary for the main control chip to have an intelligent adjustable driving ability to meet the driving requirements.

[0006] The typical application structure of the primary-side feedback detection flyback power converter system is as Figure 1As shown in the figure, it is assumed that the system operates in discontinuous conduction mode (DCM). In an ideal state, after the primary inductance current of the transformer flows through the conducting power transistor, the voltage is transmitted to the CS port of the control chip via the sampling resistor. When the CS detects the threshold voltage Vpeak, it immediately controls the power transistor to turn off. The peak current of the primary inductance of the transformer is determined by the following formula:

[0007]

[0008] In actual operation, when the CS detects the threshold voltage Vpeak, there is a delay time for the internal control signal to turn off. Therefore, the actual peak current of the primary inductance of the transformer and the output power are determined by the following formulas respectively:

[0009]

[0010] Vpeak: The threshold voltage set inside the chip for controlling the peak current of the primary inductance of the transformer;

[0011] Rcs: The value of the sampling resistor from the CS port of the chip to ground;

[0012] Vin: The voltage value after the AC input voltage passes through the bridge rectifier circuit;

[0013] Lp: The primary inductance of the transformer;

[0014] Ton: The time corresponding to the voltage at the CS terminal reaching Vpeak from the start of conduction of the power transistor;

[0015] Td: The delay time from the CS voltage reaching Vpeak to turning off the power transistor after the control signal is issued;

[0016] Ipeak: The actual peak current of the primary inductance of the transformer;

[0017] It can be seen from formulas (1) and (2) that the rising slope of the peak current of the primary inductance of the transformer changes with the changes of Lp, Vin, and Td. When the primary inductance LP of the transformer remains unchanged on a fixed application board and within the full AC voltage range (90 - 264 range), the rising slope of the primary side current is mainly affected by the voltage value VIN after the AC input voltage passes through the bridge rectifier circuit. However, in the control chip, the ability to drive the GATE signal of the power MOSFET is fixed, specifically manifested as the fixed rising edge delay and falling edge delay of the GATE. At low AC voltages, the switching loss of the MOSFET dominates. To reduce losses and improve efficiency, it is necessary to appropriately increase the driving ability of the GATE. In the case of high AC voltages, the current on the MOSFET rises significantly within the system delay TD time, and the operating frequency is high, resulting in increased EMI interference. It is necessary to appropriately reduce the driving ability of the GATE.

[0018] When the switching power supply operates at the rated power or even exceeds the rated power for a long time, the power loss of the power supply system gradually increases, and the lost power is released as heat. Currently, high power density switching power supplies are popular, which also means that the external dimensions of chargers or adapters are getting smaller and smaller. The limited heat dissipation space and heat dissipation capacity will cause the temperature of the switching power supply to rise, resulting in phenomena such as the charger or adapter getting hot. When the temperature continues to rise, on the one hand, the on-resistance of the power MOSFET increases, and the on-loss and off-loss on the power MOSFET increase, and the power efficiency of the switching power supply decreases. The temperature continues to rise, forming a positive feedback mechanism for temperature rise. When the temperature of the switching power supply system is high, a series of dangerous factors will be brought. For example, when the temperature rise is too high, the transformer operates abnormally and saturates, and the primary inductance current loses its inhibitory effect. The current flowing through the power MOSFET exceeds the rated value, resulting in serious consequences such as the damage of the power MOSFET. Summary of the Invention

[0019] Aiming at the above deficiencies in the prior art, a high-precision intelligent adjustment drive control system provided by the present invention solves the problem that the switching power supply system is prone to damage when the temperature is high during operation.

[0020] In order to achieve the above invention purpose, the technical solution adopted by the present invention is: a high-precision intelligent adjustment drive control system, including:

[0021] A per-cycle peak voltage detection circuit for detecting the voltage CSA generated by the peak current of the primary winding of the transformer on the resistor RCS when the PWM is turned off, and calculating the voltage rise slope KCSA of the primary winding of the transformer;

[0022] An actual peak voltage detection circuit for detecting the voltage CSB generated by the actual peak current of the primary winding of the transformer on the resistor RCS, calculating the voltage rise slope KCSB within the system delay from the moment when the PWM is turned off to the moment when the actual peak voltage is turned off, and calculating the system delay time TD signal from the moment when the PWM is turned off to the moment when the actual peak voltage is turned off;

[0023] A voltage rise slope reference circuit for generating an internally set threshold slope KBG signal according to the detected system delay time TD signal;

[0024] An adaptive compensation drive circuit, according to the detected two voltage rise slopes KCSA and KCSB, comparing KCSA and KCSB with the threshold slope KBG through calculation, and outputting a CTRR signal for intelligently adjusting the drive turn-on ability and a CTRF signal for the drive turn-off ability. The CTRR signal and the CTRF signal are respectively used to control the pre-stage upper drive NMOS transistor M1 and the pre-stage lower drive NMOS transistor M2, and a GATE signal for intelligently adjusting the drive ability can be obtained. The GATE signal controls the power MOSFET to turn on or off.

[0025] Further: The input end of the per-cycle peak voltage detection circuit is connected to the internal control signal PWM, the voltage CS generated by the current of the primary winding of the transformer on the resistor RCS, and the internal reference voltage VA, and outputs the voltage CSA generated by the peak current of the primary winding at the PWM turn-off moment on the resistor RCS and the voltage rise slope KCSA of the primary winding voltage.

[0026] Further: During the PWM conduction period, the current of the primary winding of the transformer linearly rises at a fixed slope. This current flows through the RCS resistor to generate the CS voltage. When the CS voltage is greater than the internal reference voltage VA, the entire control system starts to work; at the end of PWM, sample and hold the CS voltage as CSA, calculate the voltage difference ΔCSA between CSA and VA, and then calculate the time difference ΔTA between the PWM turn-off moment and the VA moment. The primary winding voltage rise slope KCSA signal can be obtained through the voltage difference ΔCSA and the time difference ΔTA.

[0027] Further: The input end of the actual peak voltage detection circuit is connected to the internal control signal PWM and the voltage CSA generated by the per-cycle current of the primary winding on the resistor RCS, and outputs the voltage CSB generated by the actual peak current of the primary winding of the transformer on the resistor RCS, the voltage rise slope KCSB within the system delay from the PWM turn-off moment to the actual peak voltage turn-off moment, and the system delay time TD signal.

[0028] Further: At the PWM turn-off moment, due to the internal logic delay of the system, the power MOSFET will not turn off immediately, and the current of the primary winding of the transformer will not turn off immediately. The CS voltage generated by this current flowing through the RCS resistor continues to rise; the actual peak voltage detection circuit detects the true CS peak voltage through the internal circuit and saves it as the CSB signal, detects the time difference TD signal from the PWM turn-off moment to the moment when the true CS peak voltage is reached, and calculates the voltage difference ΔCSB between CSB and CSA; calculates the primary winding voltage rise slope KCSB signal of the voltage difference ΔCSB within the system delay TD time.

[0029] Further: The input end of the voltage rise slope reference circuit is connected to the system delay time TD signal, and outputs the internally set threshold slope KBG; according to the system delay time TD signal obtained in the actual peak voltage detection circuit, an internally generated voltage rise slope reference KBG signal is generated within the circuit.

[0030] Further: The adaptive compensation drive circuit includes a slope compensation pre-stage drive circuit, a pre-stage upper drive NMOS transistor M1, and a pre-stage lower drive NMOS transistor M2.

[0031] Further: The input end of the slope compensation pre-stage drive circuit is connected to the internal control signals PWM, KCSA signal, KCSB signal, and KBG signal, and outputs CTRR signal and CTRF signal.

[0032] Further: The CTRR signal is connected to the gate terminal of the pre-stage upper drive NMOS transistor M1, the CTRF signal is connected to the gate terminal of the pre-stage lower drive NMOS transistor M2. The drain terminal of the pre-stage upper drive NMOS transistor M1 is connected to the internal high-voltage power supply VDD of the chip. The source terminal of the pre-stage upper drive NMOS transistor M1 is connected to the drain terminal of the pre-stage lower drive NMOS transistor M2, and outputs the GATE signal. The source terminal of the lower drive NMOS transistor M2 is grounded, and the GATE signal is connected to the gate terminal of the power MOSFET.

[0033] The beneficial effects of the present invention are as follows: The present invention can use the same control chip to drive different power MOSFETs, and can satisfy the balance of the driving ability of the power MOSFET within the full load range of the AC voltage. At the same time, it can also prevent the power MOSFET from being damaged due to the saturation of the transformer core when the external temperature is too high and other adverse consequences. Brief Description of the Drawings

[0034] Figure 1 It is a typical application structure block diagram of the primary side feedback detection flyback power converter system;

[0035] Figure 2 It is a principle structure diagram of a high-precision intelligent adjustment drive control system of the present invention;

[0036] Figure 3 A signal schematic diagram of a high-precision intelligent adjustment drive control technology of the present invention. Detailed Embodiments

[0037] The following describes the detailed embodiments of the present invention to facilitate those skilled in the art of the present technology to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the detailed embodiments. For those of ordinary skill in the art of the present technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions created using the concept of the present invention are within the scope of protection.

[0038] As Figure 2 shown, a high-precision intelligent adjustment drive control system includes:

[0039] A cycle-by-cycle peak voltage detection circuit for detecting the voltage CSA generated by the peak current of the primary winding of the transformer on the resistor RCS when PWM is turned off, and calculating the voltage rise slope KCSA of the primary winding of the transformer;

[0040] The input terminal of the per-cycle peak voltage detection circuit is connected to the internal control signal PWM, the voltage CSB generated by the actual peak current of the primary winding of the transformer across the resistor RCS, and the internal reference voltage VA. The output is the voltage CSA generated by the per-cycle voltage peak current of the primary winding across the resistor RCS and the voltage rise slope KCSA of the primary winding voltage. During the conduction of PWM, the primary winding current linearly rises at a fixed slope. This current flows through the RCS resistor to generate the CS voltage. When the CS voltage is greater than the internal reference voltage VA, the entire control system starts to work. At the end of PWM, the CS voltage is sampled and held as CSA, the voltage difference ΔCSA between CSA and VA is calculated, and then the time difference ΔTA between the PWM and VA moments is calculated. The primary winding voltage rise slope KCSA signal can be obtained through the voltage difference ΔCSA and the time difference ΔTA.

[0041] The actual peak voltage detection circuit is used to detect the actual peak voltage CSB on the primary winding of the transformer, calculate the voltage rise slope KCSB within the system delay from the PWM off moment to the moment when the CS voltage reaches the actual peak voltage, and calculate the system delay time TD signal of the CS voltage from the PWM off moment to the actual peak voltage moment.

[0042] The input terminal of the actual peak voltage detection circuit is connected to the internal control signal PWM and the voltage CSA generated by the per-cycle peak current of the primary winding across the resistor RCS. The output is the voltage CSB generated by the actual peak current of the primary winding of the detected transformer across the resistor RCS, the voltage rise slope KCSB within the system delay from the PWM off moment to the actual peak voltage off moment, and the system delay time TD signal. At the PWM off moment, due to the internal logic delay of the system, the power MOSFET does not immediately turn off, the primary winding current does not immediately turn off, and the CS voltage continues to rise. The actual peak voltage detection circuit detects the true CS peak voltage through the internal circuit and takes it as the CSB signal, detects the time difference TD signal from the PWM off moment to the moment when the CS voltage reaches the true peak moment, and calculates the voltage difference ΔCSB between CSB and CSA. The primary winding voltage rise slope KCSB signal within the system delay TD time of the calculated voltage difference ΔCSB is obtained.

[0043] The voltage rise slope reference circuit generates an internally set threshold slope KBG signal based on the detected system delay time TD signal.

[0044] The input terminal of the voltage rise slope reference circuit is connected to the system delay time TD signal, and the output is the internally set threshold slope KBG. An internally set voltage rise slope reference KBG signal is generated inside the circuit according to the system delay time TD signal obtained in the actual peak voltage detection circuit.

[0045] The adaptive compensation driving circuit, according to the detected voltage rising slopes KCSA and KCSB of the two primary windings of the transformer, through arithmetic comparison with the threshold slope KBG, outputs the CTRR and CTRF signals whose rising edge time can be intelligently adjusted. The CTRR signal and the CTRF signal respectively control the upper driving NMOS transistor M1 and the lower driving NMOS transistor M2 of the previous stage, and obtain the GATE signal whose driving ability can be intelligently adjusted. The GATE signal controls the power MOSFET to turn on or off.

[0046] The adaptive compensation driving circuit includes a slope compensation pre-driving circuit, an upper driving NMOS transistor M1 of the previous stage, and a lower driving NMOS transistor M2 of the previous stage. The input end of the slope compensation pre-driving circuit is connected to the internal control signal PWM, the KCSA signal, the KCSB signal, and the KBG signal, and outputs the CTRR signal and the CTRF signal. The CTRR signal is connected to the gate terminal of the upper driving NMOS transistor M1 of the previous stage, the CTRF signal is connected to the gate terminal of the lower driving NMOS transistor M2 of the previous stage. The drain terminal of the upper driving NMOS transistor M1 of the previous stage is connected to the internal high-voltage power supply VDD of the chip, the source terminal of the upper driving NMOS transistor M1 of the previous stage is connected to the drain terminal of the lower driving NMOS transistor M2 of the previous stage, and outputs the GATE signal. The source terminal of the lower driving NMOS transistor M2 is grounded, and the GATE signal is connected to the gate terminal of the power MOSFET.

[0047] An embodiment of the present invention is: Refer to Figure 3As shown, when the internal control signal PWM of the chip is high, it controls GATE to be high, the power is turned on, and the current in the primary winding of the transformer rises linearly. Then, the CS voltage across the voltage detection resistor of the primary winding of the transformer rises linearly. When PWM is turned off, the CS voltage is detected and saved as CSA. When the CS voltage exceeds the internally set reference voltage VA, the entire control system starts to work. On the one hand, the CS voltage is sampled and held as CSA at the end of PWM. On the other hand, the voltage difference ΔCSA between CSA and VA is calculated, the time difference ΔTA between the PWM and VA moments is calculated, and then the rising slope KCSA of the voltage of the primary winding of the transformer is calculated. After PWM is turned off, the current in the primary winding of the transformer will not turn off immediately, and the CS voltage will necessarily continue to rise and will necessarily be delayed for a period of time before turning off. The actual peak voltage detection circuit of the primary winding of the transformer detects the actual CS peak voltage through the internal circuit and holds it as the CSB signal, detects the time difference TD signal from the end of PWM to the actual peak moment of the CS voltage, and calculates the voltage difference ΔCSB between CSB and CSA. The rising slope KSCB signal of the voltage of the primary winding within the system delay time TD signal is calculated. At the same time, according to the system delay time TD signal, a voltage rising slope reference KBG signal is generated inside the circuit. In the first case, under normal circumstances, when the difference between the slopes of KCSB and KCSA is small, the entire CS voltage basically rises linearly. When the inductance of the primary winding of the transformer is fixed, the slope of KCSA is only related to the rated operating current of the power MOSFET or the AC voltage, i.e., the VIN voltage.

[0048] In the case of power MOSFETs of the same process type, of course, the power MOSFET with a larger rated operating current has a larger area and a larger coupled GS gate capacitance. Then, when driven by the same driving ability GATE signal, the rising slope of KCSA is small. The slope of KCSA can intuitively reflect the current capacity of the power MOSFET. In a conventional flyback switching power supply, the driving ability of the pre-stage of GATE is fixed. That is, the driving abilities of the upper driving NMOS transistor M1 and the lower driving NMOS transistor M2 in the pre-stage are fixed and will not change with the current capacity of the power MOSFET. When the voltage rising reference slope KBG is introduced, KCSA is calculated and compared with KBG. By compensating the slope of the pre-stage driving circuit, the driving abilities of the upper driving NMOS transistor M1 and the lower driving NMOS transistor M2 in the pre-stage are adjusted internally, and thus the speed of the rising and falling edges of GATE can be adjusted, i.e., the driving ability of GATE can be adjusted. In this way, power MOSFETs with different current capacities can be driven.

[0049] Meanwhile, when the power MOSFET is fixed and the AC voltage changes. Naturally, when VIN is large, the slope of KCSA is large. Naturally, when VIN is small, the slope of KCSA is small. The magnitude of the VIN voltage can also be intuitively reflected from the slope of KCSA. In a conventional primary feedback switching power supply, the driving ability of the pre-stage of GATE is fixed. That is, the driving abilities of the upper driving NMOS transistor M1 and the lower driving NMOS transistor M2 in the pre-stage are fixed and will not change with the change of the AC voltage VIN. When introducing the voltage rising reference slope KBG, by performing an operation and comparison between KCSA and KBG, and internally adjusting the driving abilities of the upper driving NMOS transistor M1 and the lower driving NMOS transistor M2 in the pre-stage through a slope compensation pre-stage driving circuit, the rising and falling edges of GATE can be adjusted, that is, the driving ability of GATE can be adjusted. In this way, the driving ability of the power MOSFET can be in a balanced state at different AC voltages VIN.

[0050] In the second case, when KCSB is greater than KCSA, after the PWM is turned off, within the internal logic delay TD time of the system, the rising slope of the CS voltage is fast, and the driving ability of the main control chip can no longer meet the requirements of the power MOSFET, and the chip enters a critical abnormal state. In this case, the slope compensation pre-stage driving voltage enters the fast response mode. On the one hand, it quickly increases the driving ability of the lower driving NMOS transistor, shortens the falling edge time of GATE, and the greater the falling slope of GATE, the faster the power MOSFET is turned off. On the other hand, it continuously compares the differences between the two voltage rising slopes KCSB and KCSA. When KSB exceeds KCSA and is greater than the threshold set by the internal circuit, it enters the protection state, GATE stops generating pulses, and the switching power supply system is protected.

Claims

1. A high-precision intelligent adjustment drive control system, characterized in that, Comprising: A per-cycle peak voltage detection circuit, which is used to detect the voltage CSA generated by the peak current of the primary winding of the transformer on the resistor RCS when PWM is turned off, and calculate the voltage rise slope KCSA of the primary winding of the transformer; An actual peak voltage detection circuit, which is used to detect the voltage CSB generated by the actual peak current of the primary winding of the transformer on the resistor RCS, calculate the voltage rise slope KCSB within the system delay from the PWM turn-off moment to the actual peak voltage turn-off moment, and calculate the system delay time TD signal from the PWM turn-off moment to the actual peak voltage turn-off moment; A voltage rise slope reference circuit, which generates an internally set threshold slope KBG signal according to the detected system delay time TD signal; An adaptive compensation drive circuit, which performs arithmetic comparison of KCSA and KCSB with the threshold slope KBG according to the detected two voltage rise slopes KCSA and KCSB, and outputs a CTRR signal for intelligently adjusting the drive turn-on ability and a CTRF signal for the drive turn-off ability. The CTRR signal and the CTRF signal are respectively used to control the upper drive NMOS transistor M1 and the lower drive NMOS transistor M2 of the front stage, obtain a GATE signal for intelligently adjusting the drive ability, and the GATE signal controls the power MOSFET to turn on or off.

2. The high-precision intelligent adjustment drive control system according to claim 1, wherein The input end of the per-cycle peak voltage detection circuit is connected to the internal control signal PWM, the voltage CS generated by the primary winding current of the transformer on the resistor RCS, and the internal reference voltage VA, and outputs the voltage CSA generated by the peak current of the primary winding at the PWM turn-off moment on the resistor RCS and the voltage rise slope KCSA of the primary winding.

3. The high-precision intelligent adjustment drive control system according to claim 2, wherein During the PWM conduction period, the primary winding current of the transformer rises linearly at a fixed slope. This current flows through the RCS resistor to generate the CS voltage. When the CS voltage is greater than the internal reference voltage VA, the entire control system starts to work; at the end of PWM, sample and hold the CS voltage as CSA, calculate the voltage difference ΔCSA between CSA and VA, and at the same time calculate the time difference ΔTA between the PWM turn-off moment and the VA moment. Obtain the primary winding voltage rise slope KCSA signal through the voltage difference ΔCSA and the time difference ΔTA.

4. The high-precision intelligent adjustment drive control system according to claim 1, characterized in that The input end of the actual peak voltage detection circuit is connected to the internal control signal PWM and the voltage CSA generated by the per-cycle current of the primary winding on the resistor RCS, and outputs the voltage CSB generated by the actual peak current on the primary winding of the transformer on the resistor RCS, the voltage rise slope KCSB within the system delay from the PWM turn-off moment to the actual peak voltage turn-off moment, and the system delay time TD signal.

5. The high-precision intelligent adjustment drive control system according to claim 4, wherein At the PWM turn-off moment, due to the internal logic delay of the system, the power MOSFET does not turn off immediately, and the current in the primary winding of the transformer does not turn off immediately. The CS voltage generated by this current flowing through the RCS resistor continues to rise; the actual peak voltage detection circuit detects the true CS peak voltage through the internal circuit and saves it as the CSB signal, detects the time difference TD signal from the PWM turn-off moment to the moment when the true CS peak voltage is reached, and calculates the voltage difference ΔCSB between CSB and CSA; The calculated voltage difference ΔCSB is the primary winding voltage rise slope KCSB signal within the system delay TD time.

6. The high-precision intelligent adjustment drive control system according to claim 1, characterized in that, The input end of the voltage rise slope reference circuit is connected to the system delay time TD signal, and the output is the internally set threshold slope KBG; according to the system delay time TD signal obtained in the actual peak voltage detection circuit, a voltage rise slope reference KBG signal is generated inside the circuit.

7. The high-precision intelligent adjustment drive control system according to claim 1, wherein The adaptive compensation drive circuit includes a slope compensation pre-drive circuit, a pre-drive upper NMOS transistor M1, and a pre-drive lower NMOS transistor M2.

8. The high-precision intelligent adjustment drive control system according to claim 7, characterized in that, The input end of the slope compensation pre-drive circuit is connected to the internal control signal PWM, the KCSA signal, the KCSB signal, and the KBG signal, and the output is the CTRR signal and the CTRF signal.

9. The high-precision intelligent adjustment drive control system according to claim 8, wherein The CTRR signal is connected to the gate terminal of the pre-drive upper NMOS transistor M1, the CTRF signal is connected to the gate terminal of the pre-drive lower NMOS transistor M2, the drain terminal of the pre-drive upper NMOS transistor M1 is connected to the internal high-voltage power supply VDD of the chip, the source terminal of the pre-drive upper NMOS transistor M1 is connected to the drain terminal of the pre-drive lower NMOS transistor M2, and the GATE signal is output. The source terminal of the lower NMOS transistor M2 is grounded, and the GATE signal is connected to the gate terminal of the power MOSFET.

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