Delay device and delay control method

Abstract

This invention provides a delay device and a delay control method. The delay device includes at least one current-controlled delay group and at least one switch. The at least one current-controlled delay group is coupled to a transmission line, and each current-controlled delay group includes at least one current-controlled delay unit, each current-controlled delay unit providing a delay according to a control voltage. Switches are respectively coupled between the current-controlled delay group and the transmission line, and each switch is turned on or off according to the bit of an enable signal applied to it. This invention can dynamically adjust the generated delay and is unaffected by parasitic capacitance.

Description

Technical Field

[0001] This invention relates to a delay device and a delay control method, and more particularly to a delay device and a delay control method that do not require an encoder and can be dynamically adjusted. Background Technology

[0002] With the advancement of electronic technology, integrated circuit design has become a crucial technology. In circuit design, controlling the propagation delay on transmission lines is often necessary. Existing technologies offer various methods to adjust this delay. For example, setting the value of a capacitor on the transmission line or controlling the pull-up or pull-down current source of a buffer can generate a delay. However, the resulting delay can be difficult to control due to parasitic capacitance transmitted to the line, or the adjustable range of the controllable delay is often limited, failing to meet design specifications. Furthermore, existing technologies often require complex decoders to program the propagation delay of the provided transmission lines, and this approach also struggles to control the linearity of the delay adjustment, failing to meet high-precision design specifications. Summary of the Invention

[0003] This invention relates to a delay device and a delay control method that can dynamically adjust the generated delay without the need for an encoder and is unaffected by parasitic capacitance.

[0004] According to an embodiment of the present invention, the delay device includes at least one current-controlled delay unit and at least one switch. Current-controlled delay groups are coupled to a transmission line, each current-controlled delay group including at least one current-controlled delay unit, each current-controlled delay unit providing a delay according to a control voltage. Switches are respectively coupled between the current-controlled delay groups and the transmission line, each switch being turned on or off according to a bit of an enable signal applied thereto.

[0005] According to an embodiment of the present invention, the delay control method includes: setting at least one current control delay group on a transmission line, each current control delay group including at least one current control delay device; providing a control voltage to each current control delay device to cause each current control delay device to provide a delay; setting a plurality of switches between the transmission line and the current control delay group respectively; and providing corresponding bits of an enable signal to each switch respectively to cause each switch to be turned on or off respectively. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0007] Figure 1This is a schematic diagram of a delay device according to an embodiment of the present invention;

[0008] Figure 2 This is a circuit diagram of a delay device according to another embodiment of the present invention;

[0009] Figure 3A as well as Figure 3B This is a schematic diagram illustrating other embodiments of the current-controlled delay device in the delay apparatus of this invention;

[0010] Figure 4 This is a schematic diagram of a delay device according to another embodiment of the present invention;

[0011] Figure 5A And 5B is the present invention Figure 4 Equivalent circuit diagram of the delay device 400 in the embodiment when performing delay adjustment operation;

[0012] Figure 6 This is a flowchart of a delay control method according to an embodiment of the present invention.

[0013] Explanation of icon numbers

[0014] 100, 200, 400: Delay devices;

[0015] 110~1N0: Current-controlled delay group;

[0016] 410: Enable signal generator

[0017] 420: Control Voltage Generator

[0018] BUF1, BUF2: Buffers;

[0019] D11~DN1: Diodes;

[0020] DC11~DCNM, DC11A~DCNMB: Current-controlled delay unit;

[0021] EN: Enable signal;

[0022] EN <0> ~EN <n-1>:Bit;

[0023] IN: Input signal;

[0024] M11~MN1, M31, M32, M33: Transistors;

[0025] MP1, MP2, MN1, MN2: Transistors;

[0026] OUT: Output signal;

[0027] SW1~SWN, SW1A~SWNB: Switches;

[0028] TWR, TWR1, TWR2: Transmission wires;

[0029] VC: Control voltage;

[0030] VCC: Power supply voltage;

[0031] VSS: Reference ground terminal;

[0032] S610~S640: Control steps. Detailed Implementation

[0033] In the following detailed description, reference is made to the accompanying drawings, which form part of the description. In the drawings, similar symbols generally denote similar components unless the context otherwise requires.

[0034] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a delay device according to an embodiment of the present invention. The delay device 100 includes a plurality of current-controlled delay groups 110-1N0 and a plurality of switches SW1-SWN. Each current-controlled delay group may include at least one current-controlled delay unit. In some embodiments, the number of current-controlled delay units included in each current-controlled delay group may not be the same. For example, as... Figure 1 As shown, the first current-controlled delay group 110 includes one current-controlled delay unit DC11; the second current-controlled delay group 110 includes two current-controlled delay units DC21 and DC22; and the Nth current-controlled delay group 1N0 includes M current-controlled delay units DCN1 to DCNM, where M can be equal to 2. N-1 N is a positive integer. That is, in this embodiment, the ratio of the number of current-controlled delay units in two adjacent current-controlled delay groups 110 to 1N0 is 1:2. And the ratio of the number of current-controlled delay units in each of the current-controlled delay groups 110 to 1N0 in this embodiment is, in order, 1:2:4:…:2. N-1 .

[0035] Switches SW1 to SWN are respectively coupled between the current control delay groups 110 to 1N0 and the transmission line TWR. In this embodiment, the transmission line TWR can be coupled between buffer BUF1 and buffer BUF2. The input terminal of buffer BUF1 receives the input signal IN, and the output terminal of buffer BUF2 provides the output signal OUT. Switches SW1 to SWN respectively receive multiple bits of the enable signal EN. <0> ~EN <n-1>Among them, EN is the position. <0> This can be the least significant bit (LSB) of the enable signal EN. <n-1>Then it can be the most significant bit (MSB) of the enable signal EN.

[0036] In other embodiments of the present invention, the number of current-controlled delay groups can be at least one, and the number of corresponding connected switches can also be at least one. Each current-controlled delay group may include one or more current-controlled delay units, without any specific quantity limitation.

[0037] On the other hand, the number of current control delay units in the current control delay groups 110 to 1N0 can be determined based on the multiple bits of the enable signal EN received by the switches SW1 to SW. <0> ~EN <n-1>The bits are set in high-low order. The least significant bit (EN bit) of the receive enable signal EN is used. <0> The current control delay group 110 coupled to switch SW1 includes only one (=2) 0 Current control delay DC11; receives the second least significant bit (bit EN) of the enable signal EN. <1> The current control delay group 110 coupled to the switch SW2 includes 2 (=2) 1 Current-controlled delay units DC21 and DC22. And so on, receiving the most significant bit (bit EN) of the enable signal EN. <n-1>The current control delay group 110 coupled to the switch SWN includes M (=2) units. N-1 Current-controlled delay units DCN1 to DCNM. That is, multiple bits of the enable signal EN. <0> ~EN <n-1>The bit order is positively correlated with the number of current control delay units DCN1 to DCNM in the corresponding current control delay groups 110 to 1N0.

[0038] In this embodiment, each current-controlled delay unit receives a control voltage VC and provides a delay based on the control voltage VC. Each current-controlled delay unit can generate current internally based on the control voltage VC, and determine the amount of delay provided by the charging or discharging behavior of the current. The adjustment of the delay amount for signal transmission on the transmission line TWR can be achieved by controlling the on or off state of each switch. Specifically, when all switches SW1 to SWN are respectively based on multiple bits of the enable signal EN... <0> ~EN <n>When all switches are disconnected, the signal transmission delay on the transmission line TWR is minimized. When at least one switch from SW1 to SWN is turned on according to multiple bits of the enable signal EN, the signal transmission delay on the transmission line TWR can be increased. Therefore, the degree of increase in the signal transmission delay on the transmission line TWR can be determined by the number of current-controlled delay units effectively connected to the transmission line TWR. Taking the example that each of the current-controlled delay units DCN1 to DCNM can provide the same unit delay X, when only switch SW1 is turned on, the signal transmission delay on the transmission line TWR can be increased by 1X; when only switch SW2 is turned on, the signal transmission delay on the transmission line TWR can be increased by 2X. Similarly, when only switch SWN is turned on, the signal transmission delay on the transmission line TWR can be increased by 2... N-1 X. Of course, in this embodiment, multiple switches SW1 to SWN can be turned on simultaneously. For example, when both switches SW1 and SW2 are turned on, the signal transmission delay on the transmission line TWR can be increased by 3X. From the above description, it can be seen that when all switches SW1 to SWN are turned on, the maximum increase in signal transmission delay on the transmission line TWR is equal to (2 N -1)X.

[0039] Furthermore, in this embodiment of the invention, the signal transmission delay on the transmission line TWR can also be adjusted by adjusting the control voltage VC. Specifically, by adjusting the control voltage VC, each of the current-controlled delay devices DCN1 to DCNM can provide the same unit delay X'. When only switch SW1 is turned on, the signal transmission delay on the transmission line TWR can be increased to 1X'. When both switches SW1 and SW2 are turned on, the signal transmission delay on the transmission line TWR can be increased by 3X'. From the above description, it can be seen that when all switches SW1 to SWN are turned on, the maximum increase in the signal transmission delay on the transmission line TWR is equal to (2... N -1)X'.

[0040] It is worth mentioning that, in this embodiment of the invention, the number of bits of the enable signal EN can be set according to actual design requirements, without a specific limitation on the number of bits. Specifically, when the delay adjustment in the design specifications requires relatively high resolution, the enable signal EN can have a relatively high number of bits, such as 8 or 16 bits. Conversely, when the delay adjustment in the design specifications requires relatively low resolution, the enable signal EN can have a relatively low number of bits, such as 2 or 4 bits.

[0041] Furthermore, in this embodiment, each current-controlled delayer can have the same circuit architecture and provide the same delay.

[0042] Please refer to the following: Figure 2 , Figure 2 This is a circuit diagram of a delay device according to another embodiment of the present invention. The delay device 200 includes a plurality of switches SW to SWN and a plurality of current-controlled delay groups. The plurality of current-controlled delay groups are respectively coupled to the transmission line TWR through switches SW to SWN.

[0043] A transmission line TWR is coupled between buffers BUF1 and BUF2. Buffer BUF1 includes transistors MP1 and MN1 connected in series between the power supply voltage VCC and the reference ground terminal VSS. The control terminals of transistors MP1 and MN1 receive the input signal IN, and the coupled terminals of transistors MP1 and MN1 are coupled to the transmission line TWR. Buffer BUF2 includes transistors MP2 and MN2 connected in series between the power supply voltage VCC and the reference ground terminal VSS. The control terminals of transistors MP2 and MN2 are coupled to the transmission line TWR, and the coupled terminals of transistors MP1 and MN1 generate the output signal OUT. In this embodiment, buffers BUF1 and BUF2 are inverters. In other embodiments, buffers BUF1 and BUF2 can be any buffer circuit without certain limitations.

[0044] In this embodiment, each of the current-controlled delayers DC11 to DCNM has the same circuit architecture. Taking the current-controlled delayer DC11 as an example, DC11 includes a transistor M21 and a diode D21. Transistor M21 and diode D21 are connected in series between switch SW1 and reference ground VSS. The control terminal of transistor M21 receives a control voltage VC and provides current according to the control voltage VC. The anode of diode D21 is coupled to transistor M21, and the cathode of diode D21 is coupled to reference ground VSS. The current provided by transistor M21 can charge or discharge through diode D21, thereby generating a delay. The current-controlled delayer DN1 includes a transistor MN1 and a diode DN1. Transistor MN1 and diode DN1 have the same electrical characteristics as transistor M11 and diode D11, respectively.

[0045] The current-controlled delay units DC11 to DCNM can perform coarse adjustment of the signal transmission delay on the transmission line TWR based on the control voltage VC. Fine adjustment of the signal transmission delay on the transmission line TWR can be performed by turning each of the switches SW1 to SWN on or off.

[0046] Incidentally, in this embodiment, the coupling order of transistor M21 and diode D21 in the current-controlled delay circuit DC11 can be interchanged and is not limited to the following configuration: Figure 2 As shown.

[0047] Please refer to the following: Figure 3A as well as Figure 3B , Figure 3A as well as Figure 3B This is a schematic diagram illustrating another embodiment of the current-controlled delay device in the delay apparatus of this invention. Figure 3A In this circuit, the current-controlled delay unit 310 includes transistors M31 and M32 connected in series. Transistor M32 is an N-type transistor coupled in a diode configuration. The first terminal of transistor M32 is coupled to a control terminal and then to transistor M31. The second terminal of transistor M32 is coupled to a reference ground terminal VSS. The control terminal of transistor M31 receives a control voltage VC and generates a current based on the control voltage VC.

[0048] exist Figure 3B In this circuit, the current-controlled delay unit 320 includes transistors M31 and M33 connected in series. Transistor M33 is a P-type transistor and is also coupled in a diode configuration. The second terminal of transistor M33 is coupled to the control terminal and to the reference ground terminal VSS. The second terminal of transistor M32 is coupled to transistor M31. The control terminal of transistor M31 receives a control voltage VC and generates current based on the control voltage VC.

[0049] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of a delay device according to another embodiment of the present invention. The delay device 400 includes current-controlled delay units DC11A-DCNMA, DC11B-DCNMB, switches SW1A-SWNA, SW1B-SWNB, an enable signal generator 410, and a control voltage generator 420. The current-controlled delay units DC11A-DCNMA are coupled to the transmission line TWR1 via switches SW1A-SWNA, and the current-controlled delay units DC11B-DCNMB are coupled to the transmission line TWR2 via switches SW1B-SWNB. The current-controlled delay units DC11A-DCNMA and switches SW1A-SWNA are used to adjust the signal transmission delay on the transmission line TWR1, while the current-controlled delay units DC11B-DCNMB and switches SW1B-SWNB are used to adjust the signal transmission delay on the transmission line TWR2.

[0050] Regarding the adjustment of signal transmission delay, detailed descriptions have been provided in the preceding embodiments, and will not be repeated here. Unlike the preceding embodiments, in this embodiment, the enable signal generator 410 is coupled to switches SW1A-SWNA and SW1B-SWNB. The enable signal generator 410 generates an enable signal EN, and controls the on / off state of switches SW1A-SWNA and SW1B-SWNB through multiple bits of the enable signal EN. In this embodiment, the enable signal generator 410 can generate multiple bits of the enable signal EN based on a delay fine-tuning signal. The enable signal generator 410 can encode the delay fine-tuning signal to generate the multiple bits of the enable signal EN.

[0051] A control voltage generator 420 is coupled to current control delay units DC11A to DCNMB to generate a control voltage VC. The control voltage generator 420 adjusts the control voltage VC according to a coarse delay adjustment mechanism. Specifically, the control voltage generator 420 can decrease the delay provided by each current control delay unit DC11A to DCNMB by increasing the control voltage VC, and can increase the delay provided by each current control delay unit DC11A to DCNMB by decreasing the control voltage VC. Taking the example of the control voltage generator 420 executing the coarse delay adjustment mechanism based on a digital signal to generate the control voltage VC, the control voltage generator 420 can be a digital-to-analog converter circuit.

[0052] For details on adjusting the movements, please refer to [link / reference]. Figure 5A And 5B. Figure 5A And 5B is the present invention Figure 4 The equivalent circuit diagram of the delay device 400 in the embodiment when performing a delay adjustment operation. Figure 5A In this configuration, when all switches SW1A to SWNB are open, all current-controlled delay circuits DC11A to DCNMB are electrically isolated from transmission lines TWR1 and TWR2. At this time, transmission lines TWR1 and TWR2 experience minimal signal transmission delay. Figure 5B In this configuration, when all switches SW1A to SWNB are turned on, all current-controlled delay circuits DC11A to DCNMA are electrically connected to transmission line TWR1, and all current-controlled delay circuits DC11B to DCNMB are electrically connected to transmission line TWR2. At this time, transmission lines TWR1 and TWR2 have the maximum signal transmission delay.

[0053] Of course, the switches SW1A to SWNB in ​​this embodiment of the invention are not limited to being fully on or fully off. The delay device 400 can select which switches SW1A to SWNB to be turned on according to the required delay amount. And the signal transmission delay on the transmission lines TWR1 and TWR2 can be adaptively adjusted by dynamically adjusting the turned-on switches.

[0054] Please refer to the following: Figure 6 , Figure 6 This is a flowchart of a delay control method according to an embodiment of the present invention. In step S610, at least one current-controlled delay group is provided on the transmission line, each current-controlled delay group including at least one current-controlled delay device. In step S620, a control voltage is provided to the current-controlled delay device to cause each current-controlled delay device to provide a delay. In step S630, a switch is provided between the transmission line and each current-controlled delay group. Then, in step S640, the corresponding bit of an enable signal is provided to each switch to turn each switch on or off.

[0055] The implementation details of the above steps have been described in detail in the aforementioned embodiments, and will not be repeated here.

[0056] According to the above, embodiments of the present invention provide at least one current-controlled delay group on the transmission line, with each current-controlled delay group having one or more current-controlled delay devices. A switch is provided between each current-controlled delay group and the transmission line. By controlling the on / off state of each switch, the number of current-controlled delay devices actually connected to the transmission line can be controlled, effectively controlling the transmission delay amount. Based on the current-controlled delay group configuration, the delay device of the present invention does not require a complex decoder to achieve digital delay programming. Furthermore, the present invention provides both coarse adjustment (adjusting the control voltage) and fine adjustment (adjusting the on / off state of the switch) mechanisms for adjusting the delay amount, expanding the adjustment range and resolution, and effectively improving the linearity of the delay adjustment. The current-controlled delay device of the present invention also reduces the impact of parasitic capacitance through current control.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.< / n>

Claims

1. A delay device, characterized in that, include: Multiple current-controlled delay groups are coupled to a transmission line, and the multiple current-controlled delay groups include a different number of current-controlled delay units, each of which provides a delay according to a control voltage; as well as Multiple switches, each corresponding to a multiple current-controlled delay group, each of the multiple switches being coupled between the corresponding current-controlled delay group and the transmission line, and each of the multiple switches being turned on or off according to the bit of the enable signal applied to it. Each of the current-controlled delay units includes: A first transistor, which provides current according to the control voltage; and A diode, connected in series with the first transistor between the corresponding switch and a reference ground terminal, performs a charging or discharging action according to the current to provide the delay.

2. The delay device according to claim 1, characterized in that, The diode is a second transistor configured as a diode. The first terminal of the second transistor is coupled to the first transistor. The control terminal of the second transistor is coupled to the first terminal of the second transistor. The second terminal of the second transistor is coupled to the reference ground terminal. The second transistor is an N-type transistor.

3. The delay device according to claim 1, characterized in that, The diode is a second transistor configured as a diode. The first terminal of the second transistor is coupled to the first transistor, the control terminal of the second transistor is coupled to the second terminal of the second transistor, and the second terminal of the second transistor is coupled to the reference ground terminal. The second transistor is a P-type transistor.

4. The delay device according to claim 1, characterized in that, The ratio of the number of current-controlled delay units included in two adjacent current-controlled delay groups is 1:

2.

5. The delay device according to claim 1, characterized in that, Each bit of the enable signal controls the on or off state of a switch.

6. The delay device according to claim 5, characterized in that, The bit order of each bit of the enable signal is positively correlated with the number of the plurality of current-controlled delay units in the corresponding current-controlled delay group.

7. The delay device according to claim 1, characterized in that, Also includes: An enable signal generator, coupled to each of the at least one switch, is used to generate an enable signal that controls each switch respectively, based on a delay fine-tuning signal.

8. The delay device according to claim 1, characterized in that, Also includes: A control voltage generator, coupled to the current control delay unit, is used to generate the control voltage and adjust the control voltage according to a delay coarse adjustment mechanism.

9. A delay control method, characterized in that, include: Multiple current-controlled delay groups are set on the transmission line, and each of the multiple current-controlled delay groups includes a different number of current-controlled delay units; A control voltage is provided to each of the current-controlled delay units so that each current-controlled delay unit provides a delay according to the control voltage; A switch is provided between the transmission line and each current-controlled delay group; as well as Each switch is given a corresponding bit of the enable signal so that each switch is turned on or off respectively; Each of the current-controlled delay units includes: A first transistor, which provides current according to the control voltage; and A diode, connected in series with the first transistor between the corresponding switch and a reference ground terminal, performs a charging or discharging action according to the current to provide the delay.

10. The delay control method according to claim 9, characterized in that, Also includes: The ratio of the number of current-controlled delay units included in two adjacent current-controlled delay groups is 1:

2.

11. The delay control method according to claim 9, characterized in that, Also includes: Each bit of the enable signal controls the on or off of a switch.

12. The delay control method according to claim 11, characterized in that, The bit order of each bit of the enable signal is positively correlated with the number of the plurality of current-controlled delay units in the corresponding current-controlled delay group.

13. The delay control method according to claim 9, characterized in that, Also includes: The enable signal is generated based on the delay fine adjustment signal; as well as The control voltage is adjusted according to the delay coarse adjustment mechanism.

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