Method for manufacturing a flash memory device requiring photolithography rework

Abstract

The present invention provides a method for manufacturing a flash memory device that requires photolithography rework, including: obtaining the amount of charge on the side surface of the dielectric sidewall in multiple previous batches; obtaining the charge density on the side surface of the dielectric sidewall; obtaining the minimum width dimension of the dielectric sidewall; redesigning the mask to redefine the dimension of the dielectric sidewall in terms of width; forming a patterned photoresist layer; etching a certain thickness of the dielectric layer to obtain the shallow trench isolation structure located in the substrate and the dielectric sidewall covering the side surface of the gate. According to the charge density and some other parameters, the present application obtains the minimum width dimension of the dielectric sidewall and redesigns the mask to redefine the dimension of the dielectric sidewall in terms of width, so that the dielectric sidewall after photolithography rework can withstand high voltage in the case of plate discharge after accumulating a large amount of charge, avoiding the situation where the gate and / or the substrate are burned out due to high voltage breakdown, and improving the yield of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly relates to a method for preparing a flash memory device that requires photolithography rework. Background Art

[0002] During the Cell Recess (Cell Remove STI (CRS), forming a shallow trench isolation structure by etching back the dielectric layer) process of a 55nm NOR flash memory device, the photoresist after exposure and development has poor effect and does not expose the surfaces of all dielectric layers that need to be etched back. At this time, a photolithography rework process is required to remove the poorly performing photoresist, re-coat the photoresist to expose the surfaces of all dielectric layers that need to be etched back, and then perform the dielectric layer etching back process to obtain a shallow trench isolation structure (STI). Among them, during the process of etching back the dielectric layer to obtain STI, a certain width of dielectric layer will surely remain on the side surface of the gate, thus forming a dielectric sidewall, and this dielectric sidewall still needs to be removed by processes such as photolithography, etching, and cleaning processes.

[0003] However, process engineers found that pattern damage (device pattern damage) defects are likely to occur after the photolithography rework process. The abnormal wafer defects are distributed in a ring map, and the defects are distributed in the AA area (the junction position of STI and poly) at the junction of the periphery of the Cell area and the Cell area.

[0004] After investigation, it was found that during the CRS photolithography rework and the process of etching back the dielectric layer, due to the influence of other manufacturing processes such as the plasma etching process, a large amount of charge will accumulate on the two side surfaces (equivalent to the two electrodes of a capacitor) of the dielectric sidewall remaining on the side surface of the gate. The dielectric layer material of the dielectric sidewall is equivalent to the intermediate dielectric of the capacitor. In the subsequent dry etching process and wet etching process, the dielectric layer becomes thinner, causing the electrodes of the dielectric sidewall to discharge, thus causing the polysilicon gate (poly) and / or the substrate to be broken down by high voltage and burned out. Summary of the Invention

[0005] The present application provides a method for preparing a flash memory device that requires photolithography rework, which can solve the problem that the polysilicon gate (poly) and / or the substrate are broken down by high voltage caused by CRS photolithography rework.

[0006] On the one hand, an embodiment of the present application provides a method for manufacturing a flash memory device that requires photolithography rework. A substrate is provided, on which a gate oxide layer and a gate located on the gate oxide layer are formed. Trenches are formed in the substrate on both sides of the gate, and the trenches are filled with a dielectric layer, and the upper surface of the dielectric layer is not lower than the upper surface of the gate. Among them, the flash memory device needs to perform photolithography process rework before etching a certain thickness of the dielectric layer to obtain a shallow trench isolation structure. The method for manufacturing the flash memory device that requires photolithography rework includes:

[0007] Obtain the electric charge amount on the side surface of the dielectric sidewall that fits the gate in multiple batches where the gate and / or the substrate were broken down by high voltage due to photolithography rework problems before; wherein, during the process of etching a certain thickness of the dielectric layer to obtain a shallow trench isolation structure, a certain width of the dielectric layer will remain on the side surface of the gate to form the dielectric sidewall;

[0008] According to the electric charge amount on the side surface of the dielectric sidewall, obtain the charge density on the side surface of the dielectric sidewall;

[0009] According to the charge density, obtain the minimum width dimension of the dielectric sidewall;

[0010] According to the minimum width dimension of the dielectric sidewall, redesign the mask to redefine the width dimension of the dielectric sidewall;

[0011] Form a photoresist layer that covers the gate and the dielectric layer;

[0012] Use the mask to expose and develop the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer covers the area where the dielectric sidewall needs to be formed;

[0013] Using the patterned photoresist layer as a mask, etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure in the substrate and the dielectric sidewall that covers the side surface of the gate.

[0014] Optionally, in the method for manufacturing the flash memory device that requires photolithography rework, during the process of using the patterned photoresist layer as a mask to etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure and the dielectric sidewall, the width of the obtained dielectric sidewall is greater than or equal to the minimum width dimension of the dielectric sidewall.

[0015] Optionally, in the method for manufacturing the flash memory device that requires photolithography rework, the calculation formula for the charge density on the side surface of the dielectric sidewall is as follows:

[0016] σ = Q÷S;

[0017] Among them, σ is the charge density of the side surface of the dielectric sidewall; Q is the amount of charge on the side surface of the dielectric sidewall; S is the area of the side surface of the dielectric sidewall.

[0018] Optionally, in the method for manufacturing a flash memory device that requires photolithography rework, the calculation formula for the minimum width dimension of the dielectric sidewall is as follows:

[0019]

[0020] Among them, d is the minimum width dimension of the dielectric sidewall; k is a constant; E b is the breakdown field strength; σ is the charge density of the side surface of the dielectric sidewall; ε is the dielectric constant of the dielectric layer.

[0021] Optionally, in the method for manufacturing a flash memory device that requires photolithography rework, the dielectric layer is a silicon oxide layer.

[0022] Optionally, in the method for manufacturing a flash memory device that requires photolithography rework, in the process of etching a certain thickness of the dielectric layer with a patterned photoresist layer as a mask to obtain the shallow trench isolation structure and the dielectric sidewall, the upper surface of the obtained shallow trench isolation structure is not higher than the upper surface of the gate oxide layer.

[0023] Optionally, in the method for manufacturing a flash memory device that requires photolithography rework, after etching a certain thickness of the dielectric layer with a patterned photoresist layer as a mask to obtain the shallow trench isolation structure and the dielectric sidewall, the method for manufacturing a flash memory device that requires photolithography rework further includes:

[0024] Removing the dielectric sidewall by a dry etching process;

[0025] Cleaning the side surface of the gate by a wet cleaning process.

[0026] Optionally, in the method for manufacturing a flash memory device that requires photolithography rework, before obtaining the charge density of the side surface of the dielectric sidewall that is in contact with the gate in multiple batches where the gate and / or the substrate were broken down by high voltage due to photolithography rework problems before, the method for manufacturing a flash memory device that requires photolithography rework further includes:

[0027] Coating and forming a layer of photoresist on the gate and the dielectric layer;

[0028] Exposing and developing the photoresist to obtain a patterned photoresist, wherein the patterned photoresist does not expose the entire surface of the dielectric layer and photolithography process rework is required;

[0029] Removing the patterned photoresist.

[0030] The technical solution of the present application has at least the following advantages:

[0031] In the present application, the charge density is obtained according to the amount of charge, and then the minimum width dimension of the dielectric sidewall is obtained according to the charge density and some other parameters related to the dielectric sidewall; then, according to the minimum width dimension of the dielectric sidewall, the mask is redesigned to redefine the dimension of the dielectric sidewall in width, so that the dielectric sidewall after lithography rework can withstand high voltage in the case of plate discharge after accumulating a large amount of charge, avoiding the situation that the gate and / or the substrate are broken down and burned by high voltage, and improving the yield of the device. Description of the Drawings

[0032] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0033] Figure 1 is a cross-sectional schematic diagram of a flash memory device before the lithography process rework process according to an embodiment of the present invention;

[0034] Figure 2 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention;

[0035] Figure 3 is a cross-sectional schematic diagram of a flash memory device with a dielectric sidewall formed after the lithography process rework process according to an embodiment of the present invention;

[0036] Figure 4 is Figure 3 a top view schematic diagram of a flash memory device with a dielectric sidewall formed;

[0037] Figure 5 is a cross-sectional schematic diagram of a flash memory device with the dielectric sidewall removed according to an embodiment of the present invention;

[0038] Among them, the reference numerals are explained as follows:

[0039] 10 - Substrate, 20 - Gate oxide layer, 30 - Gate, 40 - Dielectric layer, 41 - Shallow trench isolation structure, 42 - Dielectric sidewall, a - Dimension of the dielectric sidewall in width. Detailed Embodiments

[0040] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0041] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0042] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0043] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0044] Reference Figure 1 , Figure 1 is a cross-sectional schematic diagram of a flash memory device before the photolithography process rework process in an embodiment of the present invention. A substrate 10 is provided, a gate oxide layer 20 is formed on the substrate 10, and a gate electrode 30 is formed on the gate oxide layer 20. Trenches are formed in the substrate 10 on both sides of the gate electrode 30, and a dielectric layer 40 is filled in the trenches. The upper surface of the dielectric layer 40 is not lower than the upper surface of the gate electrode 30. Among them, the flash memory device needs to perform a photolithography process rework before etching a certain thickness of the dielectric layer 40 to obtain a shallow trench isolation structure 41.

[0045] In this embodiment, a layer of photoresist is coated before the photolithography process rework process. However, the effect of the photoresist pattern formed by exposure and development is not good, so this layer of photoresist pattern with poor effect will be removed for photolithography rework. Specifically, it can include the following steps:

[0046] A layer of photoresist is coated and formed on the gate 30 and the dielectric layer 40;

[0047] The photoresist is exposed and developed to obtain a patterned photoresist. Among them, the entire surface of the dielectric layer that needs to be exposed is not exposed by the patterned photoresist. At this time, photolithography process rework is required;

[0048] Before photolithography rework, the patterned photoresist is removed.

[0049] Next, the embodiment of the present application provides a method for manufacturing a flash memory device that requires photolithography rework. Refer to Figure 2 , Figure 2 is a flowchart of the method for manufacturing a flash memory device according to an embodiment of the present invention. The method for manufacturing a flash memory device that requires photolithography rework includes:

[0050] Step S10: Obtain the electric charge amount on the side surface of the dielectric sidewall 42 that fits the gate in multiple batches where the gate 30 and / or the substrate 10 were previously broken down by high voltage due to photolithography rework problems; among them, during the process of etching a certain thickness of the dielectric layer 40 to obtain the shallow trench isolation structure 41, a certain width of the dielectric layer 40 will remain on the side surface of the gate 30 to form the dielectric sidewall 42, and the dielectric sidewall 42 covers the side surface of the gate 30. Specifically, obtain the electric charge amount on the side surface of the dielectric sidewall 42 in at least two batches where the gate and / or the substrate were previously broken down by high voltage due to photolithography rework problems. In this embodiment, the electric charge amount Q on the side surface of the dielectric sidewall can be measured and obtained by a semiconductor instrument.

[0051] Preferably, the dielectric layer 40 can be a silicon oxide layer, and the material is silicon dioxide.

[0052] Step S20: Obtain the charge density on the side surface of the dielectric sidewall 42 according to the electric charge amount on the side surface of the dielectric sidewall 42. Specifically, the calculation formula for the charge density on the side surface of the dielectric sidewall 42 is as follows:

[0053] σ = Q ÷ S;

[0054] Among them, σ is the charge density on the side surface of the dielectric sidewall 42; Q is the electric charge amount on the side surface of the dielectric sidewall 42; S is the area of the side surface of the dielectric sidewall 42.

[0055] Step S30: Obtain the minimum width dimension of the dielectric sidewall 42 according to the charge density. Specifically, the calculation formula for the minimum width dimension of the dielectric sidewall 42 is as follows:

[0056]

[0057] Wherein, d is the minimum width dimension of the dielectric sidewall; k is a constant; E b is the breakdown field strength; σ is the charge density on the side surface of the dielectric sidewall; ε is the dielectric constant of the dielectric layer.

[0058] In this embodiment, the breakdown field strength E b , the charge density σ on the side surface of the dielectric sidewall, and the dielectric constant ε of the dielectric layer can all be obtained by referring to relevant materials. The constant k is selected according to the breakdown resistance performance of the silicon dioxide material, and can be set according to actual conditions, or can be set according to the experimental experience summary of the high-voltage breakdown of the relevant silicon dioxide dielectric layer.

[0059] Specifically, after a large amount of charge accumulates on the two opposite side surfaces, the dielectric sidewall 42 is equivalent to a capacitor, and the calculation formula for the voltage across the capacitor (dielectric sidewall) is: Further, the calculation formula for the breakdown voltage of the dielectric sidewall 42 is: U 击穿 = E b ×a + k. Wherein, a is the dimension of the dielectric sidewall 42 in terms of width.

[0060] When U 介质侧墙 ≥ U 击穿 , it can be ensured that the dielectric sidewall 42 will not be broken down. Substituting the two formulas of and U 击穿 = E b ×a + k into U 介质侧墙 ≥ U 击穿 , it can be obtained that Therefore, the minimum width dimension d of the dimension a of the dielectric sidewall 42 in terms of width is

[0061] Step S40: According to the minimum width dimension of the dielectric sidewall, redesign the mask to redefine the dimension a of the dielectric sidewall 42 in terms of width.

[0062] Step S50: Form a photoresist layer, and the photoresist layer covers the gate 30 and the dielectric layer 40;

[0063] Step S60: Use the redesigned mask to expose and develop the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer covers the upper surface area where the dielectric sidewall 42 needs to be formed.

[0064] Step S70: Refer to Figure 3 and Figure 4 , Figure 3 is a cross-sectional schematic diagram of a flash memory device with a dielectric sidewall formed after the photolithography process rework process of the embodiment of the present invention, Figure 4 isFigure 3 Top view schematic diagram of a flash memory device with a dielectric sidewall formed. Using the patterned photoresist layer as a mask, etching a certain thickness of the dielectric layer 40 to obtain the shallow trench isolation structure 41 in the substrate 10 and the dielectric sidewall 42 covering the side surface of the gate 30.

[0065] Preferably, the size a of the obtained dielectric sidewall 42 in width is greater than or equal to the minimum width size d of the dielectric sidewall 42.

[0066] Furthermore, the upper surface of the shallow trench isolation structure 41 obtained by etching a certain thickness of the dielectric layer 40 is not higher than the upper surface of the gate oxide layer 20. In this embodiment, the upper surface of the shallow trench isolation structure 41 obtained by etching a certain thickness of the dielectric layer 40 is flush with the upper surface of the gate oxide layer 20.

[0067] In this application, by obtaining the charge density according to the amount of charge, and then according to the charge density and some other parameters related to the dielectric sidewall 42, obtaining the minimum width size of the dielectric sidewall 42; then according to the minimum width size of the dielectric sidewall 42, redesigning the mask to redefine the size of the dielectric sidewall 42 in width, so that the dielectric sidewall 42 after photolithography rework can withstand high voltage in the case of plate discharge after accumulating a large amount of charge, avoiding the situation that the gate and / or the substrate are burned out due to high voltage breakdown, and improving the yield of the device.

[0068] In this embodiment, referring to Figure 5 , Figure 5 is a cross-sectional schematic diagram of a flash memory device removing the dielectric sidewall according to an embodiment of the present invention. After using the patterned photoresist layer as a mask and etching a certain thickness of the dielectric layer to obtain the shallow trench isolation structure and the dielectric sidewall, after the dielectric sidewall 42 withstands high voltage, the preparation method of the flash memory device that needs photolithography rework may further include the step of removing the dielectric sidewall 42, which may specifically include: Step 1, using a dry etching process to remove the dielectric sidewall 42; Step 2, using a wet cleaning process to clean the side surface of the gate 30 to completely remove the dielectric sidewall 42.

[0069] Obviously, the above embodiments are only examples clearly described and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A method for manufacturing a flash memory device that requires photolithography rework, providing a substrate, a gate oxide layer is formed on the substrate, and a gate is formed on the gate oxide layer. Trenches are formed in the substrate on both sides of the gate, and a dielectric layer is filled in the trenches. The upper surface of the dielectric layer is not lower than the upper surface of the gate, wherein, Before etching a certain thickness of the dielectric layer to obtain a shallow trench isolation structure, a photolithography process rework is required for the flash memory device. The method for manufacturing the flash memory device that requires photolithography rework includes: Obtaining the electric charge amount on the side surface of the dielectric sidewall that is in contact with the gate in multiple batches where the gate and / or the substrate were previously broken down by high voltage due to photolithography rework problems; wherein, during the process of etching a certain thickness of the dielectric layer to obtain a shallow trench isolation structure, a dielectric layer with a certain width remains on the side surface of the gate to form a dielectric sidewall; Obtaining the charge density on the side surface of the dielectric sidewall according to the electric charge amount on the side surface of the dielectric sidewall; Obtaining the minimum width dimension of the dielectric sidewall according to the charge density; Redesigning a mask to redefine the width dimension of the dielectric sidewall according to the minimum width dimension of the dielectric sidewall; Forming a photoresist layer that covers the gate and the dielectric layer; Exposing and developing the photoresist layer using the mask to obtain a patterned photoresist layer, wherein the patterned photoresist layer covers the area where the dielectric sidewall needs to be formed; Using the patterned photoresist layer as a mask to etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure in the substrate and the dielectric sidewall that covers the side surface of the gate.

2. The method for manufacturing a flash memory device that requires photolithography rework according to claim 1, wherein During the process of using the patterned photoresist layer as a mask to etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure and the dielectric sidewall, the width of the obtained dielectric sidewall is greater than or equal to the minimum width dimension of the dielectric sidewall.

3. The method for manufacturing a flash memory device that requires photolithography rework according to claim 1, characterized in that, The calculation formula for the charge density on the side surface of the dielectric sidewall is as follows: σ = Q ÷ S; wherein, σ is the charge density on the side surface of the dielectric sidewall; Q is the electric charge amount on the side surface of the dielectric sidewall; S is the area of the side surface of the dielectric sidewall.

4. The method for manufacturing a flash memory device that requires photolithography rework according to claim 3, characterized in that, The calculation formula for the minimum width dimension of the dielectric sidewall is as follows: where d is the minimum width dimension of the dielectric sidewall; k is a constant; E b is the breakdown field strength; σ is the charge density on the side surface of the dielectric sidewall; ε is the dielectric constant of the dielectric layer.

5. The method for preparing a flash memory device that requires photolithography rework according to claim 1, characterized in that, The dielectric layer is a silicon oxide layer.

6. The method for preparing a flash memory device that requires photolithography rework according to claim 1, characterized in that, During the process of using the patterned photoresist layer as a mask to etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure and the dielectric sidewall, the upper surface of the obtained shallow trench isolation structure is not higher than the upper surface of the gate oxide layer.

7. The method for preparing a flash memory device that requires photolithography rework according to claim 1, wherein After using the patterned photoresist layer as a mask to etch a certain thickness of the dielectric layer to obtain the shallow trench isolation structure and the dielectric sidewall, the method for manufacturing the flash memory device that requires photolithography rework further includes: Removing the dielectric sidewall using a dry etching process; Cleaning the side surface of the gate using a wet cleaning process.

8. The method for manufacturing a flash memory device that requires photolithography rework according to claim 1, characterized in that, Before obtaining the charge density on the side surface of the dielectric sidewall that is in contact with the gate in multiple batches where the gate and / or the substrate were previously broken down by high voltage due to photolithography rework problems, the method for manufacturing the flash memory device that requires photolithography rework further includes: Coating and forming a layer of photoresist on the gate and the dielectric layer; Exposing and developing the photoresist to obtain a patterned photoresist, wherein the patterned photoresist does not expose the entire surface of the dielectric layer and a photolithography process rework is required; Removing the patterned photoresist.

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