A wafer measurement structure and a capacitance measurement method

Abstract

The present invention provides a wafer measurement structure and a capacitance measurement method, which at least include: N pad measurement units arranged at intervals on the upper surface of the wafer, each pad measurement unit measures one corresponding capacitance to be measured, each pad measurement unit includes three pads adjacent to each other in sequence along the horizontal or vertical direction, and the capacitance to be measured is connected between the first pad and the third pad; when the pads are arranged at equal intervals, the parasitic capacitance between adjacent pads cannot be ignored, and one capacitance unit is arranged between adjacent two pads; when the pads are not arranged at equal intervals, the parasitic capacitance between the two pads with the largest spacing can be ignored, and one capacitance unit is arranged between the two pads with the smallest spacing. The capacitance unit is connected to the pad measurement unit through a testing device to measure the capacitance to be measured. By arranging a capacitance unit between adjacent two pads, precise measurement of the capacitance to be measured inside the wafer, which is usually less than picofarad level, is realized. The structure is simple, the operation is convenient, and the applicable range is wide.

Description

Technical Field

[0001] The present invention relates to the fields of semiconductor integrated circuit manufacturing and measurement, and particularly to a wafer measurement structure and a capacitance measurement method. Background Art

[0002] The capacitance in a wafer is of MOM structure (Metal Oxide Metal), or MIM structure (Metal Insulator Metal), or PIP structure (Poly Insulator Poly). Limited by the reduction of chip area, the capacitance density in the wafer is too small, so the capacitance value in the wafer is usually less than the picofarad level. If the tiny capacitance in the wafer cannot be accurately measured, it will have an adverse impact on wafer testing (Wafer Acceptance Test, i.e., WAT), bringing uncertainty to the yield of chips in the wafer, thus affecting the subsequent manufacturing process of the wafer.

[0003] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a wafer measurement structure and a capacitance measurement method, which are used to solve the problem that it is relatively difficult to measure the capacitance less than the picofarad level in the existing wafer in the prior art.

[0005] To achieve the above object and other related objects, the present invention provides a wafer measurement structure for measuring a capacitance to be measured inside a wafer. The wafer measurement structure at least includes:

[0006] N pad measurement units spaced apart and disposed on the upper surface of the wafer. Each pad measurement unit measures one corresponding capacitance to be measured. Each pad measurement unit includes three pads adjacent to each other in sequence along the horizontal or vertical direction. Among them, N is a natural number greater than or equal to 1, and the capacitance to be measured is connected between the first pad and the third pad;

[0007] When the three pads in the Mth pad measurement unit are equally spaced, one capacitance unit is disposed between each adjacent two pads. Among them, each capacitance unit is connected between the corresponding adjacent two pads, where M is a natural number greater than or equal to 1 and less than or equal to N;

[0008] When the three pads in the M - th pad measurement unit are not equally spaced, one capacitor unit is set between the two pads with the minimum spacing, where the capacitor unit is connected between the two pads with the minimum spacing.

[0009] Among them, the test equipment is connected to the pad measurement unit to measure the capacitance of the capacitor to be measured.

[0010] Optionally, the capacitor unit is located on the upper surface of the wafer, or the capacitor unit is located inside the wafer, or the capacitor unit is arranged on the lower surface of the wafer.

[0011] Optionally, the capacitor unit is a single capacitor, or a series of multiple capacitors, or a parallel connection of multiple capacitors, or a combination of series - parallel connections of multiple capacitors.

[0012] Optionally, when the capacitor unit is located on the upper surface or the lower surface of the wafer, the capacitor is a thin - film capacitor or a ceramic capacitor; when the capacitor unit is located inside the wafer, the capacitor is formed inside the wafer by etching.

[0013] Optionally, the shapes and sizes of the pads in each pad measurement unit are equal.

[0014] Optionally, when the pads in each pad measurement unit are arranged horizontally, the tops of the pads are flush; when the pads in each pad measurement unit are arranged vertically, the left ends of the pads are flush.

[0015] To achieve the above - mentioned purpose and other related purposes, the present invention provides a capacitance measurement method for measuring a capacitor to be measured inside a wafer. The capacitance measurement method at least includes:

[0016] Step 11: Connect the test equipment to each pad measurement unit in the wafer measurement structure one by one, and perform capacitance measurement on each pad measurement unit. When the three pads in each pad measurement unit are equally spaced, the test equipment applies a signal to the first pad in the M - th pad measurement unit, and at the same time makes the second pad and the third pad at zero potential to obtain a first measurement value.

[0017] Step 12: The test equipment applies a signal to the third pad, and at the same time makes the first pad and the second pad at zero potential to obtain a second measurement value.

[0018] Step 13: The test equipment applies a signal to the second pad, and at the same time makes the first pad and the third pad at zero potential to obtain a third measurement value.

[0019] Step 14: Based on Steps 11 to 13, obtain the capacitance value of the capacitor C 待测 to be measured, where

[0020] C 待测=(First measurement value + Second measurement value - Third measurement value) / 2.

[0021] To achieve the above and other related purposes, the present invention provides a capacitance measurement method for measuring a capacitance to be measured inside a wafer. The capacitance measurement method at least includes:

[0022] Step 21: Connect the test equipment to each of the pad measurement units in the wafer measurement structure one by one, and perform capacitance measurement on each of the pad measurement units. When the three pads in each of the pad measurement units are not equally spaced, the test equipment applies a signal to the first pad in the Mth pad measurement unit, simultaneously sets the second pad to zero potential, and does not process the third pad, obtaining a fourth measurement value;

[0023] Step 22: The test equipment applies a signal to the first pad, and simultaneously sets the second pad and the third pad to zero potential, obtaining a fifth measurement value;

[0024] Step 23: Based on Steps 21 to 22, obtain the capacitance value of the capacitance C 待测 to be measured, where

[0025] C 待测 = Fifth measurement value - Fourth measurement value.

[0026] As described above, a wafer measurement structure and a capacitance measurement method of the present invention have the following beneficial effects:

[0027] 1) The wafer measurement structure and the capacitance measurement method of the present invention achieve precise measurement of the capacitance to be measured inside the wafer, which is usually less than picofarads, by setting capacitance units between adjacent two pads.

[0028] 2) The wafer measurement structure and the capacitance measurement method of the present invention have a simple structure, are easy to operate, and have a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shows a schematic diagram of the wafer measurement structure of the present invention.

[0030] Figure 2 Shows a first schematic diagram of the pad measurement unit of the present invention.

[0031] Figure 3 Shows an equivalent circuit schematic diagram of the first structure of the pad measurement unit of the present invention.

[0032] Figure 4 Shows a second schematic diagram of the pad measurement unit of the present invention.

[0033] Figure 5 Shows an equivalent circuit schematic diagram of the second structure of the pad measurement unit of the present invention.

[0034] Figure 6 Shown is a schematic diagram of the first functional flow of the capacitance measurement method of the present invention.

[0035] Figure 7 Shown is a schematic diagram of the second functional flow of the capacitance measurement method of the present invention.

[0036] Description of Reference Numerals

[0037] 1 Wafer measurement structure

[0038] 11 Pad measurement unit

[0039] 12 Capacitance unit

[0040] Steps S11 - S14

[0041] Steps S21 - S23 Detailed Embodiment

[0042] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] Please refer to Figures 1 to 7 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0044] Embodiment 1

[0045] As Figures 1 to 5 shown, this embodiment provides a wafer measurement structure 1 for measuring a to - be - measured capacitance inside a wafer. The wafer measurement structure 1 includes:

[0046] As Figure 1 , Figure 2 and Figure 4 shown, N pad measurement units 11 spaced apart from each other are provided on the upper surface of the wafer. Each pad measurement unit 11 measures one corresponding to - be - measured capacitance C 待测 , and each pad measurement unit 11 includes three pads adjacent to each other in sequence along the horizontal or vertical direction, namely a first pad PAD1, a second pad PAD2, and a third pad PAD3. Among them, N is a natural number greater than or equal to 1, and the to - be - measured capacitance C待测 It is connected between the first pad PAD1 and the third pad PAD3.

[0047] Specifically, as an example, such as Figure 2 and Figure 4 shown, the shapes and sizes of the pads in each pad measurement unit 11 are equal. More specifically, when the pads in each pad measurement unit 11 are arranged horizontally, the tops of the pads are flush; when the pads in each pad measurement unit 11 are arranged vertically, the left ends of the pads are flush. It should be noted that the steps for forming pads on the wafer include: forming components or circuits on the substrate of the wafer and completing the wiring process; performing a back thinning process after laminating the wafer and the components on the wafer; sequentially forming a color filter and a microlens on the upper part of the wafer and the components on the wafer; after pasting glass on the upper part of the microlens, exposing the metal layer on the components to the outside; forming pads with the metal layer as the object.

[0048] It should be further noted that between two pads, such as between the first pad PAD1 and the second pad PAD2, and between the second pad PAD2 and the third pad PAD3, there inevitably exists parasitic capacitance. The capacitance value of the parasitic capacitance may be very small, but in the case of ultra-high frequency and super-high frequency, etc., the parasitic capacitance cannot be ignored. The parasitic capacitance theoretically cannot be completely eliminated, and only the harmful part of the parasitic capacitance can be reduced as much as possible or the beneficial part of the parasitic capacitance can be utilized. According to the basic properties of capacitance, capacitance is proportional to the relative cross-sectional area of the two plates and inversely proportional to the distance between the plates. The two pads can be equivalent to the two plates of a capacitor. Therefore, appropriately increasing the distance between the pads in the pad measurement unit 11 can effectively reduce the parasitic capacitance. The capacitance to be measured C 待测 is connected between the first pad PAD1 and the third pad PAD3. As the integrated circuit continues to develop towards microscale, the chip area continues to shrink, and the capacitance density in the wafer decreases accordingly. The capacitance to be measured C 待测 usually has a value less than the picofarad level, and it is very difficult to accurately measure a tiny capacitance less than the picofarad level. At the same time, under the interference of the parasitic capacitance between the pads, the measurement difficulty of the capacitance to be measured C 待测 will be further increased. Since the parasitic capacitance also belongs to a capacitance with a very small value, it is necessary to make structural improvements between the pads to accurately measure the capacitance value of the capacitance to be measured C 待测 of.

[0049] It should be added that each pad measurement unit 11 includes but is not limited to the shapes and sizes of the pads being equal, and the alignment methods of the pads include but are not limited to being flush along the top or flush along the left end. As long as the parasitic capacitance between the pads can be ensured to be small enough, any shape, size, and alignment method of the pads are applicable and are not limited to this embodiment.

[0050] Such as Figure 1 andFigure 2 As shown, when the three pads in the Mth pad measurement unit 11 are arranged at equal intervals, one capacitor unit 12 is arranged between every two adjacent pads. That is, one capacitor unit 12 is arranged between the first pad PAD1 and the second pad PAD2, and one capacitor unit 12 is arranged between the second pad PAD2 and the third pad PAD3. Among them, each capacitor unit 12 is connected between the corresponding two adjacent pads, where M is a natural number greater than or equal to 1 and less than or equal to N.

[0051] As Figure 1 and Figure 4 shown, when the three pads in the Mth pad measurement unit 11 are not arranged at equal intervals, one capacitor unit 12 is arranged between the two pads with the smallest interval. If the interval between the first pad PAD1 and the second pad PAD2 is smaller than the interval between the second pad PAD2 and the third pad PAD3, then one capacitor unit 12 is arranged between the first pad PAD1 and the second pad PAD2. Among them, the capacitor unit 12 is connected between the two pads with the smallest interval. It should be noted that appropriately increasing the interval between the pads in the pad measurement unit 11 can effectively reduce the parasitic capacitance, so that the parasitic capacitance is equivalent to one-third or even smaller of the capacitance C to be measured, making the parasitic capacitance negligible compared with the capacitance C to be measured. The specific interval setting will not be elaborated here one by one. 待测 of the capacitance C to be measured, making the parasitic capacitance negligible compared with the capacitance C to be measured. 待测 The specific interval setting will not be elaborated here one by one.

[0052] Specifically, as an example, as Figure 1 , Figure 2 and Figure 4 shown, the capacitor unit 12 is located on the upper surface of the wafer, or the capacitor unit 12 is located inside the wafer, or the capacitor unit 12 is arranged on the lower surface of the wafer, or capacitor units 12 are arranged on both the upper surface, the lower surface and inside the wafer. The capacitor unit 12 can be a single capacitor, or multiple capacitors in series, or multiple capacitors in parallel, or a combination of series and parallel of multiple capacitors. When the capacitor unit 12 is located on the upper surface or the lower surface of the wafer, the capacitor is a thin-film capacitor or a ceramic capacitor; when the capacitor unit 12 is located inside the wafer, the capacitor is formed inside the wafer by etching.

[0053] It should be noted that the capacitor has the functions of bypass, decoupling, filtering and energy storage, which can ensure that the output signal of the test equipment is stably applied to the pad measurement unit 11 in the wafer measurement structure 1, so that the pad measurement unit 11 will not be damaged due to interference and the capacitance C to be measured will not be affected by interference. 待测Measurement error. When the capacitor is a thin-film capacitor, the high-efficiency self-repair function of the thin-film capacitor can effectively avoid the short-circuit hidden danger generated by the first pad PAD1, the second pad PAD2, and the third pad PAD3; when the capacitor is a ceramic capacitor, the characteristics of high voltage resistance and small size of the ceramic capacitor can effectively play the roles of bypass, decoupling, filtering, and energy storage of the capacitor unit 12, and further protect the wafer; when the capacitor unit 12 is arranged inside the wafer, it can provide an additional layer of protection for the chips inside the wafer.

[0054] It should be further noted that the position, the number of capacitors, and the capacitor connection method of the capacitor unit 12 should be set according to the specific application environment, and are not limited to this embodiment.

[0055] Such as Figure 1 、 Figure 2 and Figure 4 shown, by connecting the test equipment to the pad measurement unit 11, the capacitor C to be measured inside the wafer is measured. For the specific implementation method, please refer to Embodiment 2 and Embodiment 3. 待测 For the specific implementation method, please refer to Embodiment 2 and Embodiment 3.

[0056] Embodiment 2

[0057] Such as Figure 3 、 Figure 6 shown, this embodiment provides a capacitance measurement method for measuring the capacitor C to be measured inside the wafer, and the capacitance measurement method includes: 待测 measuring the capacitor C to be measured inside the wafer, and the capacitance measurement method includes:

[0058] S11: Such as Figure 3 and Figure 6 shown, connect the test equipment to each pad measurement unit 11 in the wafer measurement structure 1 in Embodiment 1 one by one, measure the capacitance of each pad measurement unit 11. When the 3 pads in each pad measurement unit 11 are arranged at equal intervals, the test equipment applies a signal to the first pad PAD1 in the Mth pad measurement unit 11, and at the same time makes the second pad PAD2 and the third pad PAD3 at zero potential to obtain a first measurement value, where the first measurement value = C1 + C 寄生1 + C 待测 , C1 represents the capacitor unit between the first pad PAD1 and the second pad PAD2, C 寄生1 represents the parasitic capacitance between the first pad PAD1 and the second pad PAD2, M is a natural number greater than or equal to 1 and less than or equal to N, and N represents the number of pad measurement units 11.

[0059] S12: Such as Figure 3 and Figure 6As shown, the test device applies a signal to the third pad PAD3, and at the same time sets the first pad PAD1 and the second pad PAD2 to zero potential to obtain a second measurement value, where the second measurement value = C2 + C 寄生2 + C 待测 , C2 represents the capacitance unit between the second pad PAD2 and the third pad PAD3, and C 寄生2 represents the parasitic capacitance between the second pad PAD2 and the third pad PAD3.

[0060] It should be noted that the parasitic capacitance is proportional to the relative cross-sectional area of two adjacent pads and inversely proportional to the distance between the pads. Since the three pads in each pad measurement unit 11 are arranged at equal intervals, limited by the wafer structure space (this is because the size of the wafer is limited. As the degree of wafer integration increases, the size of the chips on the wafer continues to decrease, and the number of chips integrated on the wafer continues to increase), the magnitude of the increase in the distance between the first pad PAD1 and the second pad PAD2 and the distance between the second pad PAD2 and the third pad PAD3 is limited. It is very difficult to make C 寄生1 , C 寄生2 both equivalent to one-third of the capacitance C 待测 to be measured, or even a smaller magnitude than one-third of the capacitance C 待测 to be measured. Therefore, the parasitic capacitance between adjacent pads cannot be ignored, that is, both C 寄生1 and C 寄生2 cannot be ignored.

[0061] S13: As shown in Figure 3 and Figure 6 , the test device applies a signal to the second pad PAD2, and at the same time sets the first pad PAD1 and the third pad PAD3 to zero potential to obtain a third measurement value, where the third measurement value = C1 + C 寄生1 + C2 + C 寄生2 .

[0062] S14: As shown in Figure 3 and Figure 6 , based on steps S11 to S13, the capacitance value of the capacitance C 待测 to be measured is obtained, where C 待测 = (the first measurement value + the second measurement value - the third measurement value) / 2.

[0063] Embodiment 3

[0064] As shown in Figure 5 , Figure 7 , this embodiment provides a capacitance measurement method for measuring the capacitance C 待测 inside a wafer. The capacitance measurement method includes:

[0065] S21: As shown inFigure 5 , Figure 7 As shown, connect the test equipment to each pad measurement unit 11 in the wafer measurement structure 1 one by one, and perform capacitance measurement on each pad measurement unit 11. When the 3 pads in each pad measurement unit 11 are not equally spaced, the test equipment applies a signal to the first pad PAD1 in the Mth pad measurement unit, and at the same time makes the second pad PAD2 connected to zero potential, and the third pad PAD3 is not processed, that is, the third pad PAD3 is left floating, and a fourth measurement value is obtained. Among them, the fourth measurement value = C1 + C 寄生1 , where M is a natural number greater than or equal to 1 and less than or equal to N, N represents the number of pad measurement units 11, C1 represents the capacitance unit between the first pad PAD1 and the second pad PAD2, and C 寄生1 represents the parasitic capacitance between the first pad PAD1 and the second pad PAD2.

[0066] S22: As Figure 5 , Figure 7 shown, the test equipment applies a signal to the first pad PAD1, and at the same time makes the second pad PAD2 and the third pad PAD3 connected to zero potential, and a fifth measurement value is obtained. Among them, the fifth measurement value = C1 + C 寄生1 + C 待测 . It should be noted that the parasitic capacitance is proportional to the relative cross-sectional area of two adjacent pads and inversely proportional to the distance between the pads. Appropriately increasing the distance between the pads in the pad measurement unit 11 can effectively reduce the parasitic capacitance, so that the parasitic capacitance is equivalent to one-third of the capacitance C 待测 to be measured or even smaller than one-third of the capacitance C 待测 to be measured. Furthermore, the parasitic capacitance can be ignored compared with the capacitance C 待测 to be measured. In this embodiment, increasing the distance between the second pad PAD2 and the third pad PAD3 is equivalent to reducing the distance between the first pad PAD1 and the second pad PAD2, making C 寄生1 greater than one-third of the capacitance C 待测 to be measured, that is, C 寄生1 cannot be ignored; making the parasitic capacitance between the second pad PAD2 and the third pad PAD3 less than or equal to one-third of the capacitance C 待测 to be measured, that is, the parasitic capacitance between the second pad PAD2 and the third pad PAD3 can be ignored. The specific settings of the first pad PAD1, the second pad PAD2, and the third pad PAD3 will not be elaborated here one by one.

[0067] S23: As Figure 5 , Figure 7 shown, based on steps S21 to S22, obtain the capacitance value of the capacitance C 待测 to be measured. Among them, C 待测= The fifth measurement value - the fourth measurement value.

[0068] In summary, based on Embodiment 2 or Embodiment 3, the precise capacitance value of the capacitance C to be measured is obtained. 待测 of the capacitance C to be measured.

[0069] In summary, a wafer measurement structure and a capacitance measurement method of the present invention at least include: N pad measurement units arranged on the upper surface of the wafer, each of the pad measurement units measures one corresponding capacitance C to be measured, and each of the pad measurement units includes three pads adjacent to each other in sequence along the horizontal direction or the vertical direction, where N is a natural number greater than or equal to 1, and the capacitance C to be measured is connected between the first pad and the third pad; when the three pads in the Mth pad measurement unit are arranged at equal intervals, one capacitance unit is arranged between each adjacent two pads, where each capacitance unit is connected between the corresponding adjacent two pads, where M is a natural number greater than or equal to 1 and less than or equal to N; when the three pads in the Mth pad measurement unit are not arranged at equal intervals, one capacitance unit is arranged between the two pads with the smallest interval, where the capacitance unit is connected between the two pads with the smallest interval; where the test equipment is connected to the pad measurement unit to measure the capacitance C to be measured. The wafer measurement structure and the capacitance measurement method of the present invention realize the precise measurement of the capacitance C to be measured inside the wafer, which is usually less than picofarad, by arranging capacitance units between adjacent two pads. The wafer measurement structure and the capacitance measurement method of the present invention have a simple structure, are easy to operate, and have a wide application range. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0070] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer measurement structure for measuring a capacitance to be measured inside a wafer, characterized in that, The wafer measurement structure at least includes: N pad measurement units that are spaced apart and arranged on the upper surface of the wafer. Each of the pad measurement units measures a corresponding one of the capacitors to be measured. Each of the pad measurement units includes three pads that are adjacent to each other in sequence along the horizontal direction or the vertical direction. Here, N is a natural number greater than or equal to 1, and the capacitor to be measured is connected between the first pad and the third pad. When the three pads in the M-th pad measurement unit are arranged at equal intervals, one capacitor unit is provided between every two adjacent pads. Here, each capacitor unit is connected between the corresponding two adjacent pads. Here, M is a natural number greater than or equal to 1 and less than or equal to N. When the three pads in the M-th pad measurement unit are not arranged at equal intervals, one capacitor unit is provided between the two pads with the smallest spacing. Here, the capacitor unit is connected between the two pads with the smallest spacing. Among them, the test equipment is connected to the pad measurement unit to measure the capacitor to be measured.

2. The wafer measurement structure according to claim 1, wherein: The capacitor unit is located on the upper surface of the wafer, or the capacitor unit is located inside the wafer, or the capacitor unit is provided on the lower surface of the wafer.

3. The wafer measurement structure according to claim 2, wherein: The capacitor unit is a single capacitor, or a series connection of multiple capacitors, or a parallel connection of multiple capacitors, or a combination of series and parallel connections of multiple capacitors.

4. The wafer measurement structure according to claim 3, wherein: When the capacitor unit is located on the upper surface or the lower surface of the wafer, the capacitor is a thin-film capacitor or a ceramic capacitor; when the capacitor unit is located inside the wafer, the capacitor is formed inside the wafer by etching.

5. The wafer measurement structure according to claim 1, wherein: The shapes and sizes of the pads in each of the pad measurement units are equal.

6. The wafer measurement structure according to claim 5, wherein: When the pads in each of the pad measurement units are arranged horizontally, the tops of the pads are flush; when the pads in each of the pad measurement units are arranged vertically, the left ends of the pads are flush.

7. A capacitance measurement method for measuring a capacitor to be measured inside a wafer. The capacitance measurement method at least includes: Step 11: Connect the test equipment to each of the pad measurement units in the wafer measurement structure according to any one of claims 1-6 one by one, and measure the capacitors to be measured corresponding to each of the pad measurement units. When the three pads in each of the pad measurement units are arranged at equal intervals, the test equipment applies a signal to the first pad in the M-th pad measurement unit, and at the same time makes the second pad and the third pad at zero potential to obtain a first measurement value. Step 12: The test equipment applies a signal to the third pad, and at the same time makes the first pad and the second pad at zero potential to obtain a second measurement value. Step 13: The test equipment applies a signal to the second pad, and at the same time makes the first pad and the third pad at zero potential to obtain a third measurement value. Step 14: Based on Steps 11 to 13, obtain the capacitance value of the capacitor C to be measured, where, 待测 ​ C 待测 = (First measurement value + Second measurement value - Third measurement value) / 2.

8. A capacitance measurement method for measuring a capacitor to be measured inside a wafer. The capacitance measurement method at least includes: Step 21: Connect the test equipment to each of the pad measurement units in the wafer measurement structure according to any one of claims 1-6 one by one, and perform capacitance measurement on each of the pad measurement units. When the three pads in each of the pad measurement units are not arranged at equal intervals, the test equipment applies a signal to the first pad in the M-th pad measurement unit, and at the same time makes the second pad at zero potential, and the third pad is not processed to obtain a fourth measurement value. Step 22: The test device applies a signal to the first pad, and at the same time, the second pad and the third pad are connected to zero potential to obtain a fifth measurement value; Step 23: Based on Steps 21 to 22, obtain the capacitance value of the capacitance C to be measured, where, 待测 ​ C 待测 = The fifth measurement value - the fourth measurement value.

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