A method, apparatus, and medium for processing system event logs.

Abstract

This invention discloses a system event log processing method, apparatus, and medium, applicable to the field of electronic technology. Through two readings, the first reading reads the register latch data corresponding to the CPLD abnormal power-down interrupt signal to identify the abnormal management chip, records the event to the SEL log, and simultaneously records detailed event information to the diagnostic log to enable maintenance personnel to more accurately troubleshoot and locate the source. Since hardware states can change within a certain time period, to prevent this, a second reading reads the current register latch data to record the current signal state of each corresponding trigger source and saves it to the log. This real-time reading accurately locates the trigger source and records detailed status information of each power management chip.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a method, apparatus and medium for processing system event logs. Background Technology

[0002] With the rapid development of information technology and the implementation of cloud computing and the Internet of Things, users have higher requirements for the reliability and information processing capabilities of servers. At the same time, the need for server management and monitoring is also receiving increasing attention.

[0003] When an abnormal power failure occurs on the motherboard, the Baseboard Management Controller (BMC) monitoring mechanism needs to detect and record the corresponding event log (SEL). However, the SEL log only records the current status of handling the abnormal power failure event and cannot pinpoint the trigger source or the reason for the abnormal power failure, which makes the troubleshooting process more complicated for staff.

[0004] Therefore, finding a method for processing system event logs is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a system event log processing method, device, and medium. When an event occurs, the latched data and real-time data of the power status register in the CPLD are read twice and analyzed by table lookup to accurately locate the trigger source and record the status information of each power management chip in detail.

[0006] To address the aforementioned technical problems, this invention provides a method for processing system event logs, comprising:

[0007] Read the register latch data corresponding to the CPLD abnormal power failure interrupt signal. The register latch data includes the power failure occurrence stage parameters and the signal status values ​​of each trigger source under the occurrence stage parameters.

[0008] The corresponding abnormal power management chip is identified by comparing the data latched in the register with the power status health table of the power management chip.

[0009] Record the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and record the occurrence stage parameters and relevant information in the power status health table corresponding to the abnormal power management chip to the diagnostic log.

[0010] Before the interrupt signal is restored, read the current register latch data to record the current signal status of each corresponding trigger source and save it to the shared log.

[0011] Preferably, before reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal, the method further includes:

[0012] When the CPLD detects abnormalities in the enable signal and PG signal of the power management chip, it determines that the voltage and current of the motherboard are abnormal.

[0013] Latch the status registers related to the abnormal power supply and trigger the abnormal power failure interrupt signal.

[0014] Preferably, reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal includes:

[0015] According to the preset time, the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD is read via the I2C protocol.

[0016] Preferably, the power status health table stores at least the physical location name of each trigger source, the number of bytes corresponding to the register data, the number of bits, and the valid data value.

[0017] Preferably, the abnormal power management chip is determined by comparing the data latched in the register with the power management chip in the power status health table, including:

[0018] Compare each trigger source corresponding to the register latch data with each preset trigger source in the power status health table;

[0019] When the state value of the trigger source is inconsistent with the state value of the preset trigger source, it is determined that there is an abnormality in the power management chip corresponding to the trigger source.

[0020] Preferably, after determining that the power management chip is malfunctioning, the method further includes:

[0021] Pull the alarm status flag of the trigger source corresponding to the power management chip high to trigger the alarm mechanism.

[0022] Preferably, after reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal, the method further includes:

[0023] Clear the CPLD register data.

[0024] Preferably, after the interrupt signal is restored, the method further includes:

[0025] Remove the alarm status flag of the triggered source from the high position and record it in the SEL log.

[0026] To address the aforementioned technical problems, the present invention also provides a system event log processing apparatus, comprising:

[0027] The first reading module is used to read the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD. The register latch data includes the power failure occurrence stage parameters and the signal status values ​​of each trigger source under the occurrence stage parameters.

[0028] The determination module is used to identify the corresponding abnormal power management chip by comparing the data latched in the register with the power status health table of the power management chip.

[0029] The recording module is used to record the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and to record the occurrence stage parameters and relevant information in the power status health table corresponding to the abnormal power management chip to the diagnostic log.

[0030] The second reading module is used to read the current register latch data before the interrupt signal is restored, to record the current signal status of each corresponding trigger source and save it to the shared log.

[0031] To address the aforementioned technical problems, the present invention also provides a system event log processing apparatus, comprising:

[0032] Memory, used to store computer programs;

[0033] A processor is used to implement the steps of the system event log processing method described above when executing a computer program.

[0034] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the system event log processing method described above.

[0035] This invention provides a system event log processing method, comprising: reading register latch data corresponding to a CPLD abnormal power failure interrupt signal, wherein the register latch data includes power failure occurrence stage parameters and signal status values ​​of each trigger source under the occurrence stage parameters; determining the corresponding abnormal power management chip by comparing the register latch data with the power management chip in the power status health table; recording the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and recording the occurrence stage parameters corresponding to the abnormal power management chip and relevant information in the power status health table to the diagnostic log; before the interrupt signal is restored, reading the current register latch data to record the current signal status of each corresponding trigger source and saving it to the shared log. This method uses two reads: the first read determines the abnormal management chip, records the event to the SEL log, and simultaneously records detailed event information to the diagnostic log so that maintenance personnel can more accurately troubleshoot and locate the source. Since hardware states can change within a certain time period, to avoid this phenomenon, the second read is performed in real time to accurately locate the trigger source and record the status information of each power management chip in detail.

[0036] In addition, the present invention also provides a system event log processing apparatus and medium, which have the same beneficial effects as the system event log processing method described above. Attached Figure Description

[0037] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating a system event log processing method provided in an embodiment of the present invention;

[0039] Figure 2 A structural diagram of a system event log processing device provided in an embodiment of the present invention;

[0040] Figure 3 A structural diagram of another system event log processing device provided in an embodiment of the present invention;

[0041] Figure 4 A flowchart of another system event log processing method provided in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0043] The core of this invention is to provide a system event log processing method, device, and medium. When an event occurs, the latched data and real-time data of the power status register in the CPLD are read twice and analyzed by table lookup to accurately locate the trigger source and record the status information of each power management chip in detail.

[0044] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] It should be noted that the system time log processing method provided by this invention can be applied to server architectures on Intel platforms, but is not limited to this architecture. It can also be applied to server and computer platforms on other platforms, and has a certain degree of universality.

[0046] Figure 1 A flowchart illustrating a system event log processing method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method includes:

[0047] S11: Read the register latched data corresponding to the CPLD abnormal power failure interrupt signal;

[0048] The register latch data includes the power failure occurrence stage parameters and the signal status values ​​of each trigger source under the occurrence stage parameters;

[0049] S12: Determine the corresponding abnormal power management chip by comparing the data latched in the register with the power management chip in the power status health table.

[0050] S13: Record the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and record the occurrence stage parameters and relevant information in the power status health table corresponding to the abnormal power management chip to the diagnostic log.

[0051] S14: Before the interrupt signal is restored, read the current register latch data to record the current signal status of each corresponding trigger source and save it to the shared log.

[0052] Specifically, Complex Programmable Logic Devices (CPLDs) consist of fully programmable AND / OR arrays and macrocell libraries. The AND / OR arrays are reprogrammable and capable of performing numerous logic functions. Macrocells are functional blocks that perform combinational or sequential logic, while also providing greater flexibility such as truth or two's complement output and feedback via different paths. CPLDs, or Complex Programmable Logic Devices, evolved from PAL and GAL devices. They are relatively large in scale and complex in structure, falling under the category of large-scale integrated circuits. They are digital integrated circuits where users construct logic functions according to their own needs. The basic design method involves using an integrated development software platform, employing schematics, hardware description languages, and other methods to generate corresponding target files. The code is then transferred to the target chip via a download cable ("in-system" programming) to realize the designed digital system. CPLDs utilize programming technologies such as CMOS EPROM, EEPROM, flash memory, and SRAM, thus forming high-density, high-speed, and low-power programmable logic devices.

[0053] Before reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal in step S11, the following steps are also included:

[0054] When the CPLD detects abnormalities in the enable signal and PG signal of the power management chip, it determines that the voltage and current of the motherboard are abnormal.

[0055] Latch the status registers related to the abnormal power supply and trigger the abnormal power failure interrupt signal.

[0056] Specifically, the Power Good signal, abbreviated as PG or P.OK signal, is a logic signal that detects both DC output voltage and AC input voltage, and is compatible with TTL signals. When the power is turned on, if the AC input voltage is within the rated operating range, and each DC output voltage has reached its minimum detection level (above 4.75V for +5V output), then after a delay of 100ms to 500ms, the PG circuit sends a "Power Good" signal (P.OK is high). When the AC input voltage drops below the safe operating range or the +5V voltage drops below 4.75V, the power supply sends a "Power Fail" signal. The Power Fail signal should drop to a low level of less than 0.3V for at least 1ms before the 5V drops to 4.75V, and the falling edge waveform should be steep without any self-oscillation.

[0057] The PG signal is crucial; even if all DC outputs of the power supply are normal, the motherboard will not function without the PG signal. Incorrect PG signal timing may prevent the system from booting. The power-on sequence of the power supply is generally determined by the PG signal of the power management chip in conjunction with its enable signal. After the power supply stage is enabled, its output status can be obtained through the PWRGD signal. Once the output status is confirmed to be stable, the next power rail that needs to be powered on is then activated. By using the single-mode function of an oscilloscope to capture the rising edge of the power chip output at the moment of power-on, it can be determined whether the actual sequence matches the design sequence.

[0058] When the CPLD detects anomalies in the enable and PG signals, indicating abnormal voltage and current on its server motherboard, the CPLD immediately latches the relevant status registers of the abnormal power supply—essentially, to save data. Latches are used to store data for exchange, stabilizing it for a period until new data replaces it. Registers and latches are both devices used to temporarily store data and are essentially the same. However, the output of a register normally does not change with the input; it only sends the input data to the output (pinches it into the register) when the clock is valid. In contrast, the output of a latch normally changes with the input; it only latches the output state when the latch signal arrives, preventing it from changing with the input.

[0059] After triggering the abnormal power failure interrupt signal, the register latched data corresponding to the CPLD abnormal power failure interrupt signal is read. Specific implementation examples include:

[0060] According to the preset time, the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD is read via the I2C protocol.

[0061] Understandably, after the BMC detects an abnormal power-down interruption signal from the CPLD during continuous polling, it will immediately read the "voltage status register latched data" in the CPLD via the synchronous half-duplex bus (Inter-Integrated Circuit, I2C). These registers store two pieces of information: first, the "power anomaly occurrence stage" (power-on, power-off, power-on process, power-off process); and second, the signal status of all trigger sources that may have triggered the abnormal power-down. In other words, the register latched data includes the parameters of the power anomaly occurrence stage and the signal status values ​​of each trigger source under those parameters. For example, it reads the signal status values ​​of all trigger sources during the power-on stage.

[0062] I2C Synchronization: The transmitting and receiving ends must be strictly synchronized, typically using a synchronization clock line. Half-duplex: I2C uses only one data line, so the master cannot send and receive data simultaneously. The design philosophy of I2C is to minimize signal lines while maximizing data speed. Fewer signal lines reduce pin usage, which was crucial for early chips with few pins. Simply reducing signal lines is important; a 1-wire bus uses only one wire for communication (e.g., DS18B20, DHT11 use this protocol). However, 1-wire bus communication is asynchronous, so its speed cannot be too high (typically 16.3 Kbit / s, with a maximum of 142 Kbit / s, but usually below 100 Kbit / s).

[0063] Standard I2C requires two signal lines: SCL (Serial Clock): the clock line, which is provided by the master; and SDA (Serial Data): a bidirectional data line, used for sending or receiving data (sending and receiving cannot be simultaneous). Other bus protocols can also be used to retrieve the data currently stored in the registers; this is not limited here and can be configured according to the actual situation.

[0064] In step S12, the corresponding abnormal power management chip is determined by comparing the register latched data with the power management chip in the power status health table. The status of each trigger source in the acquired register latched data is compared with the status of the trigger source in the power status health table. The power status health table stores at least the physical location name of each trigger source, the number of bytes corresponding to the register data, the number of bits, and the detailed information of the valid data value.

[0065] As one example of comparison, it specifically includes:

[0066] Compare each trigger source corresponding to the register latch data with each preset trigger source in the power status health table;

[0067] When the state value of the trigger source is inconsistent with the state value of the preset trigger source, it is determined that there is an abnormality in the power management chip corresponding to the trigger source.

[0068] When an abnormal power failure event is triggered, the BMC reads the "Voltage Status Register Latch Data" and compares each power management chip (VR) in the "Power Status Health Table" one by one. When the actual status value of a certain VR is inconsistent with the correct value in the table, it means that the VR corresponding to the trigger source is abnormal. Therefore, the abnormal power failure of the motherboard may be triggered by the abnormal VR. By analogy, all abnormal VRs can be found by looking up the table.

[0069] After locating the faulty power management chip, the abnormal power outage time is recorded in the System Event Log (SEL). Currently, the server system's Baseboard Management Controller (BMC), Hot-Swap Controller (HSC), and BIOS can all generate events, which are recorded in the SEL. The SEL browser allows users or technicians to access the SEL user interface through the Emergency Management Port (EMP) and System Setup Tool (SSU). This browser extracts information from the SEL and displays it in hexadecimal or detailed format. SEL information can be used to monitor the server and detect warnings or potential major problems. However, the SEL only records that an abnormal power outage event was triggered; it does not provide detailed and precise reasons for the event, making it impossible to pinpoint the trigger source.

[0070] Therefore, the parameters corresponding to the abnormal power management chip's occurrence stage and relevant information from the power status health table are recorded in the diagnostic log to facilitate the operation and maintenance personnel's localization and analysis. At this time, the abnormal power outage event, as well as the detailed power outage stage and physical location, will be clearly and accurately recorded.

[0071] Furthermore, since the current state values ​​of the hardware may change over a period of time—for example, two or three VRs might become abnormal during an abnormal power-down event—the number of abnormal VR states might be greater at the moment of power failure or after a longer period than during the abnormal power-down event. Therefore, a second read is performed based on the first read in step S11. Before the interrupt signal is restored, the current register latch data is read to record the current signal state of each corresponding trigger source and saved to the log to ensure the acquisition of real-time state values ​​for all power management chips. The protocol bus used in the read process can be the same as or different from that used in the first read.

[0072] As a preferred embodiment, the "real-time data of voltage status register" of the CPLD is read a second time via the I2C protocol and saved to shared memory and recorded in the log. This is because the data at this time represents the real-time status values ​​of all VRs, which can provide important basis for maintenance personnel to analyze problems.

[0073] This invention provides a system event log processing method, comprising: reading register latch data corresponding to a CPLD abnormal power failure interrupt signal, wherein the register latch data includes power failure occurrence stage parameters and signal status values ​​of each trigger source under the occurrence stage parameters; determining the corresponding abnormal power management chip by comparing the register latch data with the power management chip in the power status health table; recording the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and recording the occurrence stage parameters corresponding to the abnormal power management chip and relevant information in the power status health table to the diagnostic log; before the interrupt signal is restored, reading the current register latch data to record the current signal status of each corresponding trigger source and saving it to the shared log. This method uses two reads: the first read determines the abnormal management chip, records the event to the SEL log, and simultaneously records detailed event information to the diagnostic log so that maintenance personnel can more accurately troubleshoot and locate the source. Since hardware states can change within a certain time period, to avoid this phenomenon, the second read is performed in real time to accurately locate the trigger source and record the status information of each power management chip in detail.

[0074] Based on the above embodiments, after determining that the power management chip is malfunctioning in step S12, the method further includes:

[0075] Pull the alarm status flag of the trigger source corresponding to the power management chip high to trigger the alarm mechanism.

[0076] Specifically, its alarm status flag is raised to indicate different abnormal states. Simultaneously, an alarm mechanism is triggered to alert maintenance personnel that the current power management chip is malfunctioning and requires repair.

[0077] Correspondingly, the alarm information output by the alarm mechanism is not limited in its output method. It can be sent via email or SMS, or it can be activated by flashing lights or a buzzer. There are no specific limitations.

[0078] The present invention provides that, after determining that the power management chip is abnormal, the alarm status flag bit of the trigger source corresponding to the power management chip is pulled high to trigger the alarm mechanism, so as to remind the operation and maintenance personnel that the current power management chip is abnormal so as to troubleshoot and repair.

[0079] Based on the above embodiments, after reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal in step S11, the method further includes:

[0080] Clear the CPLD register data.

[0081] To facilitate real-time data retrieval, after the first acquisition of register latched data, the register value is cleared to allow for memory cleanup for subsequent data retrievals. Only the second acquired data is retained in the log information to improve the efficiency of maintenance personnel in analyzing problems.

[0082] Based on the above embodiments, after the interrupt signal is restored, the following is also included:

[0083] Remove the alarm status flag of the triggered source from the high position and record it in the SEL log.

[0084] This indicates that the abnormal power failure issue has disappeared. The BMC detects all VR "alarm status flags". When it detects a VR with a high "alarm status flag", the BMC clears the abnormal power failure alarm for the VR and records SEL, restoring the flag to low to improve the real-time update of log information.

[0085] The foregoing has described in detail various embodiments of the system event log processing method. Based on this, the present invention also discloses a system event log processing apparatus corresponding to the above method. Figure 2 This is a structural diagram of a system event log processing device provided in an embodiment of the present invention. Figure 2 As shown, the system event log processing device includes:

[0086] The first reading module 11 is used to read the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD. The register latch data includes the power failure occurrence stage parameters and the signal status values ​​of each trigger source under the occurrence stage parameters.

[0087] The determination module 12 is used to determine the corresponding abnormal power management chip by comparing the data latched in the register with the power management chip in the power status health table.

[0088] Recording module 13 is used to record the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and to record the occurrence stage parameters and relevant information in the power status health table corresponding to the abnormal power management chip to the diagnostic log.

[0089] The second reading module 14 is used to read the current register latch data before the interrupt signal is restored in order to record the current signal status of each corresponding trigger source and save it to the shared log.

[0090] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0091] For a description of the system event log processing device provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above system event log processing method.

[0092] Figure 3 A structural diagram of another system event log processing device provided in an embodiment of the present invention is shown below. Figure 3 As shown, the device includes:

[0093] Memory 21 is used to store computer programs;

[0094] Processor 22 is configured to implement the steps of a system event log processing method when executing a computer program.

[0095] The system event log processing device provided in this embodiment may include, but is not limited to, tablet computers, laptop computers, or desktop computers.

[0096] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 22 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 22 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0097] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 21 is used to store at least the following computer program 211, which, after being loaded and executed by the processor 22, is capable of implementing the relevant steps of the system event log processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. The operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, the data involved in the system event log processing method, etc.

[0098] In some embodiments, the system event log processing device may further include a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.

[0099] Those skilled in the field can understand, Figure 3 The structure shown does not constitute a limitation on the system event log processing apparatus and may include more or fewer components than illustrated.

[0100] The processor 22 implements the system event log processing method provided in any of the above embodiments by calling instructions stored in the memory 21.

[0101] For a description of the system event log processing device provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above system event log processing method.

[0102] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by processor 22, implements the steps of the system event log processing method described above.

[0103] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above system event log processing method.

[0105] As a preferred embodiment, Figure 4 A flowchart of another system event log processing method provided in an embodiment of the present invention is shown below. Figure 4 As shown, it includes:

[0106] S21: After an abnormal power failure is detected, the CPLD latches the power register and triggers an interrupt signal;

[0107] S22: Determine if there is an interruption during BMC polling. If yes, proceed to step S23; otherwise, proceed to step S26.

[0108] S23: The BMC reads the CPLD latch register value and the current stage of the exception for the first time;

[0109] S24: The BMC will look up and analyze the latched data, filter out all abnormal VRs, raise the corresponding flag bit, trigger an alarm, and record detailed information in the log.

[0110] S25: Read the real-time register of the CPLD power status value for the second time and record the VR real-time status value to the log;

[0111] S26: When the interrupt signal is restored, check whether there is a VR that has triggered an alarm based on the VR flag bit. If there is a VR with the flag bit pulled high, remove the alarm for it and restore the flag bit to low.

[0112] For an introduction to another system event log processing method provided by the present invention, please refer to the above method embodiments. The present invention will not be described again here, but it has the same beneficial effects as the above system event log processing method.

[0113] The foregoing has provided a detailed description of a system event log processing method, apparatus, and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0114] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for processing system event logs, characterized in that, include: Read the register latch data corresponding to the CPLD abnormal power failure interrupt signal, wherein the register latch data includes the power failure occurrence stage parameters and the signal status values ​​of each trigger source under the occurrence stage parameters; The corresponding abnormal power management chip is determined by comparing the data latched in the register with the power management chip in the power status health table. The abnormal power failure event corresponding to the abnormal power management chip is recorded in the SEL log, and the occurrence stage parameters corresponding to the abnormal power management chip and the relevant information in the power status health table are recorded in the diagnostic log. Before the interrupt signal is restored, the current register latch data is read to record the current signal status of each corresponding trigger source and saved to the shared log; Correspondingly, before reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal, the method further includes: When the CPLD detects an abnormality in the enable signal and PG signal of the power management chip, it determines that the voltage and current of the motherboard are abnormal. The status register related to the abnormal power supply is latched, and the abnormal power failure interrupt signal is triggered; wherein, when the latch signal arrives, the status of the output terminal is latched and does not change with the change of the input terminal; Correspondingly, reading the register latched data corresponding to the CPLD abnormal power-down interrupt signal includes: According to a preset time, the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD is read via the I2C protocol.

2. The system event log processing method according to claim 1, characterized in that, The power status health table stores at least the physical location name of each trigger source, the number of bytes and bits corresponding to the register data, and the valid data value.

3. The system event log processing method according to claim 1, characterized in that, The step of determining the corresponding abnormal power management chip by comparing the data latched in the register with the power status health table includes: Compare each trigger source corresponding to the register latched data with each preset trigger source of the power status health table; When the state value of the trigger source is inconsistent with the state value of the preset trigger source, it is determined that the power management chip corresponding to the trigger source is abnormal.

4. The system event log processing method according to claim 3, characterized in that, After determining that the power management chip is malfunctioning, the following steps are also included: The alarm status flag of the trigger source corresponding to the power management chip is pulled high to trigger the alarm mechanism.

5. The method for processing system event logs according to any one of claims 1 to 4, characterized in that, After reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal, the method further includes: Clear the register data of the CPLD.

6. The method for processing system event logs according to claim 4, characterized in that, After the interrupt signal is restored, the following is also included: Release the alarm status flag of the trigger source that has been raised, and record it in the SEL log.

7. A system event log processing device, characterized in that, include: The first reading module is used to read the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD, wherein the register latch data includes the occurrence stage parameters of the power failure and the signal status values ​​of each trigger source under the occurrence stage parameters; The determination module is used to determine the corresponding abnormal power management chip by comparing the data latched in the register with the power management chip in the power status health table. The recording module is used to record the abnormal power failure event corresponding to the abnormal power management chip to the SEL log, and to record the occurrence stage parameters corresponding to the abnormal power management chip and the relevant information in the power status health table to the diagnostic log. The second reading module is used to read the current register latch data before the interrupt signal is restored in order to record the current signal status of each of the corresponding trigger sources and save it to the shared log. Correspondingly, before reading the register latched data corresponding to the CPLD abnormal power failure interrupt signal, the method further includes: When the CPLD detects an abnormality in the enable signal and PG signal of the power management chip, it determines that the voltage and current of the motherboard are abnormal. The status register related to the abnormal power supply is latched, and the abnormal power failure interrupt signal is triggered; wherein, when the latch signal arrives, the status of the output terminal is latched and does not change with the change of the input terminal; Correspondingly, reading the register latched data corresponding to the CPLD abnormal power-down interrupt signal includes: According to a preset time, the register latch data corresponding to the abnormal power failure interrupt signal of the CPLD is read via the I2C protocol.

8. A system event log processing device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the system event log processing method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the system event log processing method as described in any one of claims 1 to 6.

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