Analog switch circuit with latch function

Abstract

This invention discloses an analog switch circuit with latching function. The analog switch circuit includes an input shaping circuit, a latching logic control circuit, a level conversion circuit, an output shaping circuit, and a switching circuit. The input shaping circuit shapes the received voltage signal and sends the shaped voltage signal to the latching logic control circuit. The latching logic control circuit performs different logic controls on the received voltage signal to generate different first control signals. The level conversion circuit converts the voltage range of the first control signal to a preset voltage range to generate a second control signal. The input terminal of the output shaping circuit is connected to the output terminal of the level conversion circuit, and its output terminal is connected to the switching circuit to generate a switch control signal to control the switching circuit. This invention extends the function of the switching circuit by giving it a latching function, thereby improving the reliability of the analog switch circuit.

Description

Technical Field

[0001] This invention belongs to the field of analog switch technology, and specifically relates to an analog switch circuit with latching function. Background Technology

[0002] CMOS analog switching circuits are widely used in signal transmission and acquisition systems due to their low on-resistance and fast transmission time. A CMOS analog switching circuit mainly consists of a control circuit and a transmission circuit; see details below. Figure 1 The control circuit consists of a PMOS transistor P0 and an NMOS transistor N0, which generate control signals to control the conduction and cutoff of the transmission circuit, thereby completing the signal transmission. With the development of microsystem integration, analog switches in the system are required to have data latching functions. Generally, analog switches can only transmit real-time data and do not have signal latching functions. Therefore, there is an urgent need to design an analog switch circuit with latching function. Summary of the Invention

[0003] To address the aforementioned problems, this invention proposes an analog switch circuit with latching function, extending the functionality of the switch circuit to include latching capabilities, thereby improving the reliability of the analog switch circuit.

[0004] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution:

[0005] An analog switching circuit with latching function includes an input shaping circuit, a latching logic control circuit, a level conversion circuit, an output shaping circuit, and a switching circuit.

[0006] The input shaping circuit shapes the received voltage signal and sends the shaped voltage signal to the latch logic control circuit.

[0007] The latch logic control circuit performs different logic controls on the received voltage signal to generate different first control signals;

[0008] The level conversion circuit converts the voltage range of the first control signal to a preset voltage range to generate the second control signal;

[0009] The input terminal of the output shaping circuit is connected to the output terminal of the level conversion circuit, and its output terminal is connected to the switching circuit to generate a switching control signal to control the switching circuit.

[0010] Optionally, the input shaping circuit includes a first input port, a second input port, a third input port, and a fourth input port, which are used to receive the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR, respectively; the input shaping circuit includes a first output port, a second output port, a third output port, and a fourth output port, which are used to output the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR, respectively.

[0011] Optionally, the latch logic control circuit includes a first flip-flop, a second flip-flop, a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate;

[0012] The D interface of the first flip-flop is connected to the first output terminal of the input shaping circuit for receiving the control signal IN, and its CLK interface is connected to the third output terminal of the input shaping circuit for receiving the read / write signal WR.

[0013] The D interface of the second flip-flop is connected to the second output terminal of the input shaping circuit to receive the enable signal EN, its CLK interface is connected to the fourth output terminal of the input shaping circuit to receive the read / write signal WR, and its CLR interface is connected to the third output terminal of the input shaping circuit to receive the reset signal RS.

[0014] The output terminal Q of the first flip-flop is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to one of the input terminals of the first NAND gate.

[0015] The inverted output terminal Q_ of the first flip-flop is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to one of the input terminals of the second NAND gate;

[0016] The output terminal Q of the second flip-flop is connected to the other input terminal of the first NAND gate and the second NAND gate respectively, and outputs the ENC signal to the first NAND gate and the second NAND gate;

[0017] The output of the first NAND gate is connected to the input of the third inverter, and the output of the third inverter is used to output the INC signal.

[0018] The output of the second NAND gate is connected to the input of the fourth inverter. The output of the fourth inverter is used to output the INB signal, which is complementary to the INC signal.

[0019] Optionally, when the reset signal RS is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0, and the INC signal and the INB signal constitute the first control signal, which is used to control the switching circuit to be in the cleared state.

[0020] When the reset signal RS is logic 1 and the read / write signal WR is logic 1, the ENC signal, INC signal, and INB signal are in a holding state. The INC signal and INB signal constitute the first control signal, which is used to control the switching circuit to be in a holding latch state.

[0021] When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 1, the signal ENC is logic 1, and the logic signal IN is used as the first control signal to control the state of the switching circuit.

[0022] When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 0, the ENC signal is logic 0, and the INC and INB signals are both logic 0. The INC and INB signals constitute the first control signal, which is used to control the switching circuit to be in the off state.

[0023] Optionally, the preset range is a positive and negative power supply voltage range.

[0024] Optionally, the shaped voltage signal needs to meet the TTL level requirements.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention designs a latching logic control circuit in an analog switching circuit that can perform different logic controls on the received voltage signal, thereby extending the function of the switching circuit to include latching and other functions, and improving the reliability of the analog switching circuit. Attached Figure Description

[0027] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0028] Figure 1 A circuit diagram of an analog switching circuit in the prior art;

[0029] Figure 2 This is a schematic diagram of an analog switch circuit with latching function according to an embodiment of the present invention;

[0030] Figure 3 This is a circuit diagram of a latch logic control circuit according to an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of protection of the invention.

[0032] The application principle of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] like Figure 2 As shown, this invention provides an analog switch circuit with latching function, including an input shaping circuit, a latching logic control circuit, a level conversion circuit, an output shaping circuit, and a switching circuit;

[0034] The input shaping circuit shapes the received voltage signal and sends the shaped voltage signal to the latch logic control circuit. In specific implementation, the shaped voltage signal needs to meet the TTL level requirement, which can be achieved by the input shaping circuit in the prior art.

[0035] The latch logic control circuit performs different logic controls on the received voltage signal to generate different first control signals, thereby obtaining different switching states, such as clear state, hold state, on and off state, etc. In specific applications, the voltage range of the first control signal is 0V to positive voltage.

[0036] The level conversion circuit converts the voltage range of the first control signal to a preset voltage range to generate a second control signal; in specific implementation, the preset range is a positive and negative voltage range.

[0037] The input terminal of the output shaping circuit is connected to the output terminal of the level conversion circuit, and its output terminal is connected to the switching circuit to generate a switching control signal to control the switching circuit.

[0038] This invention designs a latching logic control circuit in an analog switching circuit that can perform different logic controls on the received voltage signal, thereby extending the function of the switching circuit to include latching and other functions, and improving the reliability of the analog switching circuit.

[0039] In one specific embodiment of the present invention, the input shaping circuit includes a first input port, a second input port, a third input port, and a fourth input port, which are respectively used to receive the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR; the input shaping circuit includes a first output port, a second output port, a third output port, and a fourth output port, which are respectively used to output the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR.

[0040] In one specific embodiment of the present invention, the latch logic control circuit is used to generate control signals such as enable and latch; for example... Figure 3As shown, the latch logic control circuit specifically includes a first flip-flop (dffp), a second flip-flop (dffpc_), a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate.

[0041] The D interface of the first flip-flop is connected to the first output terminal of the input shaping circuit to receive the control signal IN, and its CLK interface is connected to the third output terminal of the input shaping circuit to receive the read / write signal WR.

[0042] The D interface of the second flip-flop dffpc_ is connected to the second output terminal of the input shaping circuit to receive the enable signal EN, its CLK interface is connected to the fourth output terminal of the input shaping circuit to receive the read / write signal WR, and its CLR interface is connected to the third output terminal of the input shaping circuit to receive the reset signal RS.

[0043] The output terminal Q of the first flip-flop dffp is connected to the input terminal (A terminal) of the first inverter, and the output terminal (Y terminal) of the first inverter is connected to one of the input terminals (A terminal) of the first NAND gate;

[0044] The inverted output terminal Q_ of the first flip-flop dffp is connected to the input terminal (A terminal) of the second inverter, and the output terminal (Y terminal) of the second inverter is connected to one of the input terminals (A terminal) of the second NAND gate;

[0045] The output terminal Q of the second flip-flop dffpc_ is connected to the other input terminal (B terminal) of the first NAND gate and the second NAND gate respectively. The output terminal Q of the second flip-flop dffpc_ outputs the ENC signal to the first NAND gate and the second NAND gate.

[0046] The output terminal (Y terminal) of the first NAND gate is connected to the input terminal (A terminal) of the third inverter, and the output terminal (Y terminal) of the third inverter is used to output the INC signal;

[0047] The output terminal (Y terminal) of the second NAND gate is connected to the input terminal (A terminal) of the fourth inverter. The output terminal (Y terminal) of the fourth inverter is used to output the INB signal, which is complementary to the INC signal.

[0048] When the reset signal RS is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0. The INC signal and the INB signal constitute the first control signal, which is used to control the switching circuit to be in the cleared state.

[0049] When the reset signal RS is logic 1 and the read / write signal WR is logic 1, the ENC signal, INC signal, and INB signal are in a holding state. The INC signal and INB signal constitute the first control signal, which is used to control the switching circuit to be in a holding latch state.

[0050] When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 1, the signal ENC is logic 1, and the logic signal IN is used as the first control signal to control the state of the switching circuit.

[0051] When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 0, the ENC signal is logic 0, and the INC and INB signals are both logic 0. The INC and INB signals constitute the first control signal, which is used to control the switching circuit to be in the off state.

[0052] In practical applications, since the amplitude of the first control signal may not meet the requirements of the switching circuit, it is usually necessary to use an output shaping circuit to shape the first control signal and generate a second control signal, which is used to directly control the switching circuit.

[0053] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An analog switching circuit with latching function, characterized in that: It includes input shaping circuit, latch logic control circuit, level conversion circuit, output shaping circuit and switching circuit; The input shaping circuit shapes the received voltage signal and sends the shaped voltage signal to the latch logic control circuit. The latch logic control circuit performs different logic controls on the received voltage signal to generate different first control signals; The level conversion circuit converts the voltage range of the first control signal to a preset voltage range to generate the second control signal; The input terminal of the output shaping circuit is connected to the output terminal of the level conversion circuit, and its output terminal is connected to the switching circuit to generate a switching control signal to control the switching circuit. The input shaping circuit includes a first input port, a second input port, a third input port, and a fourth input port, which are used to receive the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR, respectively; the input shaping circuit includes a first output port, a second output port, a third output port, and a fourth output port, which are used to output the control signal IN, the enable signal EN, the reset signal RS, and the read / write signal WR, respectively. The latch logic control circuit includes a first flip-flop, a second flip-flop, a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate; The D interface of the first flip-flop is connected to the first output terminal of the input shaping circuit for receiving the control signal IN, and its CLK interface is connected to the third output terminal of the input shaping circuit for receiving the read / write signal WR. The D interface of the second flip-flop is connected to the second output terminal of the input shaping circuit to receive the enable signal EN, its CLK interface is connected to the fourth output terminal of the input shaping circuit to receive the read / write signal WR, and its CLR interface is connected to the third output terminal of the input shaping circuit to receive the reset signal RS. The output terminal Q of the first flip-flop is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to one of the input terminals of the first NAND gate. The inverted output terminal Q_ of the first flip-flop is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to one of the input terminals of the second NAND gate; The output terminal Q of the second flip-flop is connected to the other input terminal of the first NAND gate and the second NAND gate respectively, and outputs the ENC signal to the first NAND gate and the second NAND gate; The output of the first NAND gate is connected to the input of the third inverter, and the output of the third inverter is used to output the INC signal. The output of the second NAND gate is connected to the input of the fourth inverter. The output of the fourth inverter is used to output the INB signal, which is complementary to the INC signal.

2. The analog switch circuit with latching function according to claim 1, characterized in that: When the reset signal RS is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0. The INC signal and the INB signal constitute the first control signal, which is used to control the switching circuit to be in the cleared state. When the reset signal RS is logic 1 and the read / write signal WR is logic 1, the ENC signal, INC signal, and INB signal are in a holding state. The INC signal and INB signal constitute the first control signal, which is used to control the switching circuit to be in a holding latch state. When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 1, the signal ENC is logic 1, and the logic signal IN is used as the first control signal to control the state of the switching circuit. When the reset signal RS is logic 1, the read / write signal WR is logic 0, and the enable signal EN is logic 0, the ENC signal is logic 0, and the INC and INB signals are both logic 0. The INC and INB signals constitute the first control signal, which is used to control the switching circuit to be in the off state.

3. The analog switch circuit with latching function according to claim 1, characterized in that: The preset range is the range of positive and negative power supply voltages.

4. The analog switch circuit with latching function according to claim 1, characterized in that: The shaped voltage signal must meet the TTL level requirements.

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