An embedded platform tpcm access system and a control method thereof

Abstract

The application discloses an embedded platform TPCM access system and a control method thereof, which comprises an embedded processor, a trusted platform control module, a storage module, an SPI interface control module and a monitoring module; the embedded processor provides a reset signal to the monitoring module and receives a processor global reset signal from the monitoring module; the embedded processor is interconnected with the storage module through an SPI1 bus and interconnected with the SPI interface control module through the SPI1 bus; the trusted platform control module performs a trusted measurement of the embedded processor; the trusted platform control module is interconnected with the SPI control module through an SPI2 bus; the storage module stores a start mirror image of the embedded processor; the SPI interface control module controls an access object of the storage module according to the processor global reset signal; and the monitoring module generates a restart control signal and the processor global reset signal according to the reset signal.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of trusted computing of embedded devices, and particularly relates to an embedded platform TPCM access system and a control method thereof. BACKGROUND

[0002] An embedded system is a special computer system that is application-centered and based on modern computer technology, and can flexibly tailor software and hardware modules according to user needs (function, reliability, cost, size, power consumption, environment, etc.). At present, embedded systems have been widely used in industrial control, network communication and other products, and bear diversified and complex service functions, and accordingly, the security risks are increasing. Once the program is tampered with, etc., it may cause a security incident, and therefore, it is necessary to add a trusted computing security mechanism in the embedded system.

[0003] A trusted computing control module mainly includes a trusted platform module (TPM) of the international trusted computing group (Trusted Computing Group) and a trusted platform control module (TPCM) of the Chinese national standard GB / T 29827-2013. The TPCM is a hardware module integrated in a trusted platform, is a trusted root of an active immunization trusted system, is mainly used for establishing and guaranteeing a trust source point, and provides a series of trusted computing functions such as trusted platform control, integrity measurement, secure storage, trusted reporting and cryptographic services. The TPCM is accessed in an embedded platform to build a predictable running environment for the platform, to ensure that the program will not be maliciously tampered with or stolen, and to achieve the safe running of the embedded system. After the TPCM is accessed in the embedded platform, it is necessary to ensure that the TPCM can be correctly put into operation and perform trusted measurement, and it is also necessary to ensure that the TPCM does not affect the system program when the embedded platform runs a working program, and therefore, it is an important research topic to design a reasonable TPCM access system and enable the TPCM to correctly switch in different working modes.

[0004] Invention patent application CN202010203010.0 discloses a trusted measurement method based on an M.2 interface, which defines a plurality of control signals for TPCM access on a standardized M.2 interface, and solves the problem of low adaptability of the TPCM. Although the invention patent application designs the control signals and working process of the TPCM access system, the control signals of the TPCM are not isolated from the main system after the TPCM completes the trusted measurement, and it is difficult to prevent the disturbance of the main system caused by the fault of the TPCM.

[0005] The application patent application CN201610304629.4 discloses a kind of by TPCM control POWER platform trusted implementation method and system, this method is by TPCM, third party control module, POWER platform is made of trust chain, by the power-on sequence between control module, the access of TPCM on POWER platform is realized.This application patent application needs to rely on the cooperation of third party control module and power supply system to complete the access of trusted platform control module, system design is difficult, cost is high, and this method only gives the solution when system is powered on, does not give the access method of trusted platform control module when embedded system needs to be restarted without power failure during the process of normal running application program. SUMMARY

[0006] The application aims to solve the problem that trusted platform control module can affect system program when running work program in embedded platform, and proposes an embedded platform TPCM access system and control method, which realizes reliable switching of TPCM between different working modes by controlling watchdog and other hardware circuits, so that TPCM can be reliably put into operation for performing trusted measurement during cold start and hot start of embedded system.After completing trusted measurement, TPCM can be reliably isolated from embedded running environment to avoid the influence of abnormal running state of TPCM on the normal running of embedded application program.

[0007] Technical scheme: an embedded platform TPCM access system, comprising an embedded processor, a trusted platform control module, a storage module, an SPI interface control module and a monitoring module.

[0008] The embedded processor is configured to provide a reset signal to the monitoring module, and receive a processor global reset signal from the monitoring module; when the processor global reset signal is at low level, the embedded processor is in a reset state; when the processor global reset signal is at high level, the embedded processor enters a reset start state or a running state; the embedded processor is interconnected with the storage module through SPI1 bus, and interconnected with the SPI interface control module through SPI1 bus; the reset start state includes a cold start state and a hot start state; the cold start state is that when the embedded system is initially powered on, the processor global reset signal is pulled from low level to high level to enter the start state; the hot start state is that when the embedded system is in a running state, the processor global reset signal is pulled to low level first to make the embedded system enter the reset state, and then the processor global reset signal is pulled to high level again to make the embedded system re-enter the start state; the running state is that the embedded system enters the normal program running state after completing cold start or hot start;

[0009] The TPCM is configured to pre-store trusted root reference values of each stage of the embedded processor startup, perform trusted measurement of the embedded processor, provide a TPCM reset state signal to the monitoring module, and receive a restart control signal from the monitoring module; the TPCM is interconnected with the SPI control module through an SPI2 bus

[0010] The storage module is configured to store a startup image of the embedded processor.

[0011] The SPI interface control module is configured to control an access object of the storage module according to a processor global reset signal from the monitoring module; the access object is the TPCM or the embedded processor; when the processor global reset signal is at a high level, the embedded processor accesses the storage module; and when the processor global reset signal is at a low level, the TPCM accesses the storage module.

[0012] The monitoring module is configured to generate a restart control signal provided to the TPCM according to a reset signal from the embedded processor, and provide a processor global reset signal to the SPI interface control module and the embedded processor according to the restart control signal and a TPCM reset state signal from the TPCM.

[0013] Further, when the embedded processor is initially powered on and in a reset state, a pin of the embedded processor on which the reset signal is provided is in a high-impedance state, and an SPI standard interface of the embedded processor is in a high-impedance state.

[0014] Further, the TPCM is integrated with a power-on reset circuit configured to generate the TPCM reset state signal.

[0015] Further, the reset signal provided by the embedded processor to the monitoring module includes a watchdog kick signal, a watchdog manual reset control signal, and a signal for allowing a reset during running.

[0016] The monitoring module includes a watchdog module and a reset logic generation circuit.

[0017] The watchdog module is configured to output the restart control signal according to the watchdog kick signal and the watchdog manual reset control signal; when the watchdog manual reset control signal is at a low level, the restart control signal is at a low level; when the watchdog manual reset control signal is at a high level and an interval of the watchdog kick signal exceeds a watchdog interval, the restart control signal is at a low level; and when the watchdog manual reset control signal is at a high level and the interval of the watchdog kick signal does not exceed the watchdog interval, a pin outputting the restart control signal is in a high-impedance state.

[0018] The reset logic generation circuit outputs a processor global reset signal according to a signal for allowing reset during running, a restart control signal and a TPCM reset state signal;

[0019] When the signal for allowing reset during running and the restart control signal are AND logic low, the processor global reset signal reflects the state of the TPCM reset state signal;

[0020] When the signal for allowing reset during running and the restart control signal are AND logic high, the processor global reset signal remains high;

[0021] When the embedded processor is initially powered on and in a reset state, the pins of the embedded processor on which the watchdog kick signal, the watchdog manual reset control signal and the signal for allowing reset during running are provided are in a high-impedance state.

[0022] Further, the watchdog module comprises a watchdog chip, a first pull-up resistor and a second pull-up resistor;

[0023] Pin 1 of the watchdog chip receives the watchdog kick signal, pin 2 of the watchdog chip receives the watchdog manual reset control signal, and pin 3 of the watchdog chip outputs the restart control signal;

[0024] Pin 2 of the watchdog chip is pulled up to the power supply externally by the first pull-up resistor;

[0025] Pin 3 of the watchdog chip is pulled up to the power supply by the second pull-up resistor.

[0026] Further, the reset logic generation circuit comprises a buffer, an AND gate, a pull-down resistor and a third pull-up resistor; the buffer has an enable control end;

[0027] The AND gate is used to perform AND logic on the signal for allowing reset during running and the restart control signal, and the output end of the AND gate is connected to the enable control end of the buffer; the pin of the AND gate receiving the signal for allowing reset during running is pulled down to the ground by the pull-down resistor;

[0028] The buffer receives the TPCM reset state signal and outputs the processor global reset signal; the output end of the buffer is pulled up to the power supply by the third pull-up resistor;

[0029] When the enable control end of the buffer is connected to low, the processor global reset signal reflects the state of the TPCM reset state signal;

[0030] When the enable control end of the buffer is connected to high, the output end of the buffer is in a high-impedance state, and the processor global reset signal remains high.

[0031] Further, the SPI interface control module comprises a bus transceiver, and the bus transceiver has an enable control end; the enable control end of the bus transceiver is used for accessing a processor global reset signal;

[0032] When the processor global reset signal is at a high level, the enable control end of the bus transceiver is in an inhibition state, the SPI1 bus and the SPI2 bus are isolated, and the embedded processor accesses the storage module;

[0033] When the processor global reset signal is at a low level, the enable control end of the bus transceiver is in an enable state, the SPI1 bus and the SPI2 bus are interconnected, and the trusted platform control module accesses the storage module.

[0034] The application discloses a control method for an embedded platform TPCM access system, and the embedded platform TPCM access system is the embedded platform TPCM access system disclosed in the above.

[0035] The control method comprises the following steps: controlling the trusted platform control module to perform a cold start measurement.

[0036] The step of controlling the trusted platform control module to perform the cold start measurement comprises the following steps:

[0037] After the embedded processor is initialized, the high and low levels of each pin of the embedded processor are set according to an initialization program, a signal for allowing reset during operation passes through an external pull-down resistor and is at a low level; the trusted platform control module is powered on and started, before a trusted start measurement is completed, a TPCM reset state signal is at a low level, a signal for allowing reset during operation passes through an external pull-down resistor and is at a low level, a processor global reset signal provided by the monitoring module to the embedded processor is at a low level, the processor global reset signal at the low level causes the embedded processor to be at a reset state; meanwhile, the processor global reset signal at the low level causes the trusted platform control module TPCM to be connected to the SPI1 bus through the SPI2 bus and access the storage module.

[0038] The trusted platform control module reads the Bootloader from the storage module to perform a trusted measurement.

[0039] After the bootloader is measured by the trust, the trusted platform control module pulls up the TPCM reset state signal, the processor global reset signal is high, and the high level processor global reset signal makes the embedded processor enter the reset start state; at the same time, the high level processor global reset signal makes the embedded processor obtain the storage module SPI bus control right, and the cold start measurement is completed.

[0040] The application discloses a control method for an embedded platform TPCM access system, and the embedded platform TPCM access system is the embedded platform TPCM access system disclosed above.

[0041] The control method comprises the following steps: controlling the bypassing of the trusted platform control module in the process of normally running an application program of the embedded system.

[0042] The step of controlling the bypassing of the trusted platform control module in the process of normally running an application program of the embedded system comprises the following steps.

[0043] After the trusted platform control module completes the cold start measurement, the embedded processor loads and runs the bootloader from the storage module, completes the start of the embedded processor, and starts device initialization, pulls up the signal for allowing reset during running, provides the watchdog kick signal to the monitoring module according to the watchdog time interval, pulls up the watchdog manual reset control signal, makes the watchdog exit the reset state, pulls up the restart control signal, and makes the processor global reset signal output by the buffer keep high; the high level processor global reset signal makes the SPI bus control right of the storage module be separated from the trusted platform control module, and the trusted platform control module is bypassed.

[0044] The application discloses a control method for an embedded platform TPCM access system, and the embedded platform TPCM access system is the embedded platform TPCM access system disclosed above.

[0045] The control method comprises the following steps: controlling the trusted platform control module to perform hot start measurement; the hot start measurement is that the embedded processor is restarted without power-off, and before the embedded processor kernel reloads the bootloader, the trusted platform control module performs trust measurement on the bootloader.

[0046] The step of controlling the trusted platform control module to perform hot start measurement comprises the following steps.

[0047] The restart control signal is low;

[0048] The TPCM reset state signal is low;

[0049] The low-level restart control signal and the low-level TPCM reset state signal make the buffer generate a low-level processor global reset signal;

[0050] The low-level processor global reset signal makes the embedded processor enter a reset state, and when the embedded processor enters the reset state, an SPI standard interface on the embedded processor, a pin outputting a signal for allowing a reset during running, a pin outputting a watchdog kick signal and a pin outputting a watchdog manual reset control signal are all in a high-impedance state;

[0051] The low-level processor global reset signal makes the trusted platform control module obtain SPI bus control right of the storage module, and the trusted platform control module reads Bootloader from the storage module to perform trust measurement;

[0052] After the Bootloader is measured, the trusted platform control module pulls up the TPCM reset state signal, so that the processor global reset signal is high, and the high-level processor global reset signal makes the embedded processor enter a reset start state; meanwhile, the high-level processor global reset signal makes the embedded processor obtain the SPI bus control right of the storage module, and at this time, hot start measurement ends.

[0053] Further, the restart control signal is low, and the method comprises the following steps:

[0054] When the watchdog kick signal is interrupted and the watchdog timer overflows, the restart control signal is in a low-level state; or when the embedded processor pulls down the watchdog manual reset control signal according to application program requirements, the restart control signal is in a low-level state.

[0055] Advantages: compared with the prior art, the embedded platform TPCM access system and the working mode switching method thereof have the following advantages:

[0056] (1) The embedded platform TPCM access system and the working mode switching method thereof design a storage unit SPI interface control right exchange mechanism and an embedded processor reset mechanism based on hardware logic, so that when the TPCM performs trust measurement, the CPU is in a reliable reset state, the TPCM exclusively occupies the access control right of the storage module, the system is started when power is turned on, the trusted start has a trusted entrance, and the storage module cannot be tampered with;

[0057] (2) The TPCM enters the bypass mode switching method, so that the TPCM is quickly isolated from the embedded processor application program running environment after completing the trusted start measurement, and the normal running of the embedded processor application program is not affected when the TPCM appears reset, suspension and other abnormal running conditions;

[0058] (3) The TPCM of the present application re-executes the entering method of trusted measurement when the embedded processor is hot-started. When the embedded processor program runs away, the hardware logic circuit is used to make the TPCM have the access control right of the storage module and execute the hot-started trusted measurement. When the embedded processor application program needs to be restarted, the software trigger and the hardware logic circuit are used to make the TPCM have the access control right of the storage module and execute the hot-started trusted measurement. The two methods of entering the hot-started trusted measurement mode of the TPCM can make the TPCM have the access control right of the storage module when the trusted measurement is executed, and ensure that the storage module is not tampered during the hot-started period. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1 The typical component block diagram of the embedded platform TPCM access system is shown in Figure 1.

[0060] Figure 2 The typical component block diagram of the monitoring module is shown in Figure 2. DETAILED DESCRIPTION

[0061] The technical solutions of the present application will be further described in combination with the drawings and embodiments.

[0062] The present embodiment proposes an embedded platform TPCM access system, Figure 1 The typical component block diagram of the embedded platform TPCM access system is shown in Figure 1, which mainly includes an embedded processor 11, a trusted platform control module TPCM 12, a storage module 13, an SPI interface control module 14 and a monitoring module 15. The TPCM 12 and the SPI interface control module 14 are interconnected, the SPI interface control module 14 and the storage module 13 and the embedded processor 11 are interconnected, the monitoring module 15 and the TPCM 12 and the embedded processor 11 are interconnected, and the monitoring module 15 is connected with the SPI interface control module 14. Specifically,

[0063] The embedded processor 11, as the core of the embedded platform, includes an SPI standard interface providing SPI1 signals, a pin for receiving the processor global reset signal RST1, a pin for outputting the signal RST-EN for enabling reset during operation, a pin for outputting the watchdog kick signal WDT-IN, and a pin for outputting the watchdog manual reset control signal MR. The embedded processor 11 provides the watchdog kick signal WDT-IN, the signal RST-EN for enabling reset during operation, and the watchdog manual reset control signal MR to the monitoring module 15, and receives the processor global reset signal RST1 from the monitoring module 15. The SPI1 signals provided by the embedded processor 11 include the SPI1 chip select signal SPI1-CS. The embedded processor 11 also interconnects with the storage module 13 via the SPI1 bus and with the SPI interface control module 14 via the SPI1 bus. When the embedded processor 11 is initially powered on and in the reset state, the SPI standard interface providing the SPI1 signal is in a high-impedance state, the pin that outputs the watchdog kick signal WDT-IN is in a high-impedance state, and the pin that outputs the signal RST-EN used to enable reset during operation is in a high-impedance state.

[0064] The Trusted Platform Control Module (TPCM) 12 is used to pre-store the root trust reference values ​​for each stage of the embedded processor 11's startup, perform trust measurements on the embedded processor 11, and achieve secure startup of the embedded processor 11. The TPCM 12 includes an SPI standard interface providing SPI2 signals, a pin for receiving the restart control signal WDT-O, and a pin for outputting the TPCM reset status signal RST2. The TPCM 12 outputs the TPCM reset status signal RST2 to the monitoring module 15 and receives the restart control signal WDT-O from the monitoring module 15. The SPI2 signals of the TPCM 12 include the SPI2 chip select signal SPI2-CS. The TPCM 12 is interconnected with the SPI control module 14 via the SPI2 bus. The TPCM reset status signal RST2 is provided by a power-on reset circuit integrated on the TPCM 12. This invention uses a TPCM 12 with an internally integrated power-on reset circuit, and its functional logic is guaranteed by the selected TPCM 12 module.

[0065] The TPCM 12 controls the state of the TPCM reset signal RST2 by itself. During the power-on process of the TPCM 12, the RST2 keeps a reset logic output; after the normal power-on is completed, the RST2 enters a normal logic output. In the normal running state of the TPCM 12, the restart control signal WDT-O is connected to the TPCM 12, so that the TPCM 12 enters a hot start state. After the TPCM 12 enters the hot start state, the trust measurement operation is restarted.

[0066] The storage module 13 is configured to store the start image of the embedded processor 11. The storage module 13 includes a slave mode SPI interface.

[0067] The SPI interface control module 14 is configured to control the access object of the slave mode SPI interface of the storage module 13, that is, whether to access the embedded processor 11 or to access the TPCM 12. The SPI interface control module 14 includes two SPI standard interfaces and a pin receiving the processor global reset signal RST1; the two SPI standard interfaces are respectively configured to be connected with the SPI1 bus and the SPI2 bus; the SPI interface control module 14 uses a bus transceiver with an enable control to complete the right transformation of the SPI1 bus. The pin receiving the processor global reset signal RST1 is configured as the enable control end of the bus transceiver. When the processor global reset signal RST1 is at a high level, the enable control end of the bus transceiver is in an inhibition state, the bus pins of the bus transceiver are in a high resistance state, the SPI1 bus and the SPI2 bus are not electrically connected, that is, the SPI1 bus and the SPI2 bus are isolated, and the bus buffer realizes buffering and isolation at this time. When the processor global reset signal RST1 is at a low level, the enable control end of the bus transceiver is in an enable state, the SPI2 bus obtains the control right of the SPI1 bus, that is, the SPI1 bus and the SPI2 bus are interconnected, and the TPCM 12 can access the storage module 13. The bus transceiver uses but is not limited to a 74HC245 chip, and the processor global reset signal RST1 controls the enable control end of the 74AHC245 chip.

[0068] The monitoring module 15 is configured to monitor the running state of the embedded system program, generate a restart control signal WDT-O provided to the TPCM 12 and a processor global reset signal RST1 provided to the SPI interface control module 14 and the embedded processor 11, and receive a watchdog kick signal WDI-IN, a watchdog manual reset control signal MR, a signal RST-EN for allowing reset during running, and a TPCM reset state signal RST2. The monitoring module 15 of the embodiment mainly comprises a watchdog module and a reset logic generation circuit. The watchdog module receives the watchdog kick signal WDI-IN and the watchdog manual reset control signal MR provided by the embedded processor 11, and outputs the restart control signal WDT-O. The reset logic generation circuit generates the processor global reset signal RST1 using an enable-controlled buffer, the input signal of the buffer being the TPCM reset state signal RST2, the control enable signal of the buffer being obtained by AND logic of the restart control signal WDT-O and the signal RST-EN for allowing reset during running, and the buffer using, but not limited to, a 74HC125D chip.

[0069] Figure 2 A typical block diagram of the monitoring module 15 is shown in FIG. 2, which comprises a watchdog module 21, a buffer 22, an AND gate 23, a pull-down resistor R1, a first pull-up resistor R2, a second pull-up resistor R3, and a third pull-up resistor R4.

[0070] The watchdog module 21 is a dedicated watchdog chip. Pin 1 of the watchdog module 21 receives the watchdog kick signal WDI-IN provided by the embedded processor 11, pin 2 of the watchdog module 21 receives the watchdog manual reset control signal MR, and pin 3 of the watchdog module 21 outputs the restart control signal WDT-O. Pin 2 of the watchdog module 21 is pulled up to the power supply VCC by the first pull-up resistor R2, pin 3 is an "open drain" output, and is pulled up to the power supply VCC by the second pull-up resistor R3. The output state of pin 3 is controlled by the states of pins 1 and 2. When pin 2 is at a low level, pin 3 enters a reset state and outputs a low level. When pin 2 is at a high level and the output signal interval of pin 3 exceeds the watchdog interval, pin 3 enters a reset state and outputs a low level, otherwise it is in a high impedance state.

[0071] AND gate 23 performs an AND operation on the restart control signal WDT-O output from pin 3 of watchdog module 21 and the signal RST-EN used to enable reset during operation. The output signal of AND gate 23 is connected to the enable control terminal EN of buffer 22. Buffer 24 receives the TPCM reset status signal RST2 and outputs the processor global reset signal RST1. The signal RST-EN used to enable reset during operation is pulled down to ground through pull-down resistor R1. The output terminal of buffer 22 is an "open-drain" output and is pulled up to the power supply VCC through the third pull-up resistor R4. When the enable control terminal EN of buffer 22 is low, the processor global reset input signal RST1 reflects the status of the TPCM reset status output signal RST2. When the enable control terminal EN of buffer 22 is high, the output terminal of buffer 22 is in a high-impedance state, and the processor global reset signal RST1 is no longer affected by the TPCM reset status signal RST2.

[0072] This embodiment proposes a TPCM operating mode switching method for the aforementioned embedded platform TPCM access system. Through logic control, the Trusted Platform Control Module (TPCM12) switches between a cold start trusted startup measurement mode, a TPCM bypass mode, and a warm start trusted startup measurement mode. The cold start trusted startup measurement mode refers to the mode in which the Trusted Platform Control Module (TPCM) measures the Bootloader during the initial power-up of the embedded system, before the embedded processor kernel starts. The TPCM bypass mode refers to the mode in which the Trusted Platform Control Module (TPCM) is bypassed and does not operate on the storage module during the normal operation of the embedded system after completing the cold start trusted startup measurement and the system's application. The warm start trusted startup measurement mode refers to the mode in which, during the normal operation of the system's application after completing the cold start trusted startup measurement, if the embedded processor needs to restart without power loss and the embedded processor kernel needs to reload the Bootloader, the Trusted Platform Control Module (TPCM) performs a trusted measurement on the Bootloader.

[0073] After the embedded system is powered on, the Trusted Platform Control Module (TPCM) immediately enters the cold start trusted startup metric mode as follows:

[0074] After the embedded system is powered on, the pin of the embedded processor 11 that outputs the signal RST-EN to enable reset during operation is in a high-impedance state until the embedded processor 11 completes initialization;

[0075] After the embedded processor 11 completes initialization, the high and low levels of each pin on the embedded processor 11 are set according to the initialization program. At this time, the signal RST-EN that enables reset during operation is low through the external pull-down resistor.

[0076] The trusted platform control module (TPCM) is powered on, and the TPCM reset state signal RST2 is always in a low state before the completion of the trusted boot measurement;

[0077] The signal RST-EN in a low state for allowing reset during operation enables the buffer 22 in the monitoring module 15, and the TPCM reset state signal RST2 generates the processor global reset signal RST1 through the buffer, and the low state of the processor global reset signal RST1 enables the embedded processor 11 to be in a reset state;

[0078] The low state of the processor global reset signal RST1 enables the enable end of the bus buffer in the SPI interface control module 14, and the trusted platform control module (TPCM) takes control of the SPI1 bus of the storage module 13; the TPCM is connected to the SPI1 bus through the SPI2 bus and the bus buffer after buffering, and accesses the storage module 13;

[0079] The TPCM reads the Bootloader from the storage module 13 for trusted measurement;

[0080] After the Bootloader is measured by the trusted platform control module (TPCM), the TPCM pull-up the TPCM reset state signal RST2, and the processor global reset signal RST1 is also in a high state, so that the embedded processor 11 enters a reset start state; at the same time, the bus buffer enable of the SPI interface control module 14 is disabled, and the embedded processor 11 takes control of the SPI bus of the storage module, and the cold start trusted boot measurement mode ends.

[0081] The trusted platform control module (TPCM) is powered on, and the TPCM reset state signal RST2 is always in a low state before the completion of the trusted boot measurement;

[0082] The TPCM bypass mode includes TPCM bypass mode 1 and TPCM bypass mode 2.

[0083] After the TPCM finishes the cold start trusted boot measurement mode, it immediately enters the TPCM bypass mode 1. At this time, the embedded processor 11 starts to load and run the Bootloader from the storage module 13, and completes the start. Then the embedded processor 11 starts the device initialization, pulls up the signal RST-EN for allowing the reset during the running period, and simultaneously outputs the watchdog kick signal WDT-IN to the monitoring module 15 at a set period and pulls up the watchdog manual reset control signal MR, so that the watchdog exits the reset state, and the restart control signal WDT-O is pulled up. The signal RST-EN for allowing the reset during the running period and the restart control signal WDT-O are subjected to AND logic, and the gate output is high level, the buffer output in the reset logic generation circuit is prohibited, the buffer 22 pin keeps high impedance state, and the processor global reset signal RST1 keeps high level through the external third pull-up resistor R4. At this time, the TPCM enters the TPCM bypass mode 2.

[0084] The TPCM enters the TPCM bypass mode 2. The processor global reset signal RST1 keeps high level through the external third pull-up resistor R4, and is no longer affected by the TPCM reset state signal RST2. The SPI bus control right of the storage module 13 is also separated from the TPCM control signal. In the case of abnormality of the TPCM, the embedded processor 11 will not enter the reset state or the interconnection SPI module of the storage module 13 will not be interrupted.

[0085] The TPCM enters the hot start trusted boot measurement mode in the following manner:

[0086] The restart control signal WDT-O is set to low level. There are two ways to set the restart control signal WDT-O to low level. One way is that the embedded processor program runs away, causes the watchdog kick signal WDT-IN to be interrupted, the watchdog timer overflows, and sets the restart control signal WDT-O to low level state. The other way is that the embedded processor 11 pulls down the watchdog manual reset control signal MR according to the application program requirement, so that the watchdog outputs the restart control signal WDT-O to enter the reset low level state.

[0087] The low level of the restart control signal WDT-O controls the TPCM to enter the reset state, and the TPCM reset state signal RST2 outputs low level. Meanwhile, the low level of the restart control signal WDT-O makes the buffer 22 in the monitoring module 15 in the enabled state, the TPCM reset state signal RST2 generates the processor global reset signal RST1 through the buffer, and the processor global reset signal RST1 outputs low level.

[0088] The low level state of the processor global reset signal RST1 makes the embedded processor 11 enter the reset state, and the SPI standard interface provided with the SPI1 signal, the pin outputting the signal RST-EN for allowing the reset during the running, the pin outputting the watchdog kick signal WDT-IN and the pin outputting the watchdog manual reset control signal MR on the embedded processor 11 are all in the high resistance state;

[0089] The low level state of the processor global reset signal RST1 enables the bus buffer of the SPI interface control module, and the trusted platform control module TPCM obtains the SPI bus control right of the storage module 13.

[0090] The trusted platform control module TPCM reads the Bootloader from the storage module 13 to perform the trust measurement.

[0091] After the measurement of the Bootloader, the trusted platform control module TPCM pulls up the TPCM reset state signal RST2, and the processor global reset signal RST1 also shows the high level, so that the embedded processor 11 enters the reset start state; meanwhile, the bus buffer enable of the SPI interface control module 14 is prohibited, and the embedded processor 11 obtains the SPI bus control right of the storage module 13, and at this time, the hot start trusted start measurement mode ends.

[0092] The trusted platform control module TPCM provides two trigger modes for entering the hot start trusted start measurement mode, that is, the reliable entry into the trusted start can be ensured when the application program runs away, and the reliable entry into the trusted start can be ensured according to the application requirement. Meanwhile, after the trusted platform control module TPCM enters the hot start trusted start measurement mode, the reset logic control is still provided to ensure that the embedded processor 11 is always in the reset state; meanwhile, through the feature that the pin is in the high resistance state during the power-on reset process of the embedded processor 11, it is ensured that the TPCM 12 can exclusively control the SPI1 of the storage module, and this design method can ensure that the TPCM 12 exclusively controls the storage module, provides the reliable entry into the trusted start measurement, and also ensures that the storage space of the storage module cannot be tampered and counterfeited during the start.

[0093] The technical features of the above embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, it should be considered that the combinations are within the scope of the present disclosure.

[0094] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific and detailed manner, but should not be construed as limiting the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are all within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. An embedded platform TPCM access system, characterized in that: It includes an embedded processor, a trusted platform control module, a storage module, an SPI interface control module, and a monitoring module; The embedded processor is used to provide a reset signal to the monitoring module and to receive a global processor reset signal from the monitoring module. When the global processor reset signal is low, the embedded processor is in a reset state; when the global processor reset signal is high, the embedded processor enters a reset startup state or a running state. The embedded processor is interconnected with the storage module via an SPI1 bus and with the SPI interface control module via an SPI1 bus. The reset startup state includes a cold startup state and a warm startup state. The cold startup state is when the embedded system initially powers on and the global processor reset signal is pulled from low to high to enter the startup state. The warm startup state is when the embedded system is in the running state, the global processor reset signal is first pulled low to enter the reset state, and then the global processor reset signal is pulled high to re-enter the startup state. The running state is the state where the embedded system enters normal program operation after completing a cold or warm startup. The trusted platform control module is used to pre-store the trusted root reference values ​​for each stage of the embedded processor startup and to perform trusted measurements of the embedded processor. It also provides a TPCM reset status signal to the monitoring module and receives a restart control signal from the monitoring module; the trusted platform control module is interconnected with the SPI interface control module via the SPI2 bus; The storage module is used to store the boot image of the embedded processor; The SPI interface control module is used to control the access object of the storage module according to the processor global reset signal from the monitoring module; the access object is the trusted platform control module or the embedded processor; when the processor global reset signal is high, the embedded processor accesses the storage module; when the processor global reset signal is low, the trusted platform control module accesses the storage module. The monitoring module is configured to generate a restart control signal for the trusted platform control module based on the reset signal from the embedded processor, and to provide a processor global reset signal to the SPI interface control module and the embedded processor based on the restart control signal and the TPCM reset status signal from the trusted platform control module.

2. The embedded platform TPCM access system according to claim 1, characterized in that: When the embedded processor is initially powered on and in a reset state, the pins on the embedded processor that provide the reset signal are in a high-impedance state, and the SPI standard interface on the embedded processor is also in a high-impedance state.

3. The embedded platform TPCM access system according to claim 1, characterized in that: The trusted platform control module integrates a power-on reset circuit, which is used to generate a TPCM reset status signal.

4. The embedded platform TPCM access system according to claim 1, characterized in that: The reset signals provided by the embedded processor to the monitoring module include: watchdog kick signal, watchdog manual reset control signal, and signal to allow reset during operation; The monitoring module includes a watchdog module and a reset logic generation circuit; The watchdog module is used to output a restart control signal based on the watchdog kick signal and the watchdog manual reset control signal. When the watchdog manual reset control signal is low, the restart control signal is low. When the watchdog manual reset control signal is high and the watchdog kick signal interval exceeds the watchdog timer interval, the restart control signal is low. When the watchdog manual reset control signal is high and the watchdog kick signal interval does not exceed the watchdog timer interval, the pin that outputs the restart control signal is in a high-impedance state. The reset logic generation circuit is used to output a processor global reset signal based on the signal that allows reset during operation, the restart control signal, and the TPCM reset status signal; When the AND logic of the signal used to enable reset during operation and the restart control signal is low, the processor global reset signal reflects the state of the TPCM reset status signal. The processor global reset signal remains high when the AND logic of the signal used to enable reset during operation and the restart control signal is high. When the embedded processor is initially powered on and in a reset state, the pins on the embedded processor that provide the watchdog kick signal, the watchdog manual reset control signal, and the signal for allowing reset during operation are in a high-impedance state.

5. The embedded platform TPCM access system according to claim 4, characterized in that: The watchdog module includes a watchdog chip, a first pull-up resistor, and a second pull-up resistor; Pin 1 of the watchdog chip receives the watchdog kick signal, pin 2 of the watchdog chip receives the watchdog manual reset control signal, and pin 3 of the watchdog chip outputs the restart control signal. Pin 2 of the watchdog chip is externally pulled up to the power supply through a first pull-up resistor; Pin 3 of the watchdog chip is pulled up to the power supply through a second pull-up resistor.

6. The embedded platform TPCM access system according to claim 5, characterized in that: The reset logic generation circuit includes a buffer, an AND gate, a pull-down resistor, and a third pull-up resistor; the buffer has an enable control terminal; The AND gate is used to perform AND logic on the signal that enables reset during operation and the restart control signal. The output of the AND gate is connected to the enable control terminal of the buffer. The pin on the AND gate that receives the signal that enables reset during operation is pulled down to ground through a pull-down resistor. The buffer receives the TPCM reset status signal and outputs the processor global reset signal; the output of the buffer is pulled up to the power supply through a third pull-up resistor. When the enable control terminal of the buffer is connected to a low level, the processor global reset signal reflects the state of the TPCM reset status signal. When the enable control terminal of the buffer is connected to a high level, the output terminal of the buffer is in a high-impedance state, and the processor global reset signal remains at a high level.

7. The embedded platform TPCM access system according to claim 1, characterized in that: The SPI interface control module includes a bus transceiver, which has an enable control terminal; the enable control terminal of the bus transceiver is used to access the processor global reset signal. When the processor global reset signal is high, the enable control terminal of the bus transceiver is disabled, the SP1 bus and the SPI2 bus are isolated, and the embedded processor accesses the storage module. When the processor global reset signal is low, the enable control terminal of the bus transceiver is enabled, the SPI1 bus and SPI2 bus are interconnected, and the trusted platform control module accesses the storage module.

8. A control method for an embedded platform TPCM access system, characterized in that: An embedded platform TPCM access system is the embedded platform TPCM access system as described in claim 6; The control method includes the step of controlling the trusted platform control module to perform cold start measurement; the cold start measurement is the measurement of the bootloader by the trusted platform control module when the embedded system is initially powered on and before the embedded processor kernel starts. The steps for the control module of the trusted platform to perform cold start measurement include: After the embedded processor completes initialization, the high and low levels of each pin on the embedded processor are set according to the initialization program. The signal that allows reset during operation is displayed as a low level through an external pull-down resistor. The Trusted Platform Control Module (TPCM) is powered on and started. Before the trusted startup measurement is completed, the TPCM reset status signal remains at a low level. The signal that allows reset during operation is displayed as a low level through an external pull-down resistor. The global processor reset signal provided by the monitoring module to the embedded processor is at a low level. The low-level global processor reset signal puts the embedded processor in a reset state. At the same time, the low-level global processor reset signal enables the Trusted Platform Control Module (TPCM) to connect to the SPI1 bus through the SPI2 bus to access the memory module. The trusted platform control module reads the Bootloader from the storage module to perform a trust measurement; After the bootloader passes the trust measurement, the Trusted Platform Control Module pulls the TPCM reset status signal high, and the processor global reset signal is high. The high-level processor global reset signal causes the embedded processor to enter the reset startup state. At the same time, the high-level processor global reset signal enables the embedded processor to gain control of the SPI1 bus of the storage module. At this time, the cold start measurement ends.

9. A control method for an embedded platform TPCM access system, characterized in that: An embedded platform TPCM access system is the embedded platform TPCM access system as described in claim 6; The control method includes: steps to bypass the trusted platform control module during the normal operation of the application in the embedded system; The steps for bypassing the trusted platform control module during the normal operation of the application in the embedded system include: After the trusted platform control module completes the cold start measurement, the embedded processor loads and runs the bootloader from the storage module, completes the embedded processor startup, and begins device initialization. It pulls a high signal to allow reset during operation, simultaneously provides a watchdog kick signal to the monitoring module at watchdog timer intervals, and pulls a high watchdog manual reset control signal to exit the watchdog reset state. It also pulls a high restart control signal to keep the processor global reset signal output from the buffer high. This high-level processor global reset signal disconnects the storage module's SPI1 bus control from the trusted platform control module, bypassing the trusted platform control module.

10. A control method for an embedded platform TPCM access system, characterized in that: An embedded platform TPCM access system is the embedded platform TPCM access system as described in claim 6; The control method includes the following steps: controlling the trusted platform control module to perform a hot start measurement; the hot start measurement refers to the embedded processor restarting without power loss, and the trusted platform control module performs a trusted measurement on the bootloader before the embedded processor kernel reloads the bootloader; The steps for the control module of the trusted platform to perform hot start measurement include: The reset / restart control signal is low. Set the TPCM reset signal to low level; A low-level restart control signal and a low-level TPCM reset status signal cause the buffer to generate a low-level processor global reset signal. A low-level global processor reset signal puts the embedded processor into a reset state. When the embedded processor is in a reset state, the SPI standard interface, the pin that outputs the signal that enables reset during operation, the pin that outputs the watchdog kick signal, and the pin that outputs the watchdog manual reset control signal are all in a high-impedance state. A low-level processor global reset signal enables the Trusted Platform Control Module to gain control of the SPI1 bus of the storage module. The Trusted Platform Control Module then reads the Bootloader from the storage module to perform a trust measurement. After the bootloader passes the measurement, the Trusted Platform Control Module pulls the TPCM reset status signal high, making the processor global reset signal high. The high-level processor global reset signal causes the embedded processor to enter a warm-start state. At the same time, the high-level processor global reset signal enables the embedded processor to gain control of the SPI1 bus of the storage module. At this point, the warm-start measurement ends.

11. The control method for an embedded platform TPCM access system according to claim 10, characterized in that: The reset start control signal is low level, including: When the watchdog kick signal is interrupted, the watchdog timer overflows, and the restart control signal is set to a low level; or when the embedded processor pulls down the watchdog manual reset control signal according to the application requirements, the restart control signal is set to a low level.

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