Method and apparatus for hybrid parallel programming of single-level cell memory

Abstract

This application relates to hybrid parallel programming of single-level cell memory. A memory device includes a page buffer having a cache register and a data register, a memory array having a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including causing a first page of SLC data to be stored in the cache register, causing the first page of the SLC data to be moved from the cache register to a first data register, causing a subsequent page of the SLC data to be stored in the cache register, causing the SLC data stored in the cache register and the SLC data stored in the data register to be programmed concurrently to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block, and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to hybrid parallel programming of single-level cell (SLC) memories. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a memory device comprising: a page buffer including a cache register and a plurality of data registers; a memory array including a set of sub-blocks coupled to the page buffer, wherein the sub-blocks include memory cells configured as single-level cell (SLC) memory; and control logic operably coupled to the page buffer, the control logic performing operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register among the plurality of data registers; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and the SLC data stored in the plurality of data registers to be simultaneously programmed into the sub-blocks, wherein the first page is programmed into a first sub-block and the subsequent page is programmed into a subsequent sub-block in the sub-blocks set; and causing a subset of the operations for programming the sub-blocks to be performed in parallel.

[0004] Another aspect of this disclosure provides a method comprising: causing, via control logic coupled to a page buffer and a sub-block set in a memory array, a first page of single-level cell (SLC) data to be stored in a cache register of the page buffer, wherein the sub-block set includes memory cells configured as SLC memory; causing, via the control logic, the first page of the SLC data to be moved from the cache register to a first data register among a plurality of data registers of the page buffer; causing, via the control logic, a subsequent page of the SLC data to be stored in the cache register; causing, via the control logic, the SLC data stored in the cache register and the SLC data stored in the plurality of data registers to be simultaneously programmed into the sub-block set, wherein the first page is programmed into a first sub-block and the subsequent page is programmed into a subsequent sub-block in the sub-block set; and causing, via the control logic, a subset of operations for programming the sub-block set to be performed in parallel.

[0005] Another aspect of this disclosure provides a method comprising: causing multiple pages of single-level cell (SLC) data to be sequentially stored in a cache register of the page buffer via control logic coupled to a page buffer and a sub-block set in a memory array, wherein the sub-block set includes memory cells configured as SLC memory; causing the multiple pages to be sequentially moved from the cache register to corresponding data registers in a plurality of data registers of the page buffer via the control logic, while retaining the last page of the multiple pages in the cache register; causing the multiple pages of the SLC data stored in the combination of the cache register and the plurality of data registers via the control logic to be simultaneously programmed to the sub-block set, wherein corresponding pages of the multiple pages will be programmed to each corresponding sub-block in the sub-block set; and causing a subset of operations for programming the sub-block set to be executed in parallel via the control logic. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a schematic diagram of two segments of a memory cell array comprising four sub-blocks, according to at least some embodiments.

[0011] Figure 4A This is a block diagram illustrating a memory subsystem with a page buffer according to some embodiments of the present disclosure, the page buffer including registers from which a set of sub-blocks of a memory array programmed to be configured as a single-level cell (SLC) memory.

[0012] Figure 4B This is a block diagram illustrating hybrid parallel programming of an SLC unit according to some embodiments of the present disclosure.

[0013] Figure 5 This is a flowchart of an example method for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure.

[0014] Figure 6This is a flowchart of an example method for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure.

[0015] Figure 7 This is a flowchart of an example method for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure.

[0016] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0017] This disclosure relates to hybrid parallel programming of single-level cell (SLC) memory. In certain memory devices that include non-volatile memory devices (e.g., NAND flash memory devices), system performance requirements are becoming increasingly aggressive, such as the need for short-duration programming to and reading from NAND flash cells of the memory device (tProg). Therefore, these memory devices tend to include portions of the NAND array that can be used as SLC caches, in which SLC data is programmed (and read from) before being transferred to multi-level cell (MLC) memory (e.g., three-level cell (TLC), four-level cell (QLC), or five-level cell (PLC) memory), referencing… Figure 1A To elaborate further. SLC memory programming and reading times are faster than TLC and significantly faster than high-order MLC memory such as QLC and PLC. However, in these memory devices, each programming cycle utilizes the control logic on the memory device to perform the same series of operations to program each SLC page, thus causing unwanted performance delays as each page is programmed sequentially.

[0018] This disclosure addresses the above and other drawbacks of programming to SLC memory by causing a plurality of pages of SLC data to be stored in a cache register and one or more data registers of a page buffer via a local media controller (e.g., control logic) of the memory device, the memory device being coupled to a sub-block set configured as SLC memory. In various embodiments, at least one of the plurality of pages of SLC data is moved from a cache register to a corresponding data register of the page buffer. In some embodiments, the plurality of pages comprises four pages, and three of the four pages are moved to different data registers, while the fourth of the four pages remains in the cache register, to establish the capability to perform hybrid parallel programming operations on the sub-block set. In these embodiments, the control logic further causes the SLC data in the cache register and the SLC data in one or more data registers to be simultaneously programmed to the sub-block set, wherein a corresponding page of the plurality of pages is programmed to each corresponding sub-block in the sub-block set.

[0019] In at least some embodiments, the control logic can then significantly improve programming performance by simultaneously causing a subset of operations for programming a subset of blocks from the page buffer to be executed in parallel. As an example, the subset of operations includes causing charge pump initialization of the subset, causing programming verification initialization of the subset, and causing bit lines and word lines to be discharged during a voltage recovery phase. The subset of operations may also include selecting one or more bit lines not to participate in programming.

[0020] The advantages of this method include, but are not limited to, improved performance of the memory subsystem. In the manner described herein, this performance improvement can reduce SLC memory programming time by at least one-third. With improved programming time, read operations can be completed more quickly. For example, some read operations must wait for the data to be read to be fully programmed into the memory array before the read operation can be completed. These and other advantages, which are obvious to those skilled in the art of memory programming, will be discussed in detail below.

[0021] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0022] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0023] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing power.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1AThis describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can additionally utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in FIG1 is illustrated as including a memory subsystem controller 115, in another embodiment of this disclosure, memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In one embodiment, memory subsystem 110 includes memory interface component 113, which includes cache manager 111. Memory interface component 113 is responsible for handling the interaction between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. In some embodiments, memory subsystem controller 115 includes at least a portion of cache manager 111. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory interface component 113 is part of host system 120, an application, or an operating system. In one embodiment, memory interface 113 includes cache manager 111 and other subcomponents. The cache manager 111 can direct memory access commands (such as read commands, cache read commands, snapshot read commands, cache read context switch commands, or cache reach context restore commands) to the memory device 130.

[0040] In one embodiment, the local media controller 135 includes a parallel programmer 138, and the memory device 130 includes page buffers 152 among a plurality of page buffers for temporarily storing (e.g., buffering) data when data is programmed to or read from memory cells of the memory device 130. In these embodiments, the parallel programmer 138 can direct programming operations that program data stored in page buffers 152 to a sub-block set of the SLC memory array of the memory device 130. For example, the parallel programmer 138 can cause SLC data of multiple pages to be sequentially stored in cache registers and sequentially moved to data registers in a plurality of data registers of page buffers 152, while pages of the multiple pages remain in the cache registers. The parallel programmer 138 can further cause SLC data stored in the combination of cache registers and a plurality of data registers to be simultaneously programmed to the sub-block set, wherein a corresponding page of the multiple pages will be programmed to each corresponding sub-block in the sub-block set. Additionally, the parallel programmer 138 can cause a subset of operations for programming the sub-block set to be performed in parallel. The following describes additional details regarding the operation of the cache manager 111 and the parallel programmer 138.

[0041] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0042] Memory device 130 includes an array 150 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 150 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0043] In some embodiments, the memory cell array 150 includes a portion consisting of memory cells configured as SLC memory, namely the SLC cache 145, which, for example and therefore includes the sub-block set referenced herein. In some embodiments, the SLC cache 145 represents a relatively small percentage of the entire memory cell array 150, for example, a percentage between 5% and 15% in some embodiments. The initial programming is performed more quickly, attributable to the faster execution of programming to SLC memory, when the local media controller 135 can first bootstrap programming into the SLC cache 145. The local media controller 135 can then arrange to compress the SLC data for subsequent programming into the remaining portion of the memory cell array 150, which may contain some other MLC memory type.

[0044] Row decoding circuitry 108 and column decoding circuitry 121 are provided to decode address signals. Address signals are received and decoded to access memory cell array 150. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 121 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0045] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 150 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 150. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 121 to control them in response to addresses. In one embodiment, the local media controller 135 includes a parallel programmer 138 capable of performing hybrid parallel programming of the SLC memory of memory device 130, as described herein.

[0046] The local media controller 135 also communicates with cache register 142. Cache register 142 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 150 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 142 to data register 144 for transmission to the memory cell array 150; then, new data can be latched from I / O control circuitry 112 into cache register 142. During read operations, data can be transferred from cache register 142 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 144 to cache register 142. Cache register 142 and / or data register 144 may form a page buffer 152 of memory device 130 (e.g., a portion thereof). Page buffer 152 may additionally include sensing devices ( Figure 1B (Not shown in the image), it is used to sense the data status of the memory cells of the memory cell array 150, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry system 112 and the local media controller 135 to latch status information for output to the memory subsystem controller 115.

[0047] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0048] For example, commands can be received at I / O control circuitry system 112 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry system 112 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 142. The data can then be written to data register 144 for programming memory cell array 150.

[0049] In this embodiment, cache register 142 may be omitted, and data may be written directly to data register 144. Data may also be output on input / output (I / O) pins [7:0] for 8-bit devices or on input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0050] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0051] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of an array 200A of memory cells in a memory of the described type, said portion including, for example, an SLC cache 145. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to... Figure 2 Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0052] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M One of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain transistor)). Select transistors 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select transistors 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0053] The source of each select gate 210 can be connected to the common source 216 or the SRC. The drain of each select gate 210 can be connected to the memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0054] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0055] Figure 2 The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0056] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236, such as... Figure 2 As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0057] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202...N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0058] Although Figure 2 Bit lines 2043-2045 are not explicitly depicted in the figure, but it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0059] Figure 3 This is a schematic diagram of two segments of a memory cell array 300A comprising four sub-blocks, according to at least some embodiments. In some embodiments, the memory cell array 300A is included in an SLC cache 145 of the memory device 130. For example, in a segmented SGS (or SSGS) architecture, strings of memory cells may be divided into sub-blocks, wherein in some embodiments, each SGS segment contains two sub-blocks. A first (e.g., selected) SGS segment may include a first sub-block 3050 and a second sub-block 3051. A second (e.g., unselected) SGS segment may include a third sub-block 3052 and a fourth sub-block 3053. In other embodiments, other numbers of sub-blocks may be included in the segment.

[0060] Specifically, in at least some embodiments, Figure 3 The memory cell array 300A includes bit lines 304, with each sub-block coupled to bit lines 304. A first sub-block 3050 (for simplicity, assumed to be a selected sub-block) may include a first drain-select (SGD) transistor 3120, a first source-select (SGS) transistor 3100, and a first memory cell string 3060 coupled therebetween. A second sub-block 3051 may include a second SGD transistor 3121, a second SGS transistor 3101, and a second memory cell string 3061 coupled therebetween. A third sub-block 3052 may include a third SGD transistor 3122, a third SGS transistor 3102, and a third memory cell string 3062 coupled therebetween. A fourth sub-block 3053 may include a fourth SGD transistor 3123, a fourth SGS transistor 3103, and a fourth memory cell string 3063 coupled therebetween. By way of example, the third memory cell string 3062 contained in the unselected SGS fragment contains multiple memory cells 3080…308. N Each SGS transistor can be connected to a common source (SRC), such as a source voltage line, to provide voltage to multiple memory cells 3080…308. N The source. In some embodiments, the source voltage line includes a source plate supplying the source voltage. In at least some embodiments, a plurality of word lines (WL) are coupled to the gate of the memory cell of each memory cell string 3060…3063. Each memory cell string includes a channel (not shown) coupled between the SGS transistor and the SGD transistor of the sub-block.

[0061] In these embodiments, a first drain-select gate line (SGD0) can be connected to the gate of a first SGD transistor 3120, a second drain-select gate line (SGD1) can be connected to the gate of a second SGD transistor 3121, a third drain-select gate line (SGD2) can be connected to the gate of a third SGD transistor 3122, and a fourth drain-select gate line (SGD3) can be connected to the gate of a fourth SGD transistor 3123. Additionally, a first source-select gate line (SGS0) can be connected to the gates of a first SGS transistor 3100 and a second SGS transistor 3101. Furthermore, a second source-select gate line (SGS1) can be connected to the gates of a third SGS transistor 3102 and a fourth SGS transistor 3103. Therefore, the source voltage of each memory cell string can be jointly controlled by a separate segment of source-select gate lines (SGS0 or SGS1), wherein the first segment is a combination of a first sub-block 3050 and a second sub-block 3051, and the second segment is a combination of a third sub-block 3052 and a fourth sub-block 3053.

[0062] Figure 4A This is a block diagram illustrating a memory subsystem 430 with a page buffer according to some embodiments of the present disclosure. The page buffer includes registers from which a subset of blocks of a memory array configured as a single-level cell (SLC) memory is programmed. In one embodiment, a memory interface 113 is operatively coupled to a memory device 130. In one embodiment, the memory device 130 includes a page buffer 152 and a memory array 150. The memory array 150 may include word lines formed, for example, on word line 452 and, for example, on... Figure 2 and Figure 3 The 204 mentioned in the document M Or an array of memory cells at the intersection of 304 bit lines. As discussed, these memory cells can be configured as SLC memory and are therefore contained within SLC cache 145.

[0063] In one embodiment, memory cells are grouped into blocks, which can be further divided into sub-blocks, where a given word line, for example, word line 452, is shared across multiple sub-blocks 4050, 4051, 4052, 4053. In one embodiment, each sub-block corresponds to a separate plane in memory array 150. A group of memory cells associated with a word line within a sub-block is called a physical page. Each physical page in one of the sub-blocks can be one of several page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). Multi-level cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types are LP, UP, and additional logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). In some embodiments, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data different from the data stored in other logical pages associated with that physical page.

[0064] Depending on the programming scheme used, each logical page of the memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP can be programmed in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are also possible. Page buffer 152 is used to temporarily store data being read from or written to the memory array 150 of memory device 130, and may include cache register 442 and one or more data registers 4440-444. N For read operations, data is read from memory array 150 into data registers 4440-444. NThe data is then read from one of the registers and then into cache register 442. Memory interface 113 can then read data from cache register 442. For programming operations, memory interface 113 writes data to cache register 442 and then transfers it to data registers 4440-444. N One of the pages is then programmed into memory array 250. If the programming operation involves multiple pages (e.g., UP, XP, and TP), each page may have a dedicated data register to store the data for that page. (See reference...) Figure 4B and Figure 5-7 The functionality of the parallel programmer 138 shown in Figure 1 will be discussed in more detail.

[0065] Figure 4B This is a block diagram illustrating hybrid parallel programming of an SLC cell according to some embodiments of the present disclosure. In at least some embodiments, the control logic of a parallel programmer 138, such as a local media controller 135, guides the hybrid parallel programming described herein. As discussed, the SLC cache 145 of the memory array 150 may include several sub-blocks, such as a first sub-block 4050, a second sub-block 4051, a third sub-block 4052, and a fourth sub-block 4053.

[0066] In these embodiments, the local media controller 135 sequentially stores (or buffers) multiple (e.g., four) pages of SLC data into cache register 442. Dashed lines indicate that each page (e.g., page 1, page 2, page 3, page 4) is sequentially stored into cache register 442 one at a time. In some embodiments, the parallel programmer 138 also directs this buffering step. In at least some embodiments, the parallel programmer 138 sequentially causes the first, second, and third pages of the four pages to be moved sequentially from cache register 442 to data registers 4440-444 of page buffer 152. N The corresponding data registers in the cache. For example, in at least one embodiment, the control logic moves page 3 from cache register 442 to the first data register 4440, then moves page 2 from cache register 442 to the second data register 4441, and then moves page 1 from cache register 442 to the third data register 4442. In these embodiments, the parallel programmer 138 further causes the fourth page (page 4) of the four pages to remain in cache register 442.

[0067] In various embodiments, once data registers 4440-444... NContaining one or more of three pages, the parallel programmer 138 can cause the four pages of SLC data to be programmed into corresponding sub-blocks in the sub-block set of the SLC cache 145. For example, the first page in the third data register 4442 can be programmed into the first sub-block 4050, the second page in the second data register 4441 can be programmed into the second sub-block 4051, the third page in the first data register 4440 can be programmed into the third sub-block 4052, and the fourth page held in the cache register 442 can be programmed into the fourth sub-block 4053.

[0068] In at least some embodiments, memory device 130 is configured to perform cache programming, for example, using a page cache programming command (80h-15h). Cache programming enables host system 120 to input data into cache register 442, and local media controller 135 can then cause the data to be moved to data registers 4440-444. N This then causes data registers 4440-444 to... N The data is programmed into memory array 150. A subsequent programming step may involve programming the data into specified blocks and page addresses within the memory array 150 of the selected die. In this way, host system 120 can directly access SLC cache 145 for host system purposes.

[0069] In the cache programming implementation, a single-page cache operation can be initiated during the cache busy time (RDY=1 and ARDY=0). Following the single-page cache operation, data is not transferred from cache register 442 to data registers 4440-444. N This continues until the ongoing cache programming operation is complete (RDY=1 and ARDY=1). Data is copied to data registers 4440-444. N Subsequently, cache register 442 can be used for additional programming page cache commands. When the die is ready, the host system 120 checks the fail bit to verify that the operation has been successfully completed.

[0070] In at least some cache programming embodiments, only the first data register 4440 is available to move data buffered in cache register 442, for example, making other data registers 4441-444... N The local media controller 135 can continue to provide non-cacheable programming for the memory device 130. Therefore, the embodiment described above with reference to a single hybrid parallel programming of four pages is reduced to hybrid parallel programming of two pages, such as pages 3 and 4 described within cache register 442, programming to two sub-blocks of the SLC cache 145. Therefore, the embodiment described above and referenced... Figure 5 The operation described in more detail involves two pages of SLC data.

[0071] Figure 5 This is a flowchart of an example method 500 for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, as shown in FIG1- Figure 3 The parallel programmer 138 executes method 500. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0072] like Figure 5 As illustrated in the diagram, dashed lines indicate operations performed in parallel, solid lines indicate operations performed serially, and dotted dashed lines indicate optional operations that are also performed serially (when performing non-cache programming). Therefore, when multiple pages of SLC data are programmed into a subset of blocks of the SLC cache 145, subsets of operations, including operations 505, 510, 535, and 550, can be performed in parallel. Additionally, operations 515C, 515D, 540C, and 540D are not performed when cache programming is performed, and the remainder of these operations are therefore applied only to two sub-blocks. The ability to perform subsets of operations in parallel utilizes the execution of operations that program across multiple pages, for example, at least two pages of SLC data for cache programming and four pages of SLC data for non-cache programming. For non-cache programming, this results in a performance improvement in reducing programming time (tProg) by at least one-third less programming time than the normal programming time where each page of data is programmed individually without parallelism.

[0073] At operation 505, a start operation is performed. More specifically, the processing logic performs the start operation to begin the programming operation, which includes causing a charge pump and other analog hardware initializations to be performed on the sub-block set. The charge pump will cause the bit lines, word lines, and source voltage lines to ramp up to the target voltage that can be used for programming.

[0074] At operation 510, a seed operation is performed. For example, the processing device performs a seed operation on a set of sub-blocks in memory array 150. This seed operation includes, for example, selecting one or more bit lines that are not involved in programming, such as those located in the unselected sub-blocks.

[0075] At operations 515A, 515B, 515C, and 515D, individual sub-block programming is performed. More specifically, the processing logic serially programs a first sub-block 4050 (SB0) with a first page from page buffer 152, a second sub-block 4051 (SB1) with a second page from page buffer 152, a third sub-block 4052 (SB2) with a third page from page buffer 152, and a fourth sub-block 4053 (SB3) with a fourth page from page buffer 152.

[0076] Because the programming of the sub-block is repeated serially four times, only a single set of programming operations is described for the actual writing to the SLC cache 145. For example, at operation 520, the selected bit line and source voltage line (e.g., SRC) are prepared. For example, the processing logic causes the selected bit line and selected source voltage line to be charged to a target voltage to prepare for programming the sub-block coupled between the selected bit line and the selected source voltage line. The processing logic also causes the voltages to the select gate line and select source line to be ramped up to predetermined voltages to turn on the SGD transistor and SGS transistor, respectively.

[0077] At operation 525, the programming pulse is activated. For example, the processing logic causes the unselected word lines of the sub-block to be swashed to the pass voltage and causes the selected word lines of the sub-block to be charged to the programming voltage by providing the programming pulse.

[0078] At operation 530, a pulse clear is performed. For example, the processing logic causes the memory array to exit the high-voltage programming phase by discharging the word lines of the previously applied voltage. In this way, the memory array is prepared to have the correct verification voltage applied during the programming verification operation. It should be noted that each of operations 520, 525, and 530 is repeated for each additional subblock of the SLC cache 145 that is programmed.

[0079] At operation 535, programming verification initialization is performed. For example, the processing logic causes programming verification initialization to be performed on a subset of blocks. This type of programming verification initialization may include determining which memory cells are fully programmed and which memory cells require at least one programming pulse.

[0080] At operations 540A, 540B, 540C, and 540D, a programmable verification sensing operation is performed on the sub-block set. For example, the processing logic causes a programmable verification sensing operation to be performed on one or more memory cells of the sub-block, with selected word lines connected to the sub-block for each of these operations. More specifically, at operation 540A, the processing logic causes a sensing operation to be performed on the first sub-block 4050 (SB0). At operation 540B, the processing logic causes a sensing operation to be performed on the second sub-block 4051 (SB1). At operation 540C, the processing logic causes a sensing operation to be performed on the third sub-block 4052 (SB2). At operation 540D, the processing logic causes a sensing operation to be performed on the fourth sub-block 4053 (SB3).

[0081] At operation 550, voltage recovery is performed. For example, the processing logic discharges the bit lines and word lines during the voltage recovery phase, preparing the memory array for another memory operation. After the voltage recovery phase, method 500 can loop back to operation 510 to continue additional programming of additional page sets of SLC data.

[0082] Figure 6 This is a flowchart of an example method 600 for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure. Method 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, through FIG1- Figure 3 The parallel programmer 138 executes method 600. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0083] At operation 610, the SLC data is buffered in a cache register. For example, the processing logic causes multiple pages of Single Level Cell (SLC) data to be stored sequentially, one page at a time, in the cache register of the page buffer.

[0084] At operation 620, some SLC data is moved to the data register. For example, the processing logic causes multiple pages to be sequentially moved from the cache register to their respective data registers in the page buffer, while the last page of the multiple pages remains in the cache register. (See reference) Figure 4BThis section discusses in detail how individual pages of data terminate buffering across cache registers and multiple data registers.

[0085] At operation 630, SLC data is programmed. For example, the processing logic causes multiple pages of SLC data stored in a combination of cache registers and multiple data registers to be simultaneously programmed into a sub-block set containing memory cells configured as SLC memory. Relevant pages from the multiple pages will be programmed into each corresponding sub-block within the sub-block set. This sub-block set may reside in a memory array within the SLC cache 145 of memory device 130. Figure 4B ).

[0086] At operation 640, programming is performed in partial parallelism. For example, the processing logic causes a subset of operations used for programming sub-blocks to be executed in parallel. See reference... Figure 5 The subset of such programming operations discussed may include causing charge pump initialization of the sub-block set; selecting one or more bit lines not to participate in programming; causing programming verification initialization of the sub-block set; and causing the bit lines and word lines to discharge during the voltage recovery phase.

[0087] Figure 7 This is a flowchart of an example method 700 for hybrid parallel programming of an SLC memory according to some embodiments of the present disclosure. The method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, through FIG1- Figure 3 The parallel programmer 138 executes method 700. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0088] At operation 710, SLC data is buffered. For example, the processing logic causes the first page of Single Level Cell (SLC) data to be stored in the cache register of the page buffer.

[0089] At operation 720, SLC data is moved within the page buffer. For example, the processing logic causes the first page of SLC data to be moved from the cache register to the first data register among the multiple data registers in the page buffer.

[0090] At operation 730, more SLC data is buffered. For example, the processing logic causes the next page of SLC data to be stored in a cache register. (See reference) Figure 4B This section discusses in detail how individual pages of data terminate buffering across cache registers and multiple data registers.

[0091] At operation 740, SLC data is programmed. For example, the processing logic causes SLC data stored in a cache register and SLC data stored in multiple data registers to be simultaneously programmed into a sub-block set containing memory cells configured as SLC memory. For example, the first page is programmed into the first sub-block, and subsequent pages are programmed into the next sub-block in the sub-block set. Relevant pages from multiple pages will be programmed into each corresponding sub-block in the sub-block set, as shown in the reference. Figure 4B The discussion.

[0092] At operation 750, programming is performed in partial parallelism. For example, the processing logic causes a subset of operations used for programming sub-blocks to be executed in parallel. See reference... Figure 5 The subset of such programming operations discussed may include causing charge pump initialization of the sub-block set; selecting one or more bit lines not to participate in programming; causing programming verification initialization of the sub-block set; and causing the bit lines and word lines to discharge during the voltage recovery phase.

[0093] In at least one cache programming embodiment, the sub-block set comprises two sub-blocks of the SLC cache, the latter being the second page of two pages of SLC data, and causing the simultaneous programming of SLC data stored in the cache register and SLC data stored in multiple data registers into the sub-block set involves cache programming.

[0094] In at least one non-cached programming embodiment, the sub-block set comprises four sub-blocks of the SLC cache, the SLC data comprises four pages, and the last page is the fourth page of the four pages. In these embodiments, operations 710 and 720 may additionally include processing logic causing a second page of the SLC data to be stored in a cache register; causing the second page of the SLC data to be moved from the cache register to a second data register among a plurality of data registers; causing a third page of the SLC data to be stored in a cache register; and causing the third page of the SLC data to be moved from the cache register to a third data register among a plurality of data registers. In at least one non-cached programming embodiment, operation 730 may additionally include processing logic causing the second page to be programmed into a second sub-block in the sub-block set and causing the third page to be programmed into a third sub-block in the sub-block set. In this embodiment, the last sub-block is the fourth sub-block in the sub-block set.

[0095] Figure 8An example machine illustrating computer system 800 is described, capable of executing a set of instructions within said computer system 800 to cause said machine to perform any or more of the methods discussed herein. In some embodiments, computer system 800 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1A (Operation of the cache manager 111 and / or parallel programmer 138). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0096] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0097] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0098] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. Computer system 800 may additionally include a network interface device 808 for communication on network 820.

[0099] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more instruction sets 826 or software embodying any or more of the methods or functions described herein are stored. The instructions 826 may also reside wholly or at least partially in main memory 804 and / or processing device 802 during execution by computer system 800, which also constitute machine-readable storage media. The machine-readable medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 1A The memory subsystem 110.

[0100] In one embodiment, instruction 826 includes implementing the corresponding Figure 1A The cache manager 111 and / or parallel programmer 138 provide functional instructions. Although the machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0101] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0102] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0103] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0104] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0105] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0106] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: a page buffer comprising a cache register and a plurality of data registers; a memory array comprising a set of sub-blocks coupled with the page buffer, wherein the set of sub-blocks comprises memory cells configured as single level cell (SLC) memory; and control logic operatively coupled with the page buffer, the control logic performing operations comprising: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register of the plurality of data registers; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be programmed to the set of sub-blocks concurrently, wherein the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block in the set of sub-blocks; and causing the operations for programming the set of sub-blocks to be performed in parallel.

2. The memory device of claim 1, wherein the set of sub-blocks comprises four sub-blocks of SLC cache and the SLC data comprises four pages.

3. The memory device of claim 2, wherein the subsequent page is a fourth page of the four pages, and wherein the operations further comprise: causing a second page of the SLC data to be stored in the cache register; causing the second page of the SLC data to be moved from the cache register to a second data register of the plurality of data registers; causing a third page of the SLC data to be stored in the cache register; and causing the third page of the SLC data to be moved from the cache register to a third data register of the plurality of data registers.

4. The memory device of claim 3, wherein causing the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be programmed to the set of sub-blocks further comprises: causing the second page to be programmed to a second sub-block in the set of sub-blocks; causing the third page to be programmed to a third sub-block in the set of sub-blocks; and wherein the subsequent sub-block is a fourth sub-block in the set of sub-blocks.

5. The memory device of claim 1, wherein the set of sub-blocks comprises two sub-blocks of SLC cache, the subsequent page is a second page of two-page SLC data, and wherein causing the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be programmed to the set of sub-blocks comprises cache programming.

6. The memory device of claim 1, wherein the operations for programming the set of sub-blocks further comprise: causing charge pump initialization to be performed on the set of sub-blocks; causing programming verify initialization to be performed on the set of sub-blocks; and causing bit lines and word lines to be discharged during a voltage recovery phase. ​ ​ ​ 7. The memory device of claim 6, wherein the operations to program the set of sub-blocks further comprise selecting one or more bit lines that are not to participate in programming.

8. The memory device of claim 6, wherein the operations further comprise: causing the selected bit line and the selected source voltage line to be charged to a target voltage in preparation for programming a sub-block coupled between the selected bit line and the selected source voltage line; and causing voltages to a select gate line and a select source line to ramp to predetermined voltages, respectively.

9. The memory device of claim 6, wherein the operations further comprise serially performing the following operations for each sub-block in the set of sub-blocks: causing unselected word lines of the sub-block to ramp to a pass voltage; causing a selected word line of the sub-block to be charged to a program voltage; and causing a program verify sense operation to be performed on one or more memory cells of the sub-block connected to the selected word line.

10. A method comprising: causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, a first page of single level cell (SLC) data to be stored in a cache register of the page buffer, wherein the set of sub-blocks comprises memory cells configured as SLC memory; causing, by the control logic, the first page of SLC data to be moved from the cache register to a first data register of a plurality of data registers of the page buffer; causing, by the control logic, a subsequent page of SLC data to be stored in the cache register; causing, by the control logic, the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be programmed simultaneously to the set of sub-blocks, wherein the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block in the set of sub-blocks; and causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel.

11. The method of claim 10, wherein the set of sub-blocks comprises four sub-blocks of an SLC cache and the SLC data comprises four pages.

12. The method of claim 11, wherein the subsequent page is a fourth page of the four pages, the method further comprising: causing a second page of SLC data to be stored in the cache register; causing the second page of SLC data to be moved from the cache register to a second data register of the plurality of data registers; causing a third page of SLC data to be stored in the cache register; and causing the third page of SLC data to be moved from the cache register to a third data register of the plurality of data registers.

13. The method of claim 12, wherein causing the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be programmed simultaneously to the set of sub-blocks further comprises: causing the second page to be programmed to a second sub-block in the set of sub-blocks; ​ causing the third page to be programmed to a third sub-block of the set of sub-blocks; and wherein the latter sub-block is a fourth sub-block of the set of sub-blocks.

14. The method of claim 10, wherein the set of sub-blocks comprises two sub-blocks of an SLC cache, the latter page is a second page of two pages of SLC data, and wherein causing the SLC data stored in the cache register and the SLC data stored in the first data register of the plurality of data registers to be simultaneously programmed to the set of sub-blocks comprises cache programming.

15. The method of claim 10, wherein the operations for programming the set of sub-blocks further comprise: causing charge pump initialization to be performed on the set of sub-blocks; causing programming verify initialization to be performed on the set of sub-blocks; and causing bit lines and word lines to be discharged during a voltage recovery phase.

16. The method of claim 15, wherein the operations for programming the set of sub-blocks further comprise selecting one or more bit lines that are not to participate in programming.

17. The method of claim 15, further comprising: causing selected bit lines and selected source voltage lines to be charged to a target voltage in preparation for programming a sub-block coupled between the selected bit lines and the selected source voltage lines; and causing voltages to a select gate line and a select source line to ramp to predetermined voltages, respectively.

18. The method of claim 15, further comprising serially performing the following operations for each sub-block of the set of sub-blocks: causing unselected word lines of the sub-block to ramp to a pass voltage; causing a selected word line of the sub-block to be charged to a program voltage; and causing a program verify sense operation to be performed on one or more memory cells of the sub-block connected to the selected word line.

19. A method comprising: causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, a plurality of pages of single level cell (SLC) data to be sequentially stored in a cache register of the page buffer, wherein the set of sub-blocks comprises memory cells configured as SLC memory; causing, by the control logic, the plurality of pages to be sequentially moved from the cache register to respective data registers of a plurality of data registers of the page buffer while a last page of the plurality of pages is maintained in the cache register; causing, by the control logic, the plurality of pages of SLC data stored in the cache register and the combination of the plurality of data registers to be simultaneously programmed to the set of sub-blocks, wherein respective pages of the plurality of pages are to be programmed to each respective sub-block of the set of sub-blocks; and causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel.

20. The method of claim 19, wherein the set of sub-blocks comprises four sub-blocks of an SLC cache, the plurality of pages comprises four pages of SLC data, and wherein a first, second, and third page of the four pages are stored in the plurality of data registers while a fourth page of the four pages is maintained in the cache register.

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