Packaging method and package body for packaging motherboard and chip

Abstract

The present application discloses a packaging method and packaging body for a packaging motherboard and a chip. The packaging motherboard includes a chip, a carrier board, a first plastic package and a conductive member; the first metal layer includes a plurality of first pads, the second metal layer includes a plurality of second pads, and the first pads are electrically connected to the second pads; a chip is fixed on each first pad, and a second blind hole is set in a preset area between two adjacent chips; each second blind hole is used to connect the conductive members on both sides to the second metal layer, or each second blind hole is used to connect the conductive member on one side to the second metal layer, and also to connect the first pad on the other side to the second metal layer. The above-mentioned packaging motherboard and the shared design of the second blind hole, on the one hand, can transfer the pins of each chip through half a blind hole, saving the occupied volume and enabling the packaging of large-sized chips; on the other hand, it reduces the number of second blind holes produced, which is conducive to improving processing efficiency.

Description

Technical Field

[0001] The present application relates to the field of device packaging technology, and in particular to a packaging method for a packaging motherboard and a chip, and the chip. Background Art

[0002] Encapsulation involves encapsulating multiple electrically connected components within a plastic layer, with the circuit pins extending beyond the layer to facilitate connection to other devices. Encapsulation serves to mount, secure, seal, and protect components, while also enhancing electrical and thermal performance.

[0003] To improve package production efficiency, a package motherboard is first fabricated, and then cut into individual packages. During packaging, the pins on both sides of the chip generally need to be routed to the same pad layer. To achieve this, corresponding plated blind vias (PVBs) are fabricated in the motherboard for each chip in the package area. These PVBs are used to route the pins on the side of the chip away from the pad layer to the pad layer. The need for a separate PVB for each chip reduces processing efficiency and occupies a large amount of space, making it difficult to package large chips. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a packaging method and packaging body for a packaging motherboard and a chip to solve the above problems.

[0005] In order to solve the above technical problems, the first technical solution adopted in this application is to provide a packaging motherboard, which includes: a chip, a carrier board, the carrier board includes a first metal layer, a dielectric layer, and a second metal layer stacked in sequence; the first metal layer includes a plurality of first pads, and the second metal layer includes a plurality of second pads electrically connected to the first pads, wherein a chip is fixed on each first pad; a first plastic package, the first plastic package covers each chip and the first pads; wherein the first plastic package is formed with a plurality of metallized first blind holes and second blind holes with metallized hole walls, and the second blind holes are arranged in a preset area between two adjacent chips; a conductive member, one end of the conductive member is connected to the chip through the metallized first blind hole, and the other end of the conductive member is connected to the second metal layer through the metallized second blind hole with metallized hole walls, wherein each second blind hole is used to connect the conductive members on both sides to the second metal layer, or, each second blind hole is used to connect the conductive member on one side to the second metal layer, and also used to connect the first pad on the other side to the second metal layer.

[0006] In a possible implementation manner, the further comprising: a second plastic sealing body, the second plastic sealing body being disposed in the second blind hole with the hole wall metallized.

[0007] In order to solve the above technical problems, the second technical solution adopted in the present application is to provide a chip packaging method, including: obtaining a carrier board, the carrier board including a first metal layer, a dielectric layer, and a second metal layer stacked in sequence, making a first pad on the first metal layer, making a second pad on the second metal layer, and electrically connecting the first pad and the second pad; fixing the chip on the first pad and making a first plastic package, wherein the first plastic package is located in the first metal layer and covers the chip and the first pad; making a first blind hole and a second blind hole in the first plastic package, and metalizing the hole wall of the second blind hole and the first blind hole, and the first plastic package is away from the carrier board. A conductive member is provided on one side of the chip, the conductive member is connected to the chip through a metallized first blind hole, and the conductive member is connected to the second metal layer through a metallized hole wall of a second blind hole, wherein a second blind hole is made in a preset area between two adjacent chips, so that the conductive members on both sides of the second blind hole are connected to the second metal layer through the same second blind hole, or the conductive member on one side of the second blind hole is connected to the second metal layer through the second blind hole, and the first pad on the other side of the second blind hole is connected to the second metal layer through the same second blind hole; a second plastic package is made in the second blind hole, and is cut along the busbar of the second blind hole to obtain a single-piece package.

[0008] In a possible embodiment, the steps of making a first pad on the first metal layer and making a second pad on the second metal layer include: performing graphic etching on the first metal layer and the second metal layer respectively to form the first pad on the first metal layer and the second pad on the second metal layer.

[0009] In a possible implementation, the step of fixing the chip on the first pad includes: fixing the chip on the first pad by means of a conductive adhesive, so that the chip is connected to the first pad.

[0010] In one possible embodiment, the steps of forming a first blind hole and a second blind hole in the first plastic package, and metalizing the hole wall of the second blind hole and the first blind hole include: forming the first blind hole in the first plastic package on the side of the chip away from the first pad by laser drilling, and copper depositing the first blind hole, and electroplating it to form a metal filling; forming a second blind hole in a predetermined area between two adjacent chips by laser drilling, and copper depositing the hole wall of the second blind hole, and electroplating it to form a metal filling; wherein the second blind hole passes through the first plastic package and the dielectric layer.

[0011] In a possible implementation, the first plastic package body and the second plastic package body include one or more of epoxy resin, polyimide, bismaleimide triazine, and ceramic matrix.

[0012] In a possible embodiment, before the step of cutting along the busbar of the second blind hole to obtain a single-piece package body, the step further includes: making a third plastic package body on a side of the first plastic package body away from the carrier board, the third plastic package body covering the conductive part, the first blind hole and the second blind hole.

[0013] In a possible embodiment, the chip includes a first surface and a second surface, both of which are provided with pins, and the pins on the first surface are connected to the metallized first blind vias, and the pins on the second surface are connected to the first pads.

[0014] In order to solve the above technical problems, the third technical solution adopted in this application is to provide a package body, which is manufactured by the chip packaging method described in the above embodiment.

[0015] The beneficial effects of the present application are as follows: Different from the prior art, the present application provides a packaging method and packaging body for a packaged motherboard and a chip. The packaged motherboard includes a chip, a carrier, a first plastic package and a conductive member, the carrier includes a first metal layer, a dielectric layer and a second metal layer stacked in sequence; the first metal layer includes a plurality of first solder pads, and the second metal layer includes a plurality of second solder pads electrically connected to the first solder pads; wherein a chip is fixed on each first solder pad; the first plastic package, the first plastic package covering each chip and the first solder pad; wherein the first plastic package is formed with a plurality of metallized first blind holes and second blind holes with metallized hole walls, the second blind holes being arranged in a preset area between two adjacent chips; the conductive member, one end of the conductive member is connected to the chip through the metallized first blind hole, and the other end of the conductive member is connected to the second metal layer through the metallized second blind hole with metallized hole walls, wherein each second blind hole is used to connect the conductive members on both sides to the second metal layer, or each second blind hole is used to connect the conductive member on one side to the second metal layer and also to connect the first solder pad on the other side to the second metal layer. The package motherboard of the present application has a second blind hole set between two adjacent chips, and the second blind hole is shared by the two chips. The conductive parts corresponding to the two adjacent chips are connected to the second metal layer through half of the second blind hole, thereby reducing the number of second blind holes made and improving the processing efficiency of the product. Moreover, each chip realizes the connection between the conductive part and the second metal layer through half of the second blind hole structure. Only one complete second blind hole needs to be set between adjacent chips. The structure for connecting the conductive part and the second metal layer occupies a smaller volume, and the space available for the chip is increased, which is conducive to the packaging of large-size chips. On the other hand, the first inner pad and the second outer pad connected to the chip are not directly contacted and overlapped, but are indirectly connected through metallized holes. The advantage of this structural design is that the first pad and the second pad do not need to be precisely aligned, avoiding the poor connection effect and the risk of falling off caused by the misalignment of the inner and outer pads. The first inner pad is connected to the second outer pad through the metallized hole of the dielectric layer, so that the first pad can be extended and changed in size or position arbitrarily in the first metal layer due to the lack of alignment and deviation restrictions. The first pad is more flexible and improves the platform capability of the package motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a structural diagram of the first embodiment of the packaged motherboard of the present application;

[0018] Figure 2 This is a structural diagram of the second embodiment of the packaged motherboard of the present application;

[0019] Figure 3 This is a schematic structural diagram of the third embodiment of the packaged motherboard of the present application;

[0020] Figure 4 This is a schematic structural diagram of a fourth embodiment of the packaged motherboard of the present application;

[0021] Figure 5 This is a flow chart of an embodiment of a chip packaging method of the present application;

[0022] Figure 6a-6d They are Figure 5 Schematic diagram of the board after each step of the packaging method;

[0023] Figure 7 For Figure 2 Schematic diagram of the structure of a single-piece package body obtained after the package motherboard is cut along the busbar of the second blind hole;

[0024] Figure 8 For Figure 3 Schematic diagram of the structure of a single-piece package body obtained after the package motherboard is cut along the busbar of the second blind hole;

[0025] Figure 9 For Figure 4 Schematic diagram of the structure of a single-piece package body obtained by cutting the package motherboard along the busbar of the second blind hole. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0028] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0029] To obtain the package body, first make a package motherboard, and then cut the package motherboard to obtain individual packages. Each package includes chips and other devices. The pins on both sides of the chip need to be led to the same side through metallized blind holes in the package. Therefore, when making the package motherboard, metallized blind holes need to be made on the side of each chip. The large number of holes affects production efficiency, and each chip is equipped with a blind hole separately. The blind hole occupies a large space, which is not conducive to the packaging of large-size chips.

[0030] Based on the above problems, the present application proposes a packaging motherboard, a chip packaging method and a packaging body. Adjacent chips in the packaging motherboard share metallized blind vias that lead electrodes to the same surface, which can effectively solve the above problems. The packaging motherboard, the chip packaging method and the packaging body provided by the present application are described in detail below in combination with the accompanying drawings and embodiments.

[0031] See also Figure 1 , Figure 1 In a specific embodiment, the package motherboard 100 of the present application includes a chip 101 , a carrier, a first plastic package 106 and a conductive member 108 .

[0032] In the first embodiment, the carrier includes a first metal layer, a dielectric layer 103, and a second metal layer stacked in sequence; the first metal layer includes a plurality of first pads 102, the second metal layer includes a plurality of second pads 104, the dielectric layer 103 is formed with metallized through-holes 105, and each first pad 102 is connected to the second pad 104 through the metallized through-holes 105; wherein each first pad 102 is fixed with a chip 101; a first plastic package 106, the first plastic package 106 covers each chip 101 and the first pad 102 layer; In the embodiment, the first plastic package body 106 is formed with a plurality of metalized first blind vias 107 and second blind vias 109 with metalized hole walls. A second blind via 109 is provided in a predetermined area between each pair of adjacent chips 101. A conductive member 108 is provided, one end of the conductive member 108 being connected to the chip 101 through the metalized first blind via 107, and the other end of the conductive member 108 being connected to the second metal layer through the metalized second blind via 109 with metalized hole walls. The conductive member 108 connecting each pair of adjacent chips 101 is connected to the second metal layer through the same second blind via 109. Specifically, in this embodiment, two chips 101 are provided in the package motherboard 100. In other embodiments, four, six, eight, or other numbers of chips 101 are provided in the package motherboard 100, without specific limitation. In this embodiment, each chip 101 includes pins located on the bottom surface and pins located on the top surface. The pins located on the bottom surface are fixed to the first pads 102 of the first metal layer of the carrier board using a conductive adhesive such as solder paste or silver glue. The first pad 102 is connected to the second pad 104 on the lower surface of the dielectric layer 103 via a metallized through-hole 105 on the dielectric layer 103, thereby leading the pins on the lower surface of the chip 101 to the second metal layer of the carrier. The metallized through-hole 105 in this embodiment is formed by embedding a conductive metal column in the through-hole after forming a through-hole in the dielectric layer 103, so that the two ends of the conductive metal column are respectively connected to the first pad 102 and the second pad 104, thereby realizing the connection between the inner and outer pads. In other embodiments, the metallized through-hole 105 can be formed by copper deposition and electroplating on the through-hole wall after forming a through-hole in the dielectric layer 103, so that the through-hole with metallized wall realizes the connection between the first pad 102 and the second pad 104. The method of metallizing the through-hole is not limited. In this application, the first inner pad 102 and the second outer pad 104 connected to the chip 101 are not directly connected by overlapping contact, but are indirectly connected via a metallized through-hole 105. The advantage of this structural design is that the first pad 102 and the second pad 104 do not need to be precisely aligned, avoiding the poor connection quality and the risk of detachment caused by misalignment of the inner and outer pads. On the other hand, the first inner pad 102 is connected to the second outer pad 104 via the metallized through-hole 105 in the dielectric layer 103. Therefore, since the first pad 102 is not restricted by alignment and deviation, it can be extended and resized or changed in position at will on the first metal layer. This increases the flexibility of the first pad 102 and improves the platform capabilities of the package motherboard 100.

[0033] In order to guide the pins on the upper surface of the chip 101 to the second metal layer, the existing packaging motherboard 100 needs to make metalized blind vias for each chip 101 on the packaging motherboard 101. The number of metalized blind vias required is equal to the number of chips 101 on the motherboard. The production of a large number of metalized blind vias affects the processing efficiency of the product. In addition, the pins of each chip 101 are transferred through complete blind vias, and the blind vias occupy a large space, which is not conducive to the packaging of large-sized chips 101. In this embodiment, one end of the conductive member 108 is connected to the pin on the upper surface of the chip 101 through the metallized first blind via 107, and the other end of the conductive member 108 is connected to the second metal layer through the second blind via 109. Unlike the prior art, in this embodiment, the second blind via 109 is located between two adjacent chips 101, and the conductive members 108 corresponding to the two adjacent chips 101 are connected to the corresponding areas of the second metal layer through the same second blind via 109. It can be understood that the two adjacent chips 101 lead the pins on the upper surface of the chip 101 to the preset area of ​​the second metal layer through the same second blind via 109. This structural design can greatly reduce the number of second blind vias 109 produced on the packaging motherboard 100, thereby improving the processing efficiency of the product. On the other hand, this structural design allows each chip 101 to lead the pins on the upper surface of the chip 101 to the second metal layer through half of the second blind via 109 instead of the complete second blind via 109. The volume occupied by the structure for connecting the conductive member 108 and the second metal layer is reduced, and the space available for the chip 101 is increased, which is beneficial to the packaging of large-size chips 101.

[0034] Different from the prior art, the present application proposes a package motherboard 100 in which a second blind via 109 is provided between two adjacent chips 101. The conductive members 108 corresponding to the two adjacent chips 101 are connected to the second metal layer through the same second blind via 109, thereby reducing the number of second blind vias 109 required and improving product processing efficiency. Furthermore, each chip 101 connects the conductive member 108 to the second metal layer through half of the second blind via 109. This reduces the volume of the structure connecting the conductive member 108 to the second metal layer, increasing the space available for the chip 101 and facilitating the packaging of large-sized chips 101. Furthermore, the first inner pad 102 and the second outer pad 104 connecting the chip 101 are not directly contacted and overlapped, but are indirectly connected via a metallized through-hole 105. This structural design benefits the first pad 102 and the second pad 104 from being precisely aligned, thus avoiding the risk of misalignment and disconnection caused by misalignment of the inner and outer pads. The inner first pad 102 is connected to the outer second pad 104 through the metallized through-hole 105 of the dielectric layer 103, so that the first pad 102 can be extended and changed in size or position at will in the first metal layer due to no alignment or deviation restrictions. The first pad 102 is more flexible, thereby improving the platform capability of the packaging motherboard 100.

[0035] Furthermore, in some other embodiments, the package motherboard 100 further includes a second plastic encapsulation body, which is disposed within the second blind vias 109 having metalized hole walls. Specifically, the advantage of metallizing only the hole walls of the second blind vias 109 and then filling the holes with the second plastic encapsulation body is that, after the package motherboard 100 is cut along the busbars of the second blind vias 109 to obtain individual packages, there is no need to individually plastic encapsulate the metalized hole walls of each package, thereby simplifying the production process and improving processing efficiency.

[0036] It should be noted that in this embodiment, the side walls of the second blind via 109 are shared by the conductive members 108 corresponding to the two chips 101 to connect the conductive members 108 to the second metal layer. In some other embodiments, the side walls of the second blind via 109 are also used for conductive purposes. For example, one side wall is used to connect the conductive member 108 corresponding to the chip 101 to the second metal layer, and the other side wall is used to connect the second metal layer area corresponding to the other chip 101 to other devices. Similarly, the second blind via 109 is divided into two halves, which can be used by the two chips 101 to connect the conductive members 108 to the second metal layer or the second metal layer to other components. Sharing the second blind via 109 reduces the number of second blind vias 109 produced, improves processing efficiency, reduces occupied space, and facilitates the packaging of large-size chips 101.

[0037] See also Figure 2 , Figure 2In another specific embodiment, the package motherboard 300 of the present application includes a chip 301 , a carrier, a first plastic package 306 and a conductive member 308 .

[0038] In the second embodiment, the carrier includes a first metal layer, a dielectric layer 303, and a second metal layer stacked in sequence; the first metal layer includes a plurality of first pads 302, and the second metal layer includes a plurality of second pads 304 electrically connected to the first pads 302, and a chip 301 is fixed on each first pad 302; a first plastic package 306 covers each chip 301 and the first pads 302; wherein the first plastic package 306 is formed with a plurality of metallized first blind holes 307 and second blind holes 309 with metallized hole walls, and the second blind holes 309 are arranged in a preset area between two adjacent chips 301; one end of the conductive member 308 is connected to the chip 301 through the metallized first blind hole 307, and the other end of the conductive member 308 is connected to the second metal layer through the second blind hole 309 with metallized hole walls, wherein each second blind hole 309 is used to connect the conductive member 308 on one side to the second metal layer, and is also used to connect the first pad 302 on the other side to the second metal layer. Similar to the first embodiment, in this embodiment, the second blind vias 309 are also shared by two adjacent chips 301, reducing the number of holes drilled and the volume occupied by the second blind vias 309, thereby improving processing efficiency and enabling the packaging of large chips 301. Unlike the first embodiment, in which the second blind vias 309 were used by the chips 301 on both sides to guide the conductive members 308 to the second metal layer, in this embodiment, the second blind vias 309 are used by the chip 301 on one side to connect the conductive member 308 to the second metal layer and by the chip 301 on the other side to connect the first pads 302 of the chip 301 to the second metal layer. The second blind vias 309 are still shared by both chips 301, achieving the same effect of reducing the number of holes drilled and the volume occupied by the second blind vias 309. When cutting to produce individual packages, the package motherboard 300 is still cut along the busbars of the second blind vias 309 to obtain monolithic packages.

[0039] See also Figure 3 , Figure 3 In another specific embodiment, the package motherboard 400 of the present application includes a chip 401 , a carrier, a first plastic package 406 and a conductive member 408 .

[0040] This embodiment is an improvement on the second embodiment. Unlike the second embodiment, in this embodiment, chips 401 are flip-chip mounted on first pads 402 of the first metal layer. The pins 401 of the chips are connected to the first pads 402 and then lead out through second blind vias 309 to the second pads 404. The other side of the pins is then connected to the second metal layer through conductive members 408 and second blind vias 409. Similar to the previous embodiment, in this embodiment, the second blind vias 409 are shared by two adjacent chips 401, serving to lead the lower pins of one chip 401 to the second pads 404 and the upper surface of the other chip 401 to the second metal layer. This reduces the number of second blind vias 409 required and the volume they occupy, thereby improving processing efficiency and enabling the packaging of large-sized chips 401. When cutting to produce individual packages, the package motherboard 400 is still cut along the busbars of the second blind vias 409 to produce single-piece packages.

[0041] See also Figure 4 , Figure 4 In another specific embodiment, the package motherboard 500 of the present application includes a chip 501 , a carrier, a first plastic package 506 and a conductive member 508 .

[0042] This embodiment is an improvement on the first embodiment. Unlike the first embodiment, in this embodiment, the chips 501 are flip-chip mounted on the first pads 502 of the first metal layer. Similar to the first embodiment, the second blind vias 509 are shared by two adjacent chips 501, serving both to connect the top surface of the chip 501 on one side to the second metal layer and to connect the top surface of the chip 501 on the other side to the second metal layer. This reduces the number of second blind vias 509 required and the volume they occupy, thereby improving processing efficiency and enabling the packaging of large-sized chips 501. When cutting to produce individual packages, the package motherboard 500 is still cut along the busbars of the second blind vias 509 to obtain a single package.

[0043] In summary, the packaging motherboard of the present application mainly reduces the number of second blind holes punched and saves the volume occupied by the second blind holes through the shared design of the second blind holes, thereby realizing the packaging of large-size memory chips and improving processing efficiency. Among them, this design is also applicable to the packaging of flip chips, so that adjacent flip chips share the second blind holes for lead conduction.

[0044] See also Figure 5 and Figure 6a-6d , Figure 5 This is a flow chart of an embodiment of the chip packaging method of the present application. Figure 1 An embodiment of a packaging method for packaging a motherboard. Figure 6a-6d They are Figure 5 Schematic diagram of the board after each step of the packaging method. In a specific embodiment, the packaging method of the present application includes:

[0045] S11: Obtain a carrier board, which includes a first metal layer, a dielectric layer 203, and a second metal layer stacked in sequence. A first pad 202 is formed on the first metal layer, a second pad 204 is formed on the second metal layer, and the first pad 202 and the second pad 204 are electrically connected.

[0046] In this embodiment, a metallized through hole 205 is formed in the dielectric layer 203 , so that the first pad 202 is connected to the second pad 204 through the metallized through hole 205 .

[0047] Specifically, the carrier is a double-sided copper-clad laminate, comprising a first metal layer, a dielectric layer 203, and a second metal layer stacked in sequence. In some embodiments, the steps of forming the first pad 202 on the first metal layer and the second pad 204 on the second metal layer include: performing pattern etching on the first metal layer and the second metal layer, respectively, to form the first pad 202 on the first metal layer and the second pad 204 on the second metal layer. The specific pattern etching process may include: film lamination, exposure, development, and then etching.

[0048] S12 : Fixing the chip 201 on the first pad 202 and making a first plastic package 206 , wherein the first plastic package 206 is located on the first metal layer and covers the chip 201 and the first pad 202 .

[0049] Specifically, after making a first solder pad 202 on the first metal layer of the carrier and a second solder pad 204 on the second metal layer, the pins on one side of the chip 201 are fixed to the first solder pad 202 through conductive glue to connect the chip 201 to the first solder pad 202, where the conductive glue can be silver paste, solder paste, etc., without specific limitation.

[0050] In this embodiment, two chips 201 are provided on the carrier. In other embodiments, four, six, eight, or other numbers of chips 201 may be provided on the carrier, without specific limitation. In this embodiment, each chip 201 includes pins located on the bottom surface and pins located on the top surface. The pins located on the bottom surface are secured to first pads 202 on the first metal layer of the carrier using a conductive adhesive such as solder paste or silver glue. The first pads 202 are connected to second pads 204 on the bottom surface of the dielectric layer 203 via metallized through-holes 205 in the dielectric layer 203, thereby extending the pins on the bottom surface of the chip 201 to the second metal layer of the carrier. Among them, the metallized through hole 205 in this embodiment is formed by burying a conductive metal column in the through hole after making a through hole in the dielectric layer 203, so that the two ends of the conductive metal column are respectively connected to the first pad 202 and the second pad 204, thereby realizing the connection between the inner and outer pads. In other embodiments, the formation of the metallized through hole 205 can be achieved by copper plating and electroplating the through hole wall after making a through hole in the dielectric layer 203, so that the through hole with metallized hole wall realizes the connection between the first pad 202 and the second pad 204. The method of through hole metallization is not limited. In this application, the inner pad first pad 202 and the outer pad second pad 204 connected to the chip 201 are not directly contacted and overlapped, but are indirectly connected through the metallized through hole 205. The advantage of this structural design is that the first pad 202 and the second pad 204 do not need to be precisely aligned, thereby avoiding the poor connection effect and the risk of falling off caused by the misalignment of the inner and outer pads. On the other hand, the inner first pad 202 is connected to the outer second pad 204 through the metallized through-hole 205 of the dielectric layer 203, so that the first pad 202 can be extended and changed in size or position arbitrarily in the first metal layer due to no alignment or deviation restrictions. The first pad 202 is more flexible, which improves the platform capability of the packaging motherboard.

[0051] The first plastic package body 206 may be made of one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic-based materials, and the specific material is not limited here.

[0052] S13: Making a first blind hole 207 and a second blind hole 209 in the first plastic package 206, and metalizing the hole wall of the second blind hole 209 and the first blind hole 207, and setting a conductive member 208 on a side of the first plastic package 206 away from the carrier, the conductive member 208 is connected to the chip 201 through the metalized first blind hole 207, and the conductive member 208 is connected to the second metal layer through the metalized hole wall of the second blind hole 209, wherein a second blind hole 209 is made in a preset area between two adjacent chips 201, so that the conductive members 208 on both sides of the second blind hole 209 are connected to the second metal layer through the same second blind hole 209, or the conductive member 208 on one side of the second blind hole 209 is connected to the second metal layer through the second blind hole 209, and the first pad 207 on the other side of the second blind hole 209 is connected to the second metal layer through the same second blind hole 209.

[0053] In this embodiment, a second blind via 209 is formed in a predetermined area between every two adjacent chips 201, and the conductive member 208 connecting every two adjacent chips 201 is connected to the second metal layer through the same second blind via 209. In other embodiments, the conductive member 208 on one side of the second blind via 209 is connected to the second metal layer through the second blind via 209, and the first pad 207 on the other side of the second blind via 209 is connected to the second metal layer through the same second blind via 209.

[0054] In some embodiments, the steps of forming a first blind via 207 and a second blind via 209 in the first plastic package 206 and metallizing the hole walls of the second blind via 209 and the first blind via 207 include: forming the first blind via 207 in the first plastic package 206 on the side of the chip 201 away from the first pad 202 by laser drilling, depositing copper on the first blind via 207, and then electroplating to form a metal filling; forming a second blind via 209 in a predetermined area between two adjacent chips 201 by laser drilling, depositing copper on the hole walls of the second blind via 209, and then electroplating to form a metal filling; wherein the second blind via 209 passes through the first plastic package 206 and the dielectric layer 203. The chip 201 includes a first surface and a second surface, both of which are provided with pins, with the pins on the first surface connected to the metallized first blind via 207, and the pins on the second surface connected to the first pad 202. Specifically, in this embodiment, the first surface of chip 201 is the top surface of chip 201, and the second surface of chip 201 is the bottom surface of chip 201. Metallization of first blind via 207 can be performed by directly embedding a conductive metal pillar within first blind via 207, or by performing copper deposition or electroplating on the walls of first blind via 207, without specific limitation. Metallization of the walls of second blind via 209 can be performed by copper deposition or electroplating. The purpose of fabricating the metallized first blind via 207 and the metallized second blind via 209 is to connect the pins on the top surface of chip 201 to the second metal layer. In order to guide the pins on the upper surface of the chip 201 to the second metal layer, the existing packaging motherboard needs to make metalized blind holes for each chip 201 on the packaging motherboard. The number of metalized blind holes required is equal to the number of chips 201 on the motherboard. The production of a large number of metalized blind holes affects the processing efficiency of the product. In addition, the pins of each chip 201 are transferred through complete blind holes, and the blind holes occupy a large space, which is not conducive to the packaging of large-sized chips 201. In this embodiment, one end of the conductive member 208 is connected to the pin on the upper surface of the chip 201 through the metallized first blind via 207, and the other end of the conductive member 208 is connected to the second metal layer through the second blind via 209. Unlike the prior art, in this embodiment, the second blind via 209 is located between two adjacent chips 201, and the conductive members 208 corresponding to the two adjacent chips 201 are connected to the corresponding areas of the second metal layer through the same second blind via 209. It can be understood that the two adjacent chips 201 lead the pins on the upper surface of the chip 201 to the preset area of ​​the second metal layer through the same second blind via 209. This structural design can greatly reduce the number of second blind vias 209 produced on the packaging motherboard, thereby improving the processing efficiency of the product.On the other hand, this structural design allows each chip 201 to lead the pins on the upper surface of the chip 201 to the second metal layer not through the complete second blind via 209, but instead through half of the second blind via 209. The volume occupied by the structure for connecting the conductive member 208 and the second metal layer is reduced, and the space available for the chip 201 is increased, which is conducive to the packaging of large-size chips 201.

[0055] S14: a second plastic package is manufactured in the second blind hole 209 and cut along the busbar of the second blind hole 209 to obtain a single-piece package.

[0056] The material of the second plastic package body may include one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic-based.

[0057] Specifically, the advantage of metallizing only the hole wall of the second blind hole 209 and then filling the hole with the second plastic package is that after cutting along the busbar of the second blind hole 209 to obtain a single-piece package, there is no need to plastic-encapsulate the metallized hole wall of each package separately, which simplifies the production process and improves processing efficiency.

[0058] In this embodiment, both sidewalls of the second blind via 209 are shared by the conductive members 208 corresponding to the two chips 201 to connect the conductive members 208 to the second metal layer. In some other embodiments, both sidewalls of the second blind via 209 are also used for conductive purposes. For example, one sidewall is used to connect the conductive member 208 corresponding to the chip 201 to the second metal layer, and the other sidewall is used to connect the second metal layer area corresponding to the other chip 201 to other devices. Similarly, the second blind via 209 is divided into two halves, which can be used by the two chips 201 to connect the conductive members 208 to the second metal layer or the second metal layer to other components. Sharing the second blind via 209 reduces the number of second blind vias 209 produced, improves processing efficiency, reduces occupied space, and facilitates the packaging of large-sized chips 201.

[0059] In some other embodiments, before cutting along the busbars of the second blind vias 209 to obtain a single-piece package, the step further includes forming a third plastic package on a side of the first plastic package 206 away from the carrier board, where the third plastic package covers the conductive member 208, the first blind vias 207, and the second blind vias 209. Specifically, the third plastic package is formed to protect the first blind vias 207, the second blind vias 209, and the conductive member 208 from air and corrosion.

[0060] in, Figure 6d The monolithic package is Figure 1 Schematic diagram of the monolithic package structure obtained after the package motherboard is cut along the busbar of the second blind hole. Figure 7For Figure 2 Schematic diagram of the structure of a single-piece package body obtained after the package motherboard is cut along the busbar of the second blind hole; Figure 8 For Figure 3 Schematic diagram of the structure of a single-piece package body obtained after the package motherboard is cut along the busbar of the second blind hole; Figure 9 For Figure 4 Schematic diagram of the structure of a single-piece package body obtained by cutting the package motherboard along the busbar of the second blind hole.

[0061] Different from the prior art, the present application proposes a chip 201 packaging method. This method provides a second blind via 209 between two adjacent chips 201. The conductive member 208 corresponding to each of the two adjacent chips 201 is connected to the second metal layer through the same second blind via 209, thereby reducing the number of second blind vias 209 produced and improving product processing efficiency. In addition, each chip 201 connects the conductive member 208 to the second metal layer through half of the second blind via 209 structure. The structure used to connect the conductive member 208 to the second metal layer occupies a smaller volume, and the space available for the chip 201 is increased, which is beneficial for the packaging of large-sized chips 201. Furthermore, the first inner pad 202 and the second outer pad 204 connected to the chip 201 are not directly contacted and overlapped, but are indirectly connected through a metallized through-hole 205. The advantage of this structural design is that the first pad 202 and the second pad 204 do not need to be precisely aligned, avoiding the poor connection effect and the risk of falling off caused by misalignment of the inner and outer pads. The inner first pad 202 is connected to the outer second pad 204 through the metallized through-hole 205 of the dielectric layer 203, so that the first pad 202 can be extended and changed in size or position at will in the first metal layer due to no alignment or deviation restrictions. The first pad 202 is more flexible, thereby improving the platform capability of the packaging motherboard.

[0062] Correspondingly, the present application also proposes a package body, which is manufactured by the chip packaging method described in the above embodiment.

[0063] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A package motherboard, characterized in that: The package motherboard includes: chip, A carrier board, the carrier board comprising a first metal layer, a dielectric layer, and a second metal layer stacked in sequence; the first metal layer comprising a plurality of first pads, the second metal layer comprising a plurality of second pads electrically connected to the first pads, wherein the chip is fixed to each of the first pads; a first plastic package, the first plastic package covering each of the chips and the first pads; wherein the first plastic package is formed with a plurality of metalized first blind holes and second blind holes with metalized hole walls, the second blind holes being arranged in a predetermined area between two adjacent chips; a conductive member, one end of the conductive member being connected to the chip through the metallized first blind via, and the other end of the conductive member being connected to the second metal layer through the metallized second blind via having the hole wall metallized, wherein each second blind via is used for connecting the conductive members on both sides to the second metal layer, or each second blind via is used for connecting the conductive member on one side to the second metal layer and also for connecting the first pad on the other side to the second metal layer; The second plastic sealing body is arranged in the second blind hole with the hole wall metallized.

2. A chip packaging method, characterized in that: include: Obtaining a carrier board, the carrier board comprising a first metal layer, a dielectric layer, and a second metal layer stacked in sequence, forming a first pad on the first metal layer, forming a second pad on the second metal layer, and electrically connecting the first pad and the second pad; Fixing the chip on the first pad and making a first plastic package, wherein the first plastic package is located on the first metal layer and covers the chip and the first pad; A first blind hole and a second blind hole are formed in the first plastic package body, and the hole wall of the second blind hole and the first blind hole are metallized. A conductive member is provided on a side of the first plastic package body away from the carrier board, the conductive member is connected to the chip through the metallized first blind hole, and the conductive member is connected to the second metal layer through the metallized hole wall of the second blind hole. The second blind hole is formed in a predetermined area between two adjacent chips, so that the conductive members on both sides of the second blind hole are connected to the second metal layer through the same second blind hole, or the conductive member on one side of the second blind hole is connected to the second metal layer through the second blind hole, and the first pad on the other side of the second blind hole is connected to the second metal layer through the same second blind hole. A second plastic package is manufactured in the second blind hole, and is cut along the busbar of the second blind hole to obtain a single-piece package.

3. The chip packaging method according to claim 2, characterized in that: The step of forming a first pad on the first metal layer and forming a second pad on the second metal layer includes: Pattern etching is performed on the first metal layer and the second metal layer respectively to form a first pad on the first metal layer and a second pad on the second metal layer.

4. The chip packaging method according to claim 2, characterized in that: The step of fixing the chip on the first pad includes: The chip is fixed on the first pad by conductive glue, so that the chip is connected to the first pad.

5. The chip packaging method according to claim 2, characterized in that: The steps of forming a first blind hole and a second blind hole in the first plastic package body, and metallizing the hole wall of the second blind hole and the first blind hole include: Making the first blind hole on the first plastic package body on the side of the chip away from the first pad by laser drilling, and performing copper deposition and electroplating on the first blind hole to form metal filling; The second blind hole is made in the preset area between two adjacent chips by laser drilling, and the hole wall of the second blind hole is copper plated and electroplated for metallization; wherein the second blind hole passes through the first plastic package and the dielectric layer.

6. The chip packaging method according to claim 2, characterized in that: The first plastic package body and the second plastic package body include one or more of epoxy resin, polyimide, bismaleimide triazine, and ceramic base.

7. The chip packaging method according to claim 2, characterized in that: Before the step of cutting along the busbars of the second blind holes to obtain a monolithic package, the method further includes: A third plastic packaging body is manufactured on a side of the first plastic packaging body away from the carrier board, and the third plastic packaging body covers the conductive component, the first blind hole and the second blind hole.

8. The chip packaging method according to claim 2, characterized in that: The chip includes a first surface and a second surface. Pins are provided on both the first surface and the second surface. The pins on the first surface are connected to the first metalized blind vias, and the pins on the second surface are connected to the first pads.

9. A package, characterized in that: The package body is manufactured by the chip packaging method according to any one of claims 2 to 8.

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