Control system and chip for automatically switching processor clock

Abstract

The application discloses a control system and a chip for automatically switching processor clock, and the control system comprises a switching control unit, a CPU unit and a path selector; there are at least two code partitions; there are at least two clock signals; the switching control unit is connected with each code partition, and the switching control unit is also connected with the CPU unit; the switching control unit is used for detecting the code partition currently accessed by the CPU unit, and then sending a selection signal to the path selector according to the code partition currently accessed by the CPU unit; an input end of the path selector is connected with a clock source, an output end of the path selector is connected with the CPU unit, and a selection end of the path selector is connected with the switching control unit; the path selector is used for switching the clock signal output to the CPU unit into the clock signal required by the code partition currently accessed by the CPU unit after receiving the selection signal.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a control system and chip for automatically switching processor clocks. Background Technology

[0002] With the development of technology, processors need to process more data. If they need to control the execution of high-computational algorithms cached in the code space, for example, when a processor with a relatively low operating frequency needs to control the execution of high-computational algorithms cached in the code space, the processor needs to be adjusted to operate at a higher clock frequency. However, in order for application software to respond normally (without excessive latency errors) to various switching instructions to adapt to the high-computational firmware programs required to be executed in the current software environment, the processor needs to configure relevant clock registers through software in the current application environment. This increases the instruction operation execution time, causing the processor to spend more time during the switching process between different operating frequencies, resulting in higher power consumption. The system device containing the processor consumes a lot of electrical energy, thereby reducing the processor's service life and affecting its performance. Summary of the Invention

[0003] This application discloses a control system and chip for automatically switching processor clocks, and the specific technical solution is as follows:

[0004] An automatic processor clock switching control system includes a switching control unit, a CPU unit, and a path selector. The switching control unit is connected to each code partition and also to the CPU unit. The switching control unit detects the code partition currently accessed by the CPU unit and sends a selection signal to the path selector based on the currently accessed code partition. The input of the path selector is connected to a clock source, the output of the path selector is connected to the CPU unit, and the selection terminal of the path selector is connected to the switching control unit. Upon receiving the selection signal, the path selector switches the clock signal output to the CPU unit to the clock signal required by the currently accessed code partition.

[0005] Furthermore, the control system also includes at least two code partitions, and / or at least two code partitions are externally configured on the control system; the control system also includes a clock source, and / or a clock source is externally configured on the control system; wherein, the clock source includes at least two clock signals; wherein, among the clock signals included in the clock source, there is a clock signal required by the CPU unit to access each code partition.

[0006] Further, the clock source includes a first working clock signal and a second working clock signal, wherein the clock frequency of the first working clock signal is higher than the clock frequency of the second working clock signal; the control system has a first code partition and a second code partition internally, or the control system has a first code partition and a second code partition externally; the first working clock signal is the clock signal required by the CPU unit to access the first code partition, and the second working clock signal is the clock signal required by the CPU unit to access the second code partition, wherein the computing power corresponding to the code stored in the first code partition is higher than the computing power corresponding to the code stored in the second code partition; the clock frequency required for the code stored in the first code partition to run is higher than the clock frequency required for the code stored in the second code partition to run.

[0007] Further, the selection signal includes a first selection signal and a second selection signal; the switching control unit is configured to, when detecting that the code partition currently accessed by the CPU unit changes from the first code partition to the second code partition, determine that the clock signal required for the CPU unit to currently access the second code partition is a second working clock signal, and send the first selection signal to the path selector; the path selector, upon receiving the first selection signal, switches the first working clock signal to the second working clock signal, and then outputs the second working clock signal to the CPU unit, so that the operating frequency of the CPU unit decreases from the clock frequency of the first working clock signal to the clock frequency of the second working clock signal; the switching control unit is configured to, when detecting that the code partition currently accessed by the CPU unit changes from the second code partition to the first code partition, determine that the clock signal required for the CPU unit to currently access the first code partition is a first working clock signal, and send the second selection signal to the path selector; the path selector, upon receiving the second selection signal, switches the second working clock signal to the first working clock signal, and then outputs the first working clock signal to the CPU unit, so that the operating frequency of the CPU unit increases from the clock frequency of the second working clock signal to the clock frequency of the first working clock signal.

[0008] Furthermore, the first code partition is located within a read-only memory (ROM), and the second code partition is located within an erase-write memory (ECM). The ROM contains a first system software environment and a first fixed clock signal. The code stored within the ROM runs within the first system software environment under the drive of the first fixed clock signal, reducing interference from external software configuration information. The code stored in the first code partition is accessible to the CPU unit under the first operating clock signal. The ECM contains a second system software environment and a second fixed clock signal. The code stored in the ECM runs within the second system software environment under the drive of the second fixed clock signal, reducing interference from external software configuration information. The code stored in the second code partition is accessible to the CPU unit under the second operating clock signal. The clock frequency of the first fixed clock signal is higher than the clock frequency of the second fixed clock signal.

[0009] Furthermore, when the CPU unit is in a low-power state, the CPU unit accesses the second code partition, and the code stored internally in the second code partition is in a running state; when the CPU unit's access to the second code partition is stopped by a hardware interrupt, either internally or externally, the CPU unit is triggered to start accessing the first code partition, and then the switching control unit controls the path selector to switch the clock signal output to the CPU unit to the first working clock signal; wherein, the control system is internally equipped with a timer for triggering an interrupt signal, the timer counts and generates an interrupt signal to notify the CPU unit, forming a hardware interrupt triggering method.

[0010] Furthermore, the CPU unit, after being woken up from a sleep state, is configured to trigger the switching control unit to send the second selection signal to the path selector via a hardware interrupt, so that the clock signal output by the path selector to the CPU unit is switched to the first working clock signal, and the code partition that the CPU unit needs to access is switched to the first code partition, and the code stored internally in the first code partition is guided to resume from a suspended state to a running state without changing the clock frequency of the clock signal required for the running of the code stored internally in the first code partition; wherein, when the CPU unit is in a sleep state, the entry address of the hardware interrupt is set within the first code partition; the sleep state is a low-power state.

[0011] Furthermore, the CPU unit accesses the corresponding code partition through the bus to obtain the code stored in the corresponding code partition; the switching control unit establishes a communication connection with each code partition through the bus to obtain the storage address in each code partition and monitors the access of the code partition by the CPU unit; the switching control unit also establishes a communication connection with the CPU unit through the bus to determine the code partition that the CPU unit currently needs to access.

[0012] Furthermore, each code partition is allocated from the same code space, each code partition is mounted on the same bus and its corresponding storage address is cached on the same bus; the CPU unit, the switching control unit and each code partition establish communication links through the same bus.

[0013] Further, the clock source includes a first clock unit and a second clock unit; the first clock unit is connected to the path selector; the path selector, upon receiving a second selection signal, connects the output of the first clock unit to the CPU unit, allowing the first clock unit to provide a first operating clock signal to the CPU unit; or, the first clock unit is connected to the path selector via a first frequency divider, which divides the clock signal output by the first clock unit into a first operating clock signal; the path selector, upon receiving a second selection signal, connects the output of the first frequency divider to the CPU unit, allowing the first frequency divider to provide a first operating clock signal to the CPU unit. The CPU unit provides a first operating clock signal; the second clock unit is connected to the path selector, and the path selector, upon receiving the first selection signal, connects the output of the second clock unit to the CPU unit, allowing the second clock unit to provide a second operating clock signal to the CPU unit; or, the second clock unit is connected to the path selector via a second frequency divider, which divides the clock signal output by the second clock unit into a second operating clock signal, and the path selector, upon receiving the first selection signal, connects the output of the second frequency divider to the CPU unit, allowing the second frequency divider to provide a second operating clock signal to the CPU unit.

[0014] A chip that integrates the aforementioned control system for automatically switching processor clocks.

[0015] The technical advantages of the disclosed technical solution are as follows: This application is a control system based on a switching control unit, a CPU unit, and a path selector that automatically switches the processor clock. The control system can be configured with code partitions and clock sources internally and externally. The control system automatically selects the clock signal provided by the clock source and outputs it to the CPU unit based on the clock frequency of the code running in the currently accessed code partition. The hardware selector automatically switches between different clock signals input to the CPU unit, thereby adaptively adjusting the CPU unit's operating frequency based on the code partition to be accessed. Compared to existing clock source switching operations, this reduces the need to call excessive clock registers for frequency division, allowing for frequency scaling of the CPU unit without using a frequency divider. It also eliminates the need to configure the processor's actions during clock signal switching in a dedicated configuration unit, and avoids requiring the CPU unit to frequently execute instructions for clock signal switching. This reduces the intervention of software instructions in the processor's built-in operating system, thereby reducing the time consumed during the entire clock signal switching process, lowering the power consumption of the CPU unit during clock signal switching, and ultimately reducing the power consumption of the entire control system.

[0016] The switching control unit detects when the CPU unit accesses the code partition and controls the path selector to automatically switch the clock signal input to the CPU unit, thereby achieving adaptive adjustment of the CPU unit's operating frequency. This prevents code partitions running at low clock frequencies from being accessed by CPU units operating at higher frequencies, reducing CPU unit power consumption. Specifically, when a code partition running at a low clock frequency needs to be accessed by the CPU unit, the CPU unit appropriately lowers its operating frequency. At this time, the code partition running at a high clock frequency may be idle, reducing CPU unit power consumption. It also prevents code partitions running at high clock frequencies from being accessed by CPU units operating at lower frequencies, maintaining normal system operation. Furthermore, with minimal software instruction intervention, even if the CPU unit's operating frequency needs to be increased to an excessively high frequency, the CPU unit will not generate excessive power consumption due to clock signal switching with a large frequency difference.

[0017] The control system disclosed in this application can also trigger the CPU unit's operating frequency to change to a higher frequency through a hardware interrupt, based on the CPU unit's current power consumption state (such as sleep state). That is, when the CPU is in sleep state, once it is woken up by external hardware, it enters the entry address in the first code partition guided by the hardware interrupt, so that the CPU unit switches to the high-frequency clock domain after startup. Since the configuration of application software is reduced, the CPU unit can directly access the high-frequency clock domain from the interrupt entry address after waking up, reducing the energy consumption caused by clock signal switching instruction operations, achieving more reasonable power consumption adjustment, so that the CPU unit can work at a higher operating frequency after waking up without generating too much power consumption, thereby improving the CPU unit's working performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the framework of a control system for automatically switching processor clocks, as disclosed in one embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] In the relevant descriptions of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] In the description of this application, unless otherwise expressly defined, terms such as "setup" and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0022] The internal architecture of a computer determines the flow of instructions and data, significantly impacting the system's performance and operation. Currently, a computer's internal architecture includes a processor (CPU), memory bridges, and input / output (I / O) bridges. The CPU processes data and sends instructions to the memory bridges; the memory bridges connect to memory, graphics cards, and I / O bridges, receiving instructions from the CPU and forwarding them to the appropriate memory, graphics card, or I / O bridge; and the I / O bridges connect to external devices, sending received instructions for execution.

[0023] The processor (CPU), also known as the Central Processing Unit (CPU), is an integrated circuit (IC) that performs processing, control, and storage within an information processing system. It is the core of the information processing system hardware, responsible for executing and controlling various calculations, input / output operations, and memory connections. The CPU unit disclosed in this application corresponds to this CPU unit. When the CPU is handling various computational tasks or overclocking to improve performance, its operating frequency needs to be switched to a higher clock frequency, potentially reaching several GHz or even tens of GHz. Conversely, when application software running at the high-frequency clock becomes idle, the CPU's operating frequency needs to be switched to a lower clock frequency, such as several MHz or tens of kHz.

[0024] During the process of a central processing unit (CPU) switching to different operating frequencies, the CPU handles various software and process tasks related to the switching, consuming significant instruction operation time and increasing power consumption. To reduce the power consumption generated during processor frequency switching, this embodiment discloses a control system for automatically switching the processor clock. The control system includes a switching control unit, a CPU unit, and a path selector. Based on the switching control unit, CPU unit, and path selector, a control system with clock signal switching functionality can be constructed to change the clock signal accessed by the CPU unit through a hardware switch. Specifically, it switches the CPU unit's operating frequency to adapt to the CPU unit's operating state. For example, if access to a high-speed clock domain (where the operating frequency required for code execution is relatively high, potentially reaching several GHz) is needed, then the clock signal accessed by the CPU unit is switched to a high-frequency clock signal. The CPU unit is connected to each code partition through the switching control unit. Each code partition may require a different operating frequency, thus the clock frequency of the clock signal required for the CPU unit to access each code partition is also different. (See also...) Figure 1It is understood that the switching control unit is connected to each code partition and also to the CPU unit. In some embodiments, the CPU unit is connected to each code partition through the switching control unit; or the CPU unit interacts with each code partition via the system bus, and the switching control unit also has an instruction data interaction relationship with the system bus, thus forming a communication link between the CPU unit, the switching control unit, and each code partition. The switching control unit is used to detect the code partition currently accessed by the CPU unit, and then send a selection signal sel to the path selector according to the code partition currently accessed by the CPU unit. Specifically, after determining the address information of the code partition currently accessed by the CPU unit, the address information is mapped to a pre-configured selection signal sel to select the corresponding clock signal of the externally input clock frequency to the CPU unit. For example, if the clock frequency required for the code to run in the currently accessed code partition is high, the selected clock signal cannot be too low. The input terminal of the path selector is connected to the clock source, wherein one data input terminal of the path selector is connected to a clock signal of a certain clock frequency provided by the clock source and is controlled by the selection terminal of the path selector; the output terminal of the path selector is connected to the CPU unit, specifically, the selection output terminal of the path selector is connected to the clock terminal of the CPU unit; the selection terminal of the path selector is connected to the switching control unit, specifically, the selection terminal of the path selector is connected to the selection signal sel output by the switching control unit, wherein the path selector is a multiplexer; the path selector is used to, upon receiving the selection signal sel, output the clock signal to the CPU unit. The signal is switched to the clock signal required by the CPU unit to access the code partition. That is, the clock signal currently required by the CPU unit is switched to be output to the CPU unit. Specifically, the clock signal clk_out currently required by the CPU unit is switched from the clock source and output to the clock terminal of the CPU unit through the switch path selected internally by the path selector, so that the operating frequency of the CPU unit is configured to be equal to the clock frequency of the clock signal transmitted to the CPU unit by the path selector. In the path selector, under the selection action of the selection signal sel, the clock signal currently required by the CPU unit is the clock signal transmitted to the CPU unit by the path selector, which is also the clock signal currently provided to the CPU unit by the clock source.

[0025] In some embodiments, the control system further includes at least two code partitions, or at least two code partitions are externally configured to the control system; the control system further includes a clock source, or a clock source is externally configured to the control system; wherein, the clock source includes at least two clock signals, each clock signal having a different clock frequency to adapt to the varying operating frequencies of the code partitions accessed by the CPU unit; among the clock signals included in the clock source, there is a clock signal required by the CPU unit to access each code partition.

[0026] In summary, in this embodiment, code partitions and clock sources can be set inside and outside the control system. The control system automatically selects the clock signal provided by the clock source to output to the CPU unit based on the clock frequency of the code running in the currently accessed code partition. A hardware selector automatically switches the clock signal input to the CPU unit, thereby adaptively adjusting the CPU unit's operating frequency based on the code partition to be accessed. Compared to existing clock source switching operations, this reduces the need for excessive clock register calls for frequency division, allowing for frequency scaling of the CPU unit without using a frequency divider. It also eliminates the need to configure the processor's actions during clock signal switching in a dedicated configuration unit and reduces the CPU unit's frequent execution of instructions for clock signal switching. This reduces the intervention of software instructions in the processor's built-in operating system, thereby reducing the time consumed during the entire clock signal switching process, lowering the power consumption of the CPU unit during clock signal switching, and ultimately reducing the power consumption of the entire control system.

[0027] It should be noted that all unit modules involved in this embodiment can be logic circuit modules generated by mapping using the Verilog hardware programming language under EDA tools, including the switching control unit, CPU unit, and path selector disclosed in this embodiment. Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form. It can represent logic circuit diagrams and logical expressions, as well as the logical functions performed by a digital logic system. In practical applications, a logic circuit module can be a logic circuit unit, a part of a logic circuit unit, or a combination of multiple logic circuit units. Furthermore, to highlight the innovative aspects of this invention, logic circuit modules that are not closely related to solving the technical problems proposed in this invention are not introduced in the embodiments of this invention. However, this does not mean that other modules are absent in the embodiments of this invention.

[0028] As one example, see Figure 1It is understood that the clock source includes a first working clock signal HCLK and a second working clock signal LCLK; the clock source may also include a clock signal with a different clock frequency than the first working clock signal HCLK, or the clock source may also include a clock signal with a different clock frequency than the second working clock signal LCLK. Wherein, the clock frequency of the first working clock signal HCLK is higher than the clock frequency of the second working clock signal LCLK. For example, when the clock frequency of the first working clock signal HCLK reaches 1.5GHz, the clock frequency of the second working clock signal LCLK is set to 1.2MHz. Correspondingly, at least a first code partition and a second code partition exist, that is, the first code partition and the second code partition exist internally within the control system, or the first code partition and the second code partition exist externally within the control system; the first operating clock signal HCLK is the clock signal required by the CPU unit to access the first code partition, but is not the clock signal required to run code within the first code partition; the second operating clock signal LCLK is the clock signal required by the CPU unit to access the second code partition, but is not the clock signal required to run code within the second code partition; wherein, the computing power corresponding to the code stored in the first code partition is higher than the computing power corresponding to the code stored in the second code partition, and the clock frequency required to run the code stored in the first code partition is higher than that of the first code partition. The clock frequency required for the execution of code stored in the two code partitions is preferably such that the execution space capacity of the first code partition is greater than that of the second code partition, so as to ensure that code with a large amount of functional code runs in the first code partition (which can be understood as running under the driving action of the clock signal generated by the oscillation inside the first code partition), and to ensure that code with a small amount of functional code runs in the second code partition (which can be understood as running under the driving action of the clock signal generated by the oscillation inside the second code partition); there are also code partitions of other capacities, and the clock frequency required for the execution of code stored in the code partitions of other capacities is different from the clock frequency required for the execution of code stored in the first code partition and also different from the clock frequency required for the execution of code stored in the second code partition.

[0029] In some embodiments, the CPU unit first reads the corresponding executable file from its internal preset memory according to the loading request, then loads it into the execution space of the first code partition, and runs it within the execution space of the first code partition. After the CPU unit receives the first working clock signal HCLK, the first code partition stores pre-loaded code and other data. The larger the storage capacity, the greater the computing power supported by the corresponding running algorithm. Similarly, the CPU unit also first reads the corresponding executable file from its internal preset memory according to the loading request, then loads it into the execution space of the second code partition, and runs it within the execution space of the second code partition. After the CPU unit receives the second working clock signal LCLK, the second code partition stores pre-loaded code and other data. The smaller the storage capacity, the smaller the computing power supported by the corresponding running algorithm.

[0030] It should be noted that the aforementioned executable file is loaded and formed according to a certain clock cycle, and it is an executable file compiled from the code corresponding to the pre-stored algorithm. The aforementioned CPU unit belongs to the processor, which can be a single-core unit in a multi-core processor; computing power is a unit of measurement for the amount of data processed by a single CPU core under a certain communication time, and it is related to the processor's operating frequency, computing bit width, etc. The size of the computing power represents the speed at which the CPU unit calculates binary information, and in this embodiment, it is related to the amount of data that the executable file can process per unit time during operation.

[0031] In some embodiments, the second code partition is a low-power region that supports low-speed code execution, while the first code partition is a high-speed region. When the first code partition is configured to run in a multimedia clock domain, camera connection clock domain, or Ethernet clock domain, it supports the execution of firmware algorithms with high computing power; the second code partition is configured to run in a basic input / output module, satisfying basic system boot and simple instruction data read / write requirements. For example, in an embedded MCU system, high-performance code can be stored in the read-only memory (ROM) configured as the first code partition, while ordinary code is placed in the erase-read-write memory (flash) configured as the second code partition. The speed of running code in the ROM is faster than the speed of running code in the embedded flash.

[0032] As one embodiment, in order to reduce software intervention, such as reducing the frequent execution of instructions in the operating system built into the CPU unit, additional hardware switching circuits need to be designed to control the operating frequency of the CPU unit. Correspondingly, in this embodiment, the selection signal sel includes a first selection signal and a second selection signal, which are set according to the clock signal required by the CPU unit to access each code partition, so as to switch the selection path of the path selector.

[0033] In this embodiment, the switching control unit is used to detect when the code partition currently accessed by the CPU unit changes from the first code partition to the second code partition, that is, when it detects that the address currently requested by the CPU unit is located in the second code partition and may not actually have started accessing data in the second code partition yet, while the CPU unit is still accessing data in the first code partition, it determines that the clock signal required for the CPU unit to access the second code partition is the second working clock signal LCLK, and sends a first selection signal to the path selector to switch the clock input of the CPU unit to the second working clock signal. Here, the second working clock signal is the clock signal input to the path selector from an external clock source. In this embodiment, the selection input is performed to the CPU unit through a hardware selector. Based on this, the path selector is used to switch the first working clock signal to the second working clock signal after receiving the first selection signal, that is, to switch the selected path from connecting the first working clock signal to connecting the second working clock signal, forming a switching of the selection branch for connecting the clock input of the CPU unit, and then outputting the second working clock signal to the CPU unit. Figure 1 In this context, `clk_out` refers to the second working clock signal, LCLK, which reduces the operating frequency of the CPU unit from the clock frequency of the first working clock signal to the clock frequency of the second working clock signal. Specifically, when a code partition running at a lower clock frequency needs to be accessed by the CPU unit, the CPU unit appropriately reduces its operating frequency. At this time, the code partition running at a higher clock frequency may be idle, thus reducing the power consumption of the CPU unit. Compared to existing technologies, this method of switching via a selector during the entire clock signal switching process reduces frequent switching operations on code instructions, thereby reducing the overall system power consumption. It also prevents code partitions running at lower clock frequencies from being accessed by CPU units operating at higher clock frequencies, reducing the power consumption generated by the CPU unit's operation.

[0034] The switching control unit is configured to detect when the code partition currently accessed by the CPU unit changes from the second code partition to the first code partition, i.e., when it detects that the address currently requested by the CPU unit is located in the first code partition but may not actually have started accessing data in the first code partition yet, and the CPU unit is still accessing data in the second code partition, determine that the clock signal required for the CPU unit to access the first code partition is the first working clock signal HCLK, and send a second selection signal to the path selector to switch the clock input of the CPU unit to the first working clock signal HCLK. Here, the first working clock signal is the clock signal input from an external clock source to the path selector. In this embodiment, the selection input is performed by a hardware selector to the CPU unit. Based on this, the path selector, upon receiving the second selection signal, switches the second working clock signal to the first working clock signal, i.e., switches the selected path from connecting the second working clock signal to connecting the first working clock signal, forming a switching of the selection branch for connecting the clock input of the CPU unit, and then outputs the first working clock signal to the CPU unit. Figure 1 In this context, `clk_out` refers to the first operating clock signal, HCLK, which increases the operating frequency of the CPU unit from the clock frequency of the second operating clock signal to the clock frequency of the first operating clock signal. This prevents code partitions running at high clock frequencies from being accessed by CPU units operating at lower clock frequencies, thus maintaining normal system operation. Furthermore, with reduced software instruction intervention, even if the CPU unit's operating frequency needs to be increased to an excessively high frequency, the CPU unit will not consume excessive power due to clock signal switching with a large frequency difference. Compared to existing technologies, this method reduces frequent switching operations on code instructions (involving cyclically configuring clock source switching and reverting in software instructions) during the entire clock signal switching process, thereby reducing the power consumption generated by the CPU unit during clock signal switching.

[0035] In summary, the switching control unit detects the CPU unit's access to the code partition and controls the path selector to automatically switch the clock signal input to the CPU unit, thereby achieving adaptive adjustment of the CPU unit's operating frequency and reducing the overall power consumption of the control system.

[0036] In some embodiments, the first code partition is disposed in a read-only memory (ROM), and the second code partition is disposed in an erase-read-write memory (Flash). The ROM contains a first system software environment and a first fixed clock signal. The code stored in the ROM runs in the first system software environment under the drive of the first fixed clock signal, so as to reduce the interference of software configuration information outside the ROM. The code stored in the first code partition does not run under the control of the first working clock signal HCLK, but the CPU unit is allowed to access it under the first working clock signal. The code stored in the first code partition runs under the control of the first fixed clock signal.

[0037] It's important to note that read-only memory (ROM) can only read information, not write it. Typically, a basic input / output system, called the BIOS (Basic Input / Output System), is embedded within the ROM. Its main functions are to perform power-on self-tests, initialize various functional modules within the system, install drivers for the system's basic input / output systems, and boot the operating system. Therefore, provided the code stored in the first code partition runs under the control of the first embedded clock signal, the software does not need to perform clock switching operations.

[0038] Because ROM has the characteristic of not losing information after power failure, it can be used as a BIOS chip for booting algorithm firmware, to store some hardware drivers, and also as the software application layer, hardware driver layer, and some public function libraries in the operating system.

[0039] The erase read / write memory internally contains a second system software environment and a second fixed clock signal. The code stored inside the erase read / write memory runs within the second system software environment under the drive of the second fixed clock signal, thereby reducing the interference of external software configuration information. The code stored in the second code partition does not run under the control of the second working clock signal LCLK, but the CPU unit is allowed to access it under the second working clock signal. The code stored in the second code partition runs under the control of the second fixed clock signal.

[0040] The clock frequency of the first firmware clock signal is higher than that of the second firmware clock signal. When the program runs in the ROM, the CPU unit automatically runs at high speed under the drive of the first operating clock signal HCLK, and the ROM does not require instruction configuration for software clock signal switching. When the CPU unit switches to access the erase read-write memory flash, the code running inside the erase read-write memory flash automatically reduces the clock frequency of the clock signal currently required by the CPU unit. It is worth noting that the execution of the code stored in the read-only memory and the erase read-write memory is not affected by the clock signal output by the switching control unit, that is, it is not affected by the operating frequency of the CPU unit.

[0041] Based on the aforementioned embodiments, the clock domains of the first and second fixed clock signals are relatively independent clock domains; the clock domains of the first and second working clock signals are also relatively independent clock domains; and the clock domains of the first and second fixed clock signals, as well as the clock domains of the first and second working clock signals, are mutually independent. This can meet the operating frequency requirements of different code partitions, achieve the separation of clock signals required for high-speed and low-speed code partitions, and also achieve the separation of the first working clock signal, the second working clock signal, and other selectable input clock signals input to the path selector, which helps to reduce the area occupied by different clock domains and the implementation difficulty.

[0042] In one embodiment, when the CPU unit is in a low-power state, it accesses the second code partition, and the code stored internally in the second code partition is in a running state. The CPU unit's operating frequency is equal to the clock frequency of the second operating clock. It operates at the second operating clock frequency for an extended period, and may even enter a sleep state, resulting in lower power consumption, at least lower than the power consumption generated when the CPU unit's operating frequency is equal to the clock frequency of the first operating clock. This corresponds to the CPU unit being in a low-power state. When the CPU unit's access to the second code partition is stopped by a hardware interrupt, either internally or externally, the CPU unit is triggered to start accessing the first code partition. Then, the switching control unit controls the path selector to switch the clock signal output to the CPU unit to the first operating clock signal. In this embodiment, the control system is internally equipped with a timer for triggering an interrupt signal. The timer counts and generates an interrupt signal to notify the CPU unit, forming a hardware interrupt triggering method. Compared with the prior art, which uses too many clock registers to perform clock frequency division processing to achieve the effect of clock signal switching, this embodiment uses a hardware interrupt triggering method to trigger the path selector to change the input clock signal to meet the CPU unit's current access to the first code partition, thus preventing excessive power consumption during clock switching (CPU unit operating frequency switching).

[0043] Furthermore, when the CPU unit is in a high-power state, it accesses the first code partition, and the code stored inside the first code partition is in a running state. The CPU unit's operating frequency is equal to the clock frequency of the first working clock. Operating at the first working clock frequency for an extended period and continuously performing cache read / write operations generates high power consumption, at least higher than the power consumption generated when the CPU unit's operating frequency is equal to the clock frequency of the second working clock. This corresponds to the CPU unit being in a high-power state, where the clock frequency of the first working clock signal can be considered much higher than the clock frequency of the second working clock signal. When the CPU unit's access to the first code partition is stopped by a hardware interrupt, either internally or externally, the CPU unit is triggered to start accessing the second code partition. The switching control unit then controls the path selector to switch the clock signal output to the CPU unit to the second working clock signal, reducing the CPU unit's operating frequency to the clock frequency of the second working clock signal. This reduces the power consumption generated by the CPU unit during the clock signal switching process.

[0044] It should be noted that when the CPU unit is triggered to access the corresponding code partition, the interrupt entry address needs to be pre-set in the corresponding code partition. That is, the address of the first instruction executed by the interrupt function (entry function) is called the function entry address, and the interface function can be found through this address. The interface functions required by the code partition accessed by the CPU unit come from the same executable file and / or different executable files. In the code partition accessed by the CPU unit, each function is configured to correspond to a specific function, namely a computational function. After a function is compiled, it becomes a series of instructions, recorded in the executable file. When the corresponding function is called, the function instruction code (binary data) occupies a storage unit in the execution space of the code partition. The control system, based on the hardware circuit switching mechanism, selects a code partition with an appropriate CPU unit operating frequency and memory resources to run the relevant algorithm functions in the execution space of the corresponding code partition, thereby reducing the power consumption of the control system by utilizing reasonable memory space and reasonable operating frequency.

[0045] Based on the above embodiments, the CPU unit, after being woken up from a sleep state, is configured to trigger the switching control unit to send the second selection signal to the path selector via a hardware interrupt, so that the clock signal output by the path selector to the CPU unit is switched to the first working clock signal, and the code partition that the CPU unit needs to access is switched to the first code partition, and the code stored internally in the first code partition is guided to resume from a suspended state to a running state without changing the clock frequency of the clock signal required for the running of the code stored internally in the first code partition; wherein, when the CPU unit is in a sleep state, the entry address of the hardware interrupt is set in the first code partition; the sleep state is a low-power state. Therefore, the control system can trigger the CPU unit's operating frequency to switch to a higher frequency via a hardware interrupt based on the CPU unit's current power consumption state (e.g., sleep state). That is, when the CPU is in sleep state, once it is woken up by external hardware, it enters the entry address in the first code partition guided by the hardware interrupt, so that the CPU unit switches to the high-frequency clock domain after startup. By reducing software configuration and energy consumption during the software operation stage, the control system can achieve better CPU unit power consumption adjustment. Thus, without generating excessive power consumption, the CPU unit can work at a higher operating frequency after being woken up, thereby improving the CPU unit's performance.

[0046] It should be added that hardware-triggered wake-up can wake up suspended threads / processes / tasks in the CPU unit, restore the state information formed by the CPU unit before hibernation, and restore the CPU unit, on-chip peripherals and off-chip peripherals (including switching control unit, clock source, path selector and code partition) to the running state before hibernation. Then, in this embodiment, the code partition that the CPU unit needs to access will be switched to the first code partition, and the clock signal connected to the CPU unit will also be switched to the first working clock signal, which can trigger the code stored in the first code partition to run (the code stored in the first code partition may have already entered the running state in advance).

[0047] In one embodiment, the CPU unit accesses the corresponding code partition via the bus to obtain the code stored within that partition, enabling it to invoke the required instruction code. The switching control unit establishes communication with each code partition via the bus, including instruction request and response, and data exchange and transmission, to obtain the storage address within each code partition and monitor the access status of the code partition by the CPU unit. The switching control unit also establishes communication with the CPU unit via the bus, including instruction request and response, and data exchange and transmission, to determine the code partition currently accessed by the CPU unit. Specifically, within the code partition currently accessed by the CPU unit, the called function is registered to a structure with global variables and global functions, forming specified link information. Specifically, when a function call occurs, the executable file name, the function's number within the executable file, the CPU unit's processing core number, and the function parameters are loaded and transmitted to the bus, then parsed, allowing sharing between the CPU unit and the switching control unit.

[0048] In the above embodiments, each code partition is allocated from the same code space, each code partition is mounted on the same bus and its corresponding storage address is cached on the same bus. The CPU unit and the switching control unit are both mounted on the same bus and establish handshake communication synchronization with the bus. Therefore, the CPU unit, the switching control unit and each code partition establish communication links through the same bus, including instruction request and response and data transmission, which can achieve the effect of handshake communication synchronization. This allows the switching control unit to detect the address information of the code partition that the CPU unit needs to access, and then share the result of the CPU unit's automatic switching of the accessed clock signal, adapting to the data instruction interaction needs under various operating frequency environments.

[0049] The buses mentioned in this embodiment include, but are not limited to, AHB (Advanced High performance Bus), APB (Advanced Peripheral Bus), and External Bus. The clock signal of the bus can be provided by the CPU unit, which requires the CPU unit's operating frequency to be compatible with the clock frequency required for running code within the code partition. This is so that the CPU unit, the switching control unit, and each code partition can establish synchronous communication through the same bus, reducing additional clock signal switching instruction operation time.

[0050] As one embodiment, the clock source includes a first clock unit and a second clock unit; wherein, the first clock unit can directly generate a first working clock signal or generate a first working clock signal through an additional frequency divider; the second clock unit can directly generate a second working clock signal or generate a second working clock signal through an additional frequency divider. The first clock unit and the second clock unit can be implemented by a phase-locked loop clock circuit (PLL clock circuit), preferably, both the first clock unit and the second clock unit can include an oscillator to generate the first working clock signal and / or the second working clock signal.

[0051] In one embodiment, the first clock unit is connected to the path selector, and the output of the first clock unit is connected to one input of the path selector. Upon receiving the second selection signal, the path selector connects the output of the first clock unit to the CPU unit, allowing the first clock unit to provide a first operating clock signal HCLK to the CPU unit through the selection function of the path selector. Alternatively, the first clock unit is connected to the path selector via a first frequency divider, which divides the clock signal output by the first clock unit into the first operating clock signal HCLK. Upon receiving the second selection signal, the path selector connects the output of the first frequency divider to the CPU unit, allowing the first frequency divider to provide the first operating clock signal HCLK to the CPU unit through the selection function of the path selector.

[0052] In another embodiment, the second clock unit is connected to the path selector, and the output of the second clock unit is connected to another input of the path selector. Upon receiving a first selection signal, the path selector connects the output of the second clock unit to the CPU unit, allowing the second clock unit to provide the CPU unit with a second operating clock signal LCLK through the selection function of the path selector. Alternatively, the second clock unit is connected to the path selector via a second frequency divider. The second frequency divider divides the clock signal output by the second clock unit into a second operating clock signal LCLK. Upon receiving the first selection signal, the path selector connects the output of the second frequency divider to the CPU unit, allowing the second frequency divider to provide the CPU unit with the second operating clock signal LCLK through the selection function of the path selector.

[0053] Preferably, regardless of whether the first clock unit is connected to the path selector via a frequency divider or whether the second clock unit is connected to the path selector via a frequency divider, the output of the path selector in this preferred embodiment is connected to the CPU unit via a third frequency divider. That is, the first or second working clock signal selected and output by the path selector will be divided and processed by the third frequency divider into a working clock signal that can be used normally by the CPU unit, thereby realizing the automatic switching of the CPU unit to the pre-configured working frequency.

[0054] Based on the foregoing embodiments, a chip is also disclosed that integrates the aforementioned automatic processor clock switching control system. Preferably, in this chip, the code partition is either an on-chip memory unit or an external memory unit, and the clock source is either an on-chip clock unit or an external clock unit. This enriches the application scenarios of the chip's on-chip integrated control system and improves the versatility of clock signal switching (processor operating frequency switching). Within this chip, a load request can be notified to the CPU unit via a hardware interrupt, and an externally input clock signal can be switched directly via a selector, reducing waiting time in software logic flows such as instructions. The type of load request is associated with a pre-configured communication protocol or a firmware algorithm to be run.

[0055] In this embodiment, the code partition includes at least a low-speed memory space and a high-speed memory space. The code stored in the low-speed memory space requires a lower running speed than the code stored in the high-speed memory space. The code partition is matched to the running speed required by the code stored within it. The frequency of the clock signal set by the clock source is configured so that the CPU unit enters the clock domain appropriate for the code partition to be accessed, thereby satisfying the functional effect achieved by the code partition in executing the corresponding function within a specified time. Furthermore, the real-time performance and low power consumption of switching between different clock signals are excellent. For example, the CPU unit only needs to work in microseconds to complete the loading of the executable file or even trigger the code in the running space to enter the running state, thus satisfying the functional effect achieved by the code partition in executing the corresponding function within a specified time while consuming low power costs.

[0056] In the embodiments provided in this application, it should be understood that the disclosed units and systems can be implemented in other ways. For example, the control system embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0057] The integrated units implemented as logical functional units described above can be stored in a computer-readable storage medium. These logical functional units, stored in a storage medium, include several instructions to cause chips, terminals, and devices (which may be personal computers, servers, or network devices, etc.) to execute portions of the control system described in the various embodiments of this invention. The storage medium containing the aforementioned code partition can include various media capable of storing code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A control system for automatically switching processor clocks, characterized in that, The control system comprises a switching control unit, a CPU unit and a path selector; The switching control unit is connected with each code partition and also connected with the CPU unit; the switching control unit is used for detecting the code partition currently accessed by the CPU unit and then sending a selection signal to the path selector according to the code partition currently accessed by the CPU unit; The input end of the path selector is connected with a clock source, the output end of the path selector is connected with the CPU unit, and the selection end of the path selector is connected with the switching control unit; The path selector is used for switching the clock signal output to the CPU unit into the clock signal required by the code partition currently accessed by the CPU unit after receiving the selection signal; The control system further comprises at least two code partitions and / or at least two code partitions are arranged outside the control system; The control system further comprises a clock source and / or a clock source is arranged outside the control system; wherein the clock source comprises at least two clock signals; Among the clock signals comprised by the clock source, there is a clock signal required by the CPU unit to access each code partition; The clock source comprises a first working clock signal and a second working clock signal, wherein the clock frequency of the first working clock signal is higher than the clock frequency of the second working clock signal; There are a first code partition and a second code partition inside the control system or outside the control system; The first working clock signal is a clock signal required by the CPU unit to access the first code partition, and the second working clock signal is a clock signal required by the CPU unit to access the second code partition, wherein the corresponding matching computing power of the code stored in the first code partition is higher than the corresponding matching computing power of the code stored in the second code partition; The clock frequency required by the code stored in the first code partition to run is higher than the clock frequency required by the code stored in the second code partition to run.

2. The control system of claim 1, wherein, The selection signal comprises a first selection signal and a second selection signal; When the switching control unit detects that the code partition currently accessed by the CPU unit changes from the first code partition to the second code partition, it determines that the clock signal required by the CPU unit to access the second code partition is the second working clock signal and sends the first selection signal to the path selector; the path selector is used for switching the first working clock signal to the second working clock signal after receiving the first selection signal, and then outputting the second working clock signal to the CPU unit, so as to reduce the working frequency of the CPU unit from the clock frequency of the first working clock signal to the clock frequency of the second working clock signal. The switching control unit is configured to determine that the clock signal required by the CPU unit to access the first code partition currently is the first working clock signal when the code partition currently accessed by the CPU unit is changed from the second code partition to the first code partition, and send the second selection signal to the path selector; and the path selector is configured to switch the second working clock signal to the first working clock signal after receiving the second selection signal, and output the first working clock signal to the CPU unit, so that the working frequency of the CPU unit is increased from the clock frequency of the second working clock signal to the clock frequency of the first working clock signal.

3. The control system of claim 2, wherein, The first code partition is arranged in a read-only memory, and the second code partition is arranged in an erasable read-write memory. The first system software environment and the first fixed clock signal are fixed in the read-only memory, and the code stored in the read-only memory runs in the first system software environment under the driving action of the first fixed clock signal, so as to reduce the intervention of software configuration information outside the read-only memory. The code stored in the first code partition allows the CPU unit to access under the first working clock signal. The second system software environment and the second fixed clock signal are fixed in the erasable read-write memory, and the code stored in the erasable read-write memory runs in the second system software environment under the driving action of the second fixed clock signal, so as to reduce the intervention of software configuration information outside the erasable read-write memory. The code stored in the second code partition allows the CPU unit to access under the second working clock signal. The clock frequency of the first fixed clock signal is higher than the clock frequency of the second fixed clock signal.

4. The control system of claim 2, wherein, When the CPU unit is in a low-power consumption state, the CPU unit accesses the second code partition, and the code stored in the second code partition is in a running state; after the CPU unit or the outside of the CPU unit interrupts the CPU unit from accessing the second code partition in a hardware interrupt manner, the CPU unit is triggered to start accessing the first code partition, and the switching control unit controls the path selector to switch the clock signal output to the CPU unit to the first working clock signal. The control system is internally provided with a timer for triggering an interrupt signal, and the timer generates an interrupt signal to notify the CPU unit, forming a hardware interrupt triggering manner.

5. The control system of claim 4, wherein, The CPU unit is configured to, after being woken up from a sleep state, trigger the switching control unit to send the second selection signal to the path selector in a hardware interrupt manner, so that the path selector switches the clock signal output to the CPU unit to the first working clock signal, and switches the code partition required to be accessed by the CPU unit to the first code partition, and guides the code stored in the first code partition to recover from a suspended state to a running state without changing the clock frequency of the clock signal required by the code stored in the first code partition to run. The CPU unit is in a sleep state, and the entry address of the hardware interrupt is set in the first code partition; the sleep state is one of the low power consumption states.

6. The control system of claim 1, wherein, The CPU unit accesses the corresponding code partition through a bus to obtain the code stored in the corresponding code partition; The switching control unit establishes communication with each code partition through the bus to obtain the storage address in each code partition and monitor the access of the code partition by the CPU unit; The switching control unit also establishes communication with the CPU unit through the bus to determine the code partition currently required to be accessed by the CPU unit.

7. The control system of claim 6, wherein, Each code partition is allocated from the same code space, and each code partition is mounted on the same bus and caches the corresponding storage address on the same bus; The CPU unit, the switching control unit, and each code partition establish communication through the same bus.

8. The control system of claim 2, wherein, The clock source includes a first clock unit and a second clock unit; The first clock unit is connected with the path selector; the path selector is used to connect the output end of the first clock unit to the CPU unit after receiving a second selection signal, so that the first clock unit provides a first working clock signal for the CPU unit; or the first clock unit is connected with the path selector through a first frequency divider, the first frequency divider processes the clock signal output by the first clock unit as a first working clock signal; the path selector is used to connect the output end of the first frequency divider to the CPU unit after receiving a second selection signal, so that the first frequency divider provides a first working clock signal for the CPU unit; The second clock unit is connected with the path selector, and the path selector is used to connect the output end of the second clock unit to the CPU unit after receiving a first selection signal, so that the second clock unit provides a second working clock signal for the CPU unit; or the second clock unit is connected with the path selector through a second frequency divider, the second frequency divider processes the clock signal output by the second clock unit as a second working clock signal, and the path selector is used to connect the output end of the second frequency divider to the CPU unit after receiving a first selection signal, so that the second frequency divider provides a second working clock signal for the CPU unit.

9. A chip, characterized by The chip integrates the control system of the automatic switching processor clock according to any one of claims 1 to 8.

Images