A multi-path MBI real-time processing architecture and method based on SMP mode

Abstract

The application belongs to the technical field of avionics system, and particularly relates to a multi-channel MBI real-time processing architecture and method based on an SMP mode, which comprises a master control module and a multi-channel bus interface module, a CPU processor is arranged in the master control module, application software modules and MBI driving software modules are loaded in the CPU processor, a plurality of MBI protocol chips are arranged in the multi-channel bus interface module, the plurality of MBI protocol chips communicate with the CPU processor through a LocalBus, and the plurality of MBI protocol chips are connected to an MBI bus interface. The FPGA chip hardware resources are reduced, the cost is reduced, the driving software maintenance amount is reduced, the MBI real-time performance is further improved, and the system reliability is further improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of avionics system, and particularly relates to a multi-bus interface (MBI) real-time processing architecture and method based on a symmetric multiprocessing (SMP) mode. BACKGROUND

[0002] The multi-bus interface (MBI) is a common name of the GJB289A bus, and is commonly used for communication between buses in the fields of combat, flight and weapons in the avionics field. The MBI requires high real-time response and high data integrity. The MBI is functionally divided into a bus controller (BC) function, a backup bus controller (BBC) function, a remote terminal (RT) function and a bus monitor (BM) function. To ensure reliability, there is AB channel redundancy backup in the same MBI bus network, but only one channel is in a working state at the same time. The functions of each MBI are currently realized by independent protocol chips.

[0003] To meet the requirement of high real-time response, the MBI adopts interrupt real-time processing of new bus data in the RT and BM modes. The MBI interrupts are frequent, and direct CPU interrupt processing will cause other tasks to be unable to be scheduled in real time, affecting flight safety. Therefore, the traditional MBI real-time processing method adopts FPGA chip interrupt processing of data on the protocol chip, and the CPU performs data interaction through PCI / PCIE period access to the FPGA dual port. The whole MBI data processing system architecture is as shown in Figure 1

[0004] The traditional MBI architecture has the following four deficiencies:

[0005] Firstly, a large number of hardware resources are required, and the cost is high. To ensure the real-time and integrity of MBI data, one MBI requires one expensive FPGA chip, and N MBIs require N FPGA chips. This not only requires a large amount of PCB board space, but also greatly increases the hardware cost.

[0006] Secondly, the communication real-time has further room for improvement. The MBI driver software and the MBI transmission software perform data interaction through the FPGA dual port RAM. When the MBI transmission software obtains new data but has not written it into the FPGA dual port RAM, the application software will not obtain the new data at this time, and can only process it in the next cycle, reducing the real-time performance.

[0007] ​Then, the system reliability is reduced. It is shown in two points: first, the increase of communication routing links increases the risk of data error. N-way MBI data is not directly sent to CPU for processing by the protocol chip, but is sent to CPU for processing by N FPGA chips, so that any problem of the FPGA chip will lead to abnormal MBI function of the way. Second, N-way FPGA chips need to be cooled, which increases the power consumption of the case and increases the difficulty of thermal design, directly leading to the increase of system unreliability.

[0008] Finally, the maintenance amount of the drive software is large. If there are N-way MBI, the number of software maintained by the drive software designer is N+1, including N MBI transmission software and 1 MBI drive software. SUMMARY

[0009] The technical problem solved by the present application is to reduce the FPGA chip hardware resources, reduce the cost, reduce the maintenance amount of the drive software, further improve the MBI real-time performance, and further improve the system reliability. The present application provides a multi-way MBI real-time processing architecture and method based on SMP mode.

[0010] The technical solution of the present application is:

[0011] In a first aspect,

[0012] The embodiment of the present application provides a multi-way MBI real-time processing architecture based on SMP mode. The architecture comprises a master module and a multi-way bus interface module. A CPU processor is arranged in the master module. An application software module and an MBI drive software module are loaded in the CPU processor. A plurality of MBI protocol chips are arranged in the multi-way bus interface module. The plurality of MBI protocol chips communicate with the CPU processor through a LocalBus. The plurality of MBI protocol chips are connected to an MBI bus interface.

[0013] Further, the application software module periodically processes MBI data.

[0014] The MBI drive software module is a specific implementation of the functions of MBI protocol chip initialization, state acquisition, command interaction, and data read-write function.

[0015] Further, the MBI drive software module also provides a function interface to the MBI application software, so that the MBI application software can realize the MBI related functions.

[0016] Further, the CPU processor is a multi-core processor. The interrupts and tasks related to the MBI drive software and the interrupts and tasks related to other software are respectively run on different CPU cores. A plurality of cores are set to only process the underlying tasks related to the MBI, so that the interrupts of the multi-way MBI protocol chips are distributed to the plurality of cores.

[0017] Further, the multi-channel MBI real-time processing architecture sends a message data stream as follows: an application software module calls a related interface in an MBI driver software module to write to-be-sent data into an MBI protocol chip RAM, and the MBI protocol chip sends the data to the MBI bus according to its own scheduling logic.

[0018] Further, the multi-channel MBI real-time processing architecture receives a message data stream as follows: after the MBI protocol chip receives new data from the MBI bus, the MBI driver software module is notified through a message interrupt in the RT mode and the BM mode, and the offset address of the new data is informed; the MBI driver software module reads the new data from the MBI protocol chip RAM and temporarily stores the new data in a DDR buffer area, and an application software module queries and reads the new data through a related function interface of the MBI driver software module.

[0019] The second aspect is a multi-channel MBI real-time processing method based on an SMP mode.

[0020] The embodiment of the application provides a multi-channel MBI real-time processing method based on an SMP mode, which is applied to the multi-channel MBI real-time processing architecture in the first aspect, and the multi-channel MBI real-time processing architecture sends a message data stream as follows: an application software module calls a related interface in an MBI driver software module to write to-be-sent data into an MBI protocol chip RAM, and the MBI protocol chip sends the data to the MBI bus according to its own scheduling logic.

[0021] The third aspect is a multi-channel MBI real-time processing method based on an SMP mode.

[0022] The embodiment of the application provides a multi-channel MBI real-time processing method based on an SMP mode, which is applied to the multi-channel MBI real-time processing architecture in the first aspect, and the multi-channel MBI real-time processing architecture receives a message data stream as follows: after the MBI protocol chip receives new data from the MBI bus, the MBI driver software module is notified through a message interrupt in the RT mode and the BM mode, and the offset address of the new data is informed; the MBI driver software module reads the new data from the MBI protocol chip RAM and temporarily stores the new data in a DDR buffer area, and an application software module queries and reads the new data through a related function interface of the MBI driver software module.

[0023] The multi-channel MBI real-time processing method based on the SMP mode provided by the application only needs one multi-core CPU, does not need N-channel FPGA chips, can greatly reduce the hardware cost, and directly exchanges the protocol chip data to the CPU, does not need to pass through the FPGA double port, reduces the data transmission link, improves the MBI real-time performance and the system reliability, and reduces the MBI driver software to one, and greatly reduces the maintenance amount. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1This is a schematic diagram of a traditional MBI data processing system architecture;

[0025] Figure 2 A schematic diagram of the traditional MBI message sending data flow;

[0026] Figure 3 A schematic diagram of the traditional MBI message receiving data stream;

[0027] Figure 4 Schematic diagram of the new MBI data processing system architecture;

[0028] Figure 5 A schematic diagram of the new MBI task and interrupt multi-core allocation;

[0029] Figure 6 A schematic diagram of the new MBI message sending data stream;

[0030] Figure 7 A schematic diagram of the new MBI message receiving data stream;

[0031] Figure 8 MBI driver software RT interrupt handling flowchart;

[0032] Figure 9 MBI driver software BM interrupt handling flowchart;

[0033] Figure 10 MBI application software processing flowchart. Detailed Implementation

[0034] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the traditional MBI hardware logic architecture is typically divided into a main control module and a multi-bus interface module based on module function. On the multi-bus interface module, each MBI is connected to an MBI protocol chip, and each MBI protocol chip is connected to an FPGA device. If there are N MBIs, then N MBI protocol chips and N FPGAs are required. A dual-port RAM is allocated within the FPGA as space for data exchange between the main control module and the multi-bus interface module. The MicroBlaze IP core within the FPGA accesses the dual-port RAM via the AXI bus, while the main control module CPU accesses the dual-port RAM via PCI / PCIe.

[0036] like Figure 1 As shown, the traditional MBI software architecture consists of three parts: application software, MBI driver software, and MBI transmission software.

[0037] The application software runs in the double data rate synchronous dynamic random access memory (DDR) of the master module, and the application software part function will specifically process the MBI data, including recording, response, etc.

[0038] The MBI driving software also runs in the DDR of the master module. The driving software contains two functions as follows: first, providing function interface for the application software to realize the MBI related function of system design; second, accessing the dual-port RAM of the multi-bus interface module FPGA chip through PCI / PCIe to interact with the MBI transmission software data, to realize the specific command writing, state acquisition and data reading and writing.

[0039] The MBI transmission software runs in the MicroBlaze soft core in the multi-bus interface module FPGA chip. The transmission software contains the following functions: first, realizing the access to the protocol chip, mainly including the function initialization and data reading and writing of the data buffer, and then the protocol chip realizes the bus data transceiving of the protocol layer. Second, realizing the access to the dual-port RAM of the FPGA chip to interact with the MBI driving software, mainly including the command acquisition, state reporting and data reading and writing.

[0040] The traditional MBI communication data flow is divided into sending message data flow and receiving message data flow.

[0041] The sending message data flow is shown in Figure 2 The application software calls the related interface function in the MBI driving software to write the data to be sent into the FPGA dual-port RAM. The MBI transmission software periodically queries the dual-port RAM, finds the new data to be sent, reads it out and writes it into the RAM of the protocol chip, and the protocol chip timely sends the data to the GJB289A bus according to its own scheduling logic.

[0042] The receiving message data flow is shown in Figure 3 After the protocol chip receives the new data from the GJB289A bus, it stores the data in the RAM of the protocol chip. In the RT mode and the BM mode, the MBI transmission software is informed of the offset address of the new data by interrupt, and in the BC mode, the address is specified by the MBI transmission software in advance. Then the MBI transmission software reads the new data from the RAM of the protocol chip and writes it into the FPGA dual-port RAM. The application software queries and reads the new data through the related interface function of the MBI driving software.

[0043] The application provides a multi-channel MBI real-time processing method based on an SMP mode, which is used for real-time processing of multi-channel MBI data. The application cancels the FPGA chip on the hardware, and directly connects the multi-core CPU to the MBI protocol chip through a local bus. On the software, according to the MBI transmission and operation characteristics, the performance of the multi-core CPU is fully utilized, and the SMP mode is used to separately process the underlying interrupts and tasks related to the multi-channel MBI by m cores, and all interrupts and tasks of the peripherals other than the MBI (including application software tasks) cannot run on the m cores, but run on other cores. In this way, although the N-channel MBI interrupts are frequent, the CPU core performance is much higher than that of the FPGA, which fully meets the requirements of high real-time response and high data integrity, and does not affect the normal operation of the tasks or interrupts bound to other cores.

[0044] The MBI data processing system architecture of the application is shown in Figure 4

[0045] The multi-channel MBI data processing solution based on the SMP mode is shown in the figure. If the number of MBI channels is not large, the MBI protocol chip and the CPU can be directly arranged on the main control module on the hardware, and if the number of MBI channels is too large, the CPU can be arranged on the main control module, and the MBI protocol chip can be arranged on the multi-channel bus interface module. One MBI protocol chip is connected to each MBI, and if there are N MBI, there are N MBI protocol chips. The MBI protocol chips communicate with the CPU through the LocalBus.

[0046] The MBI software based on the SMP mode is composed of two parts, including application software and MBI driver software, both of which run in the DDR of the main control module.

[0047] The application software will periodically process the MBI data, including initialization, recording, response, etc.

[0048] The MBI driver software is the specific implementation of the underlying MBI protocol chip function initialization, state acquisition, command interaction, data read-write function, and provides a function interface to the MBI application software, so that the latter realizes the MBI related functions of the system design.

[0049] The premise of the MBI software based on the SMP mode is to reasonably allocate the CPU multi-core. As shown in Figure 5 The interrupts of the N-channel MBI protocol chip are allocated to m cores (i to j), and the m cores only process the underlying tasks related to the MBI. The interrupts of other peripherals are allocated to another n cores (a to b), and the n cores only process the tasks related to the application software and other driver software. In this way, the interrupts and tasks related to the MBI driver software and the interrupts and tasks related to other software run on different CPU cores, and do not interfere with each other, which guarantees the normal operation of the respective software functions.​

[0050] The MBI communication data flow based on the SMP mode is divided into a sending message data flow and a receiving message data flow.

[0051] The sending message data flow is as shown in FIG. 2. Figure 6 The application software calls the relevant interface in the MBI driver software to write the data to be sent into the RAM of the MBI protocol chip, and the MBI protocol chip sends the data to the bus in a timely manner according to the scheduling logic thereof.

[0052] The receiving message data flow is as shown in FIG. 3. Figure 7 In order to meet the high real-time response, after receiving the new data from the bus, the MBI protocol chip notifies the MBI driver software through the message interrupt in the RT mode and the BM mode, and informs the offset address of the new data. The MBI driver software reads out the new data from the RAM of the MBI protocol chip and temporarily stores the new data in the DDR buffer area, and the application software queries and reads the new data through the relevant function interface of the MBI driver software.

[0053] Embodiment

[0054] 1. Hardware logic structure of the use case

[0055] The use case takes the Zynq 7000 launched by Xilinx as a processing platform, and the Zynq 7000 has arm Cortex-9 dual cores: core 0 and core 1. The MBI has 5 paths, and the protocol chip is SM61864G3.

[0056] The hardware is divided into a master control module and a multi-path bus interface module according to the functional modules. The Zynq 7000 is arranged on the master control module, and the SM61864G3 protocol chip is arranged on the multi-path bus interface module. The MBI data on the protocol chip is transmitted to the Zynq 7000 through the LoalBus for processing.

[0057] 2. Software architecture of the use case

[0058] The software of the use case is composed of application software and MBI driver software, and runs on the vxWorks6.9 embedded operating system platform in the SMP mode.

[0059] The interrupt numbers corresponding to the 5-path MBI are 84, 85, 86, 87 and 88, and the 5-path MBI interrupts are bound to core 1 and the interrupts of other peripherals are bound to core 0 by setting the mpcore register of the Zynq 7000.

[0060] The 5-path MBI includes 1 path of RT and 4 paths of BM. Among them, the interrupt type in the RT mode is a message end interrupt, and the interrupt types in the BM mode include a command stack half-full interrupt, a command stack full interrupt and a time stamp rollover interrupt.

[0061] The MBI driver software task runs on core 1 and the application software task runs on core 0 through the taskCpuAffinitySet method.

[0062] 3. Use case communication data flow

[0063] 3.1 Power-on initialization

[0064] After power-on, the application software first performs MBI initialization, sets the working mode of the SM61864G3 protocol chip (1-way RT and 4-way BM) through the MBIInitialize initialization function provided by the MBI driver software, and performs interrupt hooking.

[0065] Then the application software calls the MBIGo start function to make the SM61864G3 protocol chip start normal work.

[0066] 3.2 Interrupt receiving

[0067] The SM61864G3 protocol chip will trigger an interrupt in the following cases: the end of an RT message, the half-fullness of a BM command stack, the fullness of a BM command stack, and the BM time tag rollover. The MBI driver software completes the processing of each interrupt.

[0068] After the RT interrupt is generated, the MBI driver software first disables the current RT interrupt, then acquires and parses the current message, performs corresponding processing according to different message types, and finally re-enables the current RT interrupt. The RT interrupt processing flow is as shown in Figure 8 .

[0069] After the BM interrupt is generated, the MBI driver software first disables the current BM interrupt, then acquires the interrupt register value to determine the cause of the BM interrupt. If it is a data rollover interrupt, the data stack pointer is updated. If it is a clock rollover interrupt, the time tag is updated. If it is a command stack half / fullness interrupt, the command area pointer is updated. Finally, the current BM interrupt is re-enabled. The BM interrupt processing flow is as shown in Figure 9 .

[0070] 3.3 Data receiving and sending

[0071] The data acquired by the MBI driver software interrupt are saved in the DDR buffer area. The application software will periodically call the MBI driver software function to receive, process, and send RT / BM data. As shown in Figure 10 .

[0072] The application software queries the MBI driver software every 10 ms to determine whether there is new monitoring data for the 4-way BM. If there is new data, storage operation is performed.

[0073] The application software inquires whether the RT has new data every 40 ms to the MBI driving software, if yes, carries out analysis, and writes version, state and other information into the SM61864G3 protocol chip through the MBI driving software sending function, and the protocol chip will send data to the GJB289A bus in time according to its own scheduling subsequently.

[0074] The application designs a new type of multi-channel MBI real-time processing method, which does not need multiple FPGA chips on the hardware, but only needs a multi-core CPU. In this way, the multi-core CPU can be directly connected with the MBI protocol chip through the local bus, and the MBI data can be directly acquired by the CPU without passing through the FPGA dual-port RAM. The MBI related software running on the FPGA is no longer needed on the software, the MBI bottom driving and other software related interrupts and tasks are run on different CPU cores in the SMP mode, and different cores process different interrupts and tasks. In this way, the problem of abnormal running scheduling of other software caused by frequent MBI interrupts is avoided, and the high real-time performance and high integrity of the MBI are perfectly guaranteed.

[0075] The multi-channel MBI real-time processing method based on the SMP mode of the application can fully exert the performance of the multi-core CPU, can significantly reduce the hardware cost, the driving software maintenance amount and the labor cost, and further improves the MBI transmission real-time performance and the whole system reliability. The method can be applied to the multi-core CPU (such as Zynq7000, P2020, etc.), and has a significant application prospect.

Claims

1. A multi-channel MBI real-time processing architecture based on SMP mode, characterized in that, The FPGA chip is eliminated in hardware, and the multi-core CPU is directly connected to the MBI protocol chip via LocalBus. The architecture includes: a main control module and a multi-bus interface module. The main control module contains a CPU processor, and the CPU processor loads an application software module and an MBI driver software module. The multi-bus interface module contains multiple MBI protocol chips, which communicate with the CPU processor via LocalBus and are connected to the MBI bus interface. The CPU processor is a multi-core processor. Interrupts and tasks related to the MBI driver software, as well as interrupts and tasks related to other software, run on different CPU cores. Several cores are configured to handle only low-level tasks related to MBI, thereby distributing the interrupts of multiple MBI protocol chips to the configured cores.

2. The multi-channel MBI real-time processing architecture based on SMP mode according to claim 1, characterized in that, The application software module processes the MBI data periodically; The MBI driver software module is a specific implementation of the MBI protocol chip's function initialization, status acquisition, command interaction, and data read / write functions.

3. The multi-channel MBI real-time processing architecture based on SMP mode according to claim 2, characterized in that, The MBI driver software module also provides function interfaces to the MBI application software, enabling the MBI application software to implement MBI-related functions.

4. The multi-channel MBI real-time processing architecture based on SMP mode according to claim 1, characterized in that, The message data stream of the multi-channel MBI real-time processing architecture is as follows: the application software module calls the relevant interface in the MBI driver software module to write the data to be sent into the RAM of the MBI protocol chip, and the MBI protocol chip sends the data to the MBI bus according to its own scheduling logic.

5. The multi-channel MBI real-time processing architecture based on SMP mode according to claim 1, characterized in that, The multi-channel MBI real-time processing architecture receives message data streams as follows: After the MBI protocol chip receives new data from the MBI bus, it notifies the MBI driver software module through message interrupt in RT mode and BM mode, and informs it of the offset address of the new data. After the MBI driver software module reads the new data from the MBI protocol chip RAM, it temporarily stores it in the DDR buffer. The application software module queries and reads the new data through the relevant function interfaces of the MBI driver software module.

6. A multi-channel MBI real-time processing method based on SMP mode, characterized in that, The method is applied to the multi-channel MBI real-time processing architecture as described in any one of claims 1-5, wherein the multi-channel MBI real-time processing architecture sends message data streams as follows: the application software module calls the relevant interface in the MBI driver software module to write the data to be sent into the RAM of the MBI protocol chip, and the MBI protocol chip sends the data to the MBI bus according to its own scheduling logic.

7. A multi-channel MBI real-time processing method based on SMP mode, characterized in that, The method is applied to the multi-channel MBI real-time processing architecture as described in any one of claims 1-5, wherein the multi-channel MBI real-time processing architecture receives message data streams as follows: after the MBI protocol chip receives new data from the MBI bus, it notifies the MBI driver software module through message interrupt in RT mode and BM mode, and informs it of the offset address of the new data. After the MBI driver software module reads the new data from the MBI protocol chip RAM, it temporarily stores it in the DDR buffer. The application software module queries and reads the new data through the relevant function interfaces of the MBI driver software module.

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