Level conversion circuit and driver circuit

Abstract

The present application discloses a level conversion circuit and a driving circuit. The circuit includes: a pulse modulation generator, a switching element and a pulse modulator-demodulator. The pulse modulation generator is used to receive a control signal and generate a first pulse modulation signal according to the rising edge of the control signal, and generate a second pulse modulation signal according to the falling edge of the control signal. The switching element is connected to the pulse modulation generator, and the switching element is used to realize on-off control under the action of the first pulse modulation signal and the second pulse modulation signal. The pulse modulator-demodulator is used to detect the on-time of the switching element, and demodulate the first pulse modulation signal or the second pulse modulation signal according to the on-time of the switching element to control the first output terminal and the second output terminal to output a driving signal, so that the logic of the driving signal output by the first output terminal and the control signal are the same or opposite. The present application realizes low-power level logic conversion of the control signal by pulse mode and only by controlling one switching element.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a level conversion circuit and a driving circuit. Background Art

[0002] As the switch of the power system, the power tube has many application scenarios. The important parameters of the power tube include switching frequency, current capacity, voltage resistance, etc. The voltage resistance of a power tube may reach 600V or even 1200V.

[0003] In half-bridge switching applications, the connection point between the high bridge and the low bridge is floating, such as Figure 1 As shown. In such applications, a type of driver chip for the power tube of this application has been spawned. This type of driver chip converts a low-voltage logic signal into a logic signal whose voltage can float to a high voltage, and controls the on and off of the peripheral high-voltage power tube. Figure 2 As shown, the control signal generated by the gate-level driver chip can control a power tube with a larger voltage range (for example, 0 to 600V), and logic level conversion is required at this time. Among them, the control signal is transmitted from the controller (such as a single-chip microcomputer, etc.), and the control signal is a voltage with a smaller voltage range (for example, 0 to 5V). Designing a level conversion circuit to convert low-voltage logic signals into high-voltage logic signals meets the power consumption and stability requirements of the output high-voltage logic signal during the logic conversion process, which is of great significance for half-bridge switch control. Summary of the invention

[0004] In view of this, the present invention aims to solve one of the problems in the related art at least to a certain extent. To this end, the purpose of the present application is to provide a level conversion circuit and a driving circuit.

[0005] A level conversion circuit according to an embodiment of the present application. The level conversion circuit includes a pulse modulation generator, a switch element and a pulse modulator-demodulator. The pulse modulation generator is used to receive a control signal and generate a first pulse modulation signal according to the rising edge of the control signal, and generate a second pulse modulation signal according to the falling edge of the control signal; the switch element is connected to the pulse modulation generator, and the switch element is used to realize on-off control under the action of the first pulse modulation signal and the second pulse modulation signal; the pulse modulator-demodulator is connected to the switch element, and the pulse modulator-demodulator is used to detect the on-time of the switch element, and demodulate the first pulse modulation signal or the second pulse modulation signal according to the on-time of the switch element to control the first output terminal and the second output terminal to output a drive signal, so that the drive signal output by the first output terminal is the same or opposite in logic to the control signal.

[0006] In some embodiments, the pulse width duration of the first pulse modulation signal is greater than the pulse width duration of the second pulse modulation signal.

[0007] In some embodiments, the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is greater than a first duration, so that the first output terminal is in a logic high state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is not greater than the first duration, so that the first output terminal is in a logic low state; or the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is greater than the first duration, so that the first output terminal is in a logic low state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is not greater than the first duration, so that the first output terminal is in a logic high state.

[0008] In some embodiments, the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is greater than a second time period, so that the first output terminal is in a logic high state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is not greater than a third time period, so that the first output terminal is in a logic low state; or the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is greater than the second time period, so that the first output terminal is in a logic low state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the conduction time of the switch element is not greater than the third time period, so that the first output terminal is in a logic high state; wherein the third time period is less than the second time period.

[0009] In some embodiments, the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the turn-on time of the switch element is in a first time interval, so that the first output terminal is in a logic high state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the turn-on time of the switch element is in a second time interval, so that the first output terminal is in a logic low state; or the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the turn-on time of the switch element is in a first time interval, so that the first output terminal is in a logic low state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the turn-on time of the switch element is in a second time interval, so that the first output terminal is in a logic high state; wherein the lower limit of the first time interval is greater than the upper limit of the second time interval.

[0010] In some embodiments, a pulse width duration of the first pulse modulation signal is greater than a pulse width duration of the second pulse modulation signal adjacent to the first pulse modulation signal.

[0011] In certain embodiments, the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the on-time of the switch element is greater than the last on-time, so that the first output terminal is in a logic high state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the on-time of the switch element is not greater than the last on-time, so that the first output terminal is in a logic low state; or the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the on-time of the switch element is greater than the last on-time, so that the first output terminal is in a logic low state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the on-time of the switch element is not greater than the last on-time, so that the first output terminal is in a logic high state.

[0012] In some embodiments, the number of pulses of the first pulse modulation signal within a preset time is greater than the number of pulses of the second pulse modulation signal within a preset time.

[0013] In some embodiments, the pulse modem is used to detect the number of times the switching element is turned on; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the number of times the switching element is turned on is greater than a first value, so that the first output terminal is in a logic high state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the number of times the switching element is turned on is not greater than a second value, so that the first output terminal is in a logic low state; or the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the number of times the switching element is turned on is greater than a first value, so that the first output terminal is in a logic low state; the pulse modem is used to control the first output terminal and the second output terminal to output the drive signal when the number of times the switching element is turned on is not greater than a second value, so that the first output terminal is in a logic high state; wherein the second value is less than or equal to the first value.

[0014] In some embodiments, the switch element includes a level conversion high-voltage tube, a high-voltage capacitor, and a coil for magnetic isolation.

[0015] The embodiment of the present application further provides a driving circuit. The driving circuit comprises a power tube and the level conversion circuit described in any one of the above embodiments; the gate of the power tube is connected to the first output terminal.

[0016] The level conversion circuit and driving circuit of the present application generate pulse modulation signals of a first pulse width and a second pulse width respectively according to the rising edge and the falling edge of the control signal in a pulse manner, so as to control the conduction of a switching element, and judge the logic level of the control signal and output the corresponding high-voltage logic level by detecting the conduction time of the switching element, thereby realizing low-power level logic conversion of the control signal.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a schematic diagram of the current power tube structure;

[0020] Figure 2 This is a schematic diagram of the logic level conversion circuit of the current gate-level driver chip;

[0021] Figure 3This is a schematic diagram of the core circuit of the current logic level conversion circuit;

[0022] Figure 4 is a schematic diagram of a logic level conversion circuit in the related art;

[0023] Figure 5 is a schematic diagram of a level conversion circuit of certain embodiments of the present application;

[0024] Figure 6 is a schematic diagram of a driving circuit of certain embodiments of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0026] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] See also Figure 3 , Figure 3 It is the core circuit of logic level conversion. The core circuit of logic level conversion includes level conversion high-voltage tube, level conversion high-voltage tube in high-voltage domain, load ( Figure 3 The load in the circuit is a resistor, for example), the power supply VB and logic processing unit in the high-voltage domain, VPMG is the output high-voltage logic signal, and VPMS is the ground reference of the high-voltage domain. The SHVG terminal of the level conversion high-voltage tube SHV is connected to the low-voltage logic signal, and the SHVS terminal is connected to the ground of the low-voltage domain. The voltage range of the input low-voltage logic signal may include: 0~3.3V, 0~5V, 0~15V, etc., which are not limited here.

[0031] Here we first determine a logical relationship as the basis for subsequent analysis, but it does not cover all situations. When the low-voltage logic signal inputs a low level, it is hoped that no matter what voltage VPMS is at (such as 0V, 100V, 600V, 1200V, etc.), VPMG-VPMS is equal to 0V; when the low-voltage logic signal inputs a high level, it is hoped that no matter what voltage VPMS is at (such as 0V, 100V, 600V, 1200V, etc.), the VPMG output is a high level relative to VPMS (such as 15V). This logic conversion relationship can be simply understood as: when the low-voltage logic signal inputs a logic low level, the corresponding VPMG is in a logic low state; when the low-voltage logic signal inputs a logic high level, the corresponding VPMG is in a logic high state.

[0032] In this logic conversion process, power consumption problems will arise. When the level conversion high-voltage tube SHV is turned on, the voltage of its drain terminal SHVD can reach several hundred volts. According to the IV characteristics of the level conversion high-voltage tube, the current at this time generally reaches the milliampere level, such as 10mA. During the period of low-voltage logic input logic high level, the current of the level conversion high-voltage tube will continue to exist. Assuming that the logic high level duty cycle of the low-voltage logic signal is 90%, assuming that the drain terminal SHVD voltage of the level conversion high-voltage tube is 400V, and the conduction current is 10mA, it can be calculated that the power of the level conversion high-voltage tube is 400V*10mA*90%=3.6W. The power of the level conversion high-voltage tube is 3.6W, and the power loss is too large. On the one hand, it leads to low power conversion rate. On the other hand, the power loss of the level conversion high-voltage tube is too large, which will cause the level conversion high-voltage tube to heat up, and then lead to poor reliability of the high-voltage logic signal output by the logic level conversion circuit. Therefore, it is necessary to reduce this power loss.

[0033] In the related technical solutions, the logic level conversion method for reducing power loss includes, for example, Figure 4 As shown, by identifying the rising and falling edges of the low-voltage logic signal, short valid pulses (SET pulse, RST pulse) are generated respectively, and the corresponding level conversion high-voltage tubes are turned on respectively. After processing, they enter the RS trigger. When the SET pulse enters the RS trigger, the RS trigger is set; when the RST pulse enters the RS trigger, the RS trigger is reset. In this way, the low-voltage logic signal HIN can be restored at the output end of the RS trigger, and logic conversion is also performed at the same time.

[0034] Because the level conversion high-voltage tube is turned on by a short effective pulse, the power consumption is only related to the width of the effective pulse, and has nothing to do with the high-level duty cycle of the actual low-voltage logic signal. Assuming that the logic high duty cycle of the low-voltage logic signal is 90% (cycle 0.1ms), assuming that the drain SHVD voltage of the level conversion high-voltage tube is 400V, the on-current is 10mA, and the effective pulse width is 300ns. Then its power is: 400V*10mA*2*(300ns / 0.1ms)=24mW. Compared with the previous 3.6W, the power is only 6.7 thousandths.

[0035] Figure 4 The problems with the logic level conversion method shown are: (1) two level conversion high-voltage tubes are required; because the high-voltage tubes need to withstand voltages of several hundred volts, their area is relatively large; (2) when a level conversion high-voltage tube is working, the change in the peripheral voltage may cause another level conversion high-voltage tube to be mistakenly turned on, which is called common-mode interference, and thus requires additional processing circuits and risks.

[0036] See also Figure 5The present application provides a level conversion circuit 100 . The level conversion circuit 100 includes a pulse modulation generator 110 , a switch element 120 and a pulse modulator 130 .

[0037] The pulse modulation generator 110 is used to receive a control signal and generate a first pulse modulation signal according to the rising edge of the control signal, and generate a second pulse modulation signal according to the falling edge of the control signal. The control signal includes a low-voltage logic signal. The control signal can be transmitted from a controller (such as a single-chip microcomputer, etc.), and the control signal is a voltage in a smaller voltage range (such as 0 to 5V).

[0038] The switch element 120 is connected to the pulse modulation generator 110 , and the switch element 120 is used to realize on-off control under the effects of the first pulse modulation signal and the second pulse modulation signal.

[0039] The pulse modem 130 is connected to the switch element 120. The pulse modem 130 is used to detect the conduction time of the switch element 120, and demodulate the first pulse modulation signal or the second pulse modulation signal according to the conduction time of the switch element 120 to control the first output terminal 1 and the second output terminal 2 to output the driving signal, so that the logic of the driving signal output by the first output terminal is the same or opposite to the control signal, so that the first output terminal 1 can restore the logic level of the received control signal, and also perform level logic conversion. Among them, the first output terminal 1 is equivalent to Figure 2 The VPMG output terminal in the second output terminal 2 is equivalent to Figure 2 VPMS output terminal in.

[0040] At this time, a detection node 121 is provided between the switch element 120 and the pulse modem 130, and the detection node 121 is used to detect the conduction time of the switch element 120. A first end of the detection node 121 is connected to the switch element 120, a second end of the detection node 121 is connected to the pulse modem 130, and a third end of the detection node 121 is connected to the load 140 and the high voltage power supply VB in sequence.

[0041] The level conversion circuit 100 of the present application uses a pulse method to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal, and only generates a pulse modulation signal of a first pulse width and a second pulse width through the rising edge and the falling edge of the control signal to control a switch element 120, so that the switch element 120 is only turned on at the rising edge and the falling edge of the control signal, the power loss of the switch element 120 is reduced, and the level conversion high-voltage tube can be prevented from overheating due to excessive power. The pulse modulation signal can be demodulated by detecting the on-time of the switch element 120 to achieve low-power level logic conversion of the control signal, thereby ensuring the reliability of the output high-voltage logic signal.

[0042] In addition, since there is only one switch element 120 in the level conversion circuit 100 , there is no common mode interference problem caused by two switch elements 120 , and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0043] The switch element 120 may be a level conversion high voltage tube, a high voltage capacitor, and a magnetic isolation coil. The present application takes the switch element 120 as a level conversion high voltage tube 122 as an example for description.

[0044] When the switch element 120 is a level conversion high voltage tube 122, the gate SHVG of the level conversion high voltage tube 122 is connected to the pulse modulation generator 110, the first pole SHVD of the level conversion high voltage tube 122 is connected to the detection node 121, and the second pole SHVS of the level conversion high voltage tube 122 is grounded. That is, there is only one level conversion high voltage tube 122 in the level conversion circuit 100 of the present application, and there is no common mode interference problem caused by two level conversion high voltage tubes 122, and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0045] The pulse width duration of the first pulse modulation signal is greater than the pulse width duration of the second pulse modulation signal. For example, the pulse width duration of the first pulse modulation signal is 150ns, and the pulse width duration of the second pulse modulation signal is 50ns. That is, the pulse width duration of the first pulse modulation signal is different from the pulse width duration of the second pulse modulation signal, and the time widths of the two pulse modulation signals are different.

[0046] When the on-time of the switch element 120 is detected in the high voltage domain through the detection node 121, the detection can be performed through a pre-set time width sampling point Ts, and the first time length T1 is the time length corresponding to the time width sampling point Ts. The detection method of setting a time width sampling point to detect the on-time of the switch element 120 is simple and easy to execute.

[0047] When the pulse modulation signal time corresponding to the low-voltage logic signal at the rising edge is long, and the pulse modulation signal time corresponding to the low-voltage logic signal at the falling edge is short, that is, when the low-voltage logic signal is at the rising edge, the on-time of the switch element 120 corresponding to the low-voltage logic signal is long, and when the low-voltage logic signal is at the falling edge, the on-time of the switch element 120 corresponding to the low-voltage logic signal is short, that is, when the logic of the drive signal and the control signal output at the first output terminal 1 are the same, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the drive signal when the on-time of the switch element 120 is greater than the first time length T1, so that the first output terminal 1 is in a logic high state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the drive signal when the on-time of the switch element 120 is not greater than the first time length T1, so that the first output terminal 1 is in a logic low state. That is, when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is greater than the first time length T1, it is considered to be the rising edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is not greater than the first time length T1, it is considered to be the falling edge of the low-voltage logic signal.

[0048] When the logic of the driving signal and the control signal outputted from the first output terminal 1 are opposite, the pulse modem 130 can also be used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is greater than the first duration T1, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is not greater than the first duration T1, so that the first output terminal 1 is in a logic high state. That is, at this time, when the on-time of the level conversion high-voltage tube 122 of the switch element 120 is greater than the first duration T1, it is considered to be the rising edge of the low-voltage logic signal; when the on-time of the level conversion high-voltage tube 122 is not greater than the first duration T1, it is considered to be the falling edge of the low-voltage logic signal.

[0049] When the pulse modulation signal time corresponding to the low-voltage logic signal at the rising edge is short, and the pulse modulation signal time corresponding to the low-voltage logic signal at the falling edge is long, that is, when the low-voltage logic signal is at the rising edge, the corresponding on-time of the switch element 120 is short, and when the low-voltage logic signal is at the falling edge, the corresponding on-time of the switch element 120 is long, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is not greater than the first time length T1, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is greater than the first time length T1, so that the first output terminal 1 is in a logic high state. That is, when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is not greater than the first time length T1, it is considered to be the rising edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is greater than the first time length T1, it is considered to be the falling edge of the low-voltage logic signal.

[0050] When the logic of the driving signal and the control signal outputted from the first output terminal 1 are opposite, the pulse modem 130 can also be used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is greater than the first duration T1, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is not greater than the first duration T1, so that the first output terminal 1 is in a logic high state. That is, at this time, when the on-time of the level conversion high-voltage tube 122 of the switch element 120 is greater than the first duration T1, it is considered to be the rising edge of the low-voltage logic signal; when the on-time of the level conversion high-voltage tube 122 is not greater than the first duration T1, it is considered to be the falling edge of the low-voltage logic signal.

[0051] That is, the present application uses a pulse method to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal, and uses a level conversion high-voltage tube 122 to achieve low-power level logic conversion of the control signal. There is no need for two level conversion high-voltage tubes 122, which can ensure that the power loss of the level conversion high-voltage tube 122 is low.

[0052] In addition, since there is only one level conversion high voltage tube 122 in the level conversion circuit 100 , there is no common mode interference problem caused by two level conversion high voltage tubes 122 , and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0053] In addition, when detecting the conduction time of the switching element 120 in the high-voltage domain, two time-width sampling points Ts1 and Ts2 can be set for detection, where Ts1 < Ts2. The method of setting two time-width sampling points to detect the conduction time of the switching element 120 is simple and easy to implement, and the detected conduction time of the switching element 120 in the high-voltage domain is relatively accurate. The second duration T2 is the duration corresponding to the time-width sampling point Ts2, and the third duration T3 is the duration corresponding to the time-width sampling point Ts1.

[0054] At this time, when the low-voltage logic signal is at the rising edge, the pulse modulation signal has a long duration, and when the low-voltage logic signal is at the falling edge, the pulse modulation signal has a short duration. That is, when the conduction time of the switching element 120 corresponding to the rising edge of the low-voltage logic signal is long, and the conduction time of the switching element 120 corresponding to the falling edge of the low-voltage logic signal is short. That is, when the logic of the drive signal and the control signal output from the first output terminal 1 is the same, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the conduction time of the switching element 120 is greater than the second duration T2, so that the first output terminal 1 is in a logic high state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the conduction time of the switching element 120 is not greater than the third duration T3, so that the first output terminal 1 is in a logic low state, and the third duration T3 is less than the second duration T2.

[0055] When the logic of the drive signal and the control signal output from the first output terminal 1 is opposite, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the conduction time of the switching element 120 is greater than the second duration T2, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the conduction time of the switching element 120 is not greater than the third duration T3, so that the first output terminal 1 is in a logic high state. Among them, the third duration T3 is less than the second duration T2.

[0056] It can be understood that when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is greater than the second duration T2, it is considered to be the rising edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is not greater than the third duration T3, it is considered to be the falling edge of the low-voltage logic signal. Alternatively, when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is greater than the second duration T2, it is considered to be the falling edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is not greater than the third duration T3, it is considered to be the rising edge of the low-voltage logic signal. That is, the present application uses a pulse to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal, and a level conversion high-voltage tube 122 can be used to achieve low-power level logic conversion of the control signal, without two level conversion high-voltage tubes 122, which can ensure that the power loss of the level conversion high-voltage tube 122 is low.

[0057] In addition, since there is only one level conversion high voltage tube 122 in the level conversion circuit 100 , there is no common mode interference problem caused by two level conversion high voltage tubes 122 , and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0058] In addition, when detecting the conduction time of the switch element 120 in the high-voltage domain, multiple time width sampling points can also be set for detection. For example, the multiple time width sampling points include 4, namely Tsd1, Tsd2, Tsd3 and Tsd4, wherein the duration corresponding to the time width sampling point Tsd2 is greater than the duration corresponding to the time width sampling point Tsd1, the duration corresponding to the time width sampling point Tsd3 is greater than the duration corresponding to the time width sampling point Tsd2, and the duration corresponding to the time width sampling point Tsd4 is greater than the duration corresponding to the time width sampling point Tsd3. It can be understood that the present application uses a detection method for detecting the conduction time of the switch element 120 by setting multiple time width sampling points, so that the conduction time of the high-voltage domain detection switch element 120 obtained by detection can be more accurate.

[0059] At this time, when the low-voltage logic signal is at a rising edge, the corresponding pulse modulation signal time is long, and when the low-voltage logic signal is at a falling edge, the corresponding pulse modulation signal time is short, that is, when the low-voltage logic signal is at a rising edge, the corresponding on-time of the switch element 120 is long, and when the low-voltage logic signal is at a falling edge, the corresponding on-time of the switch element 120 is short, that is, when the logic of the driving signal and the control signal output at the first output terminal 1 are the same, the pulse modem 130 is used to switch the switch element 120 when the on-time is in the first time zone. When the on time of the switch element 120 is in the second time interval (Tsd1-Tsd2), the first output terminal 1 and the second output terminal 2 are controlled to output a driving signal, so that the first output terminal 1 is in a logic high state; the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a driving signal, so that the first output terminal 1 is in a logic low state, and the lower limit Tsd3 of the first time interval (Tsd3-Tsd4) is greater than the upper limit Tsd2 of the second time interval (Tsd1-Tsd2).

[0060] When the logic of the driving signal and the control signal outputted from the first output terminal 1 are opposite, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the conduction time of the switch element 120 is in the first time interval (Tsd3-Tsd4), so that the first output terminal is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the conduction time of the switch element 120 is in the second time interval (Tsd1-Tsd2), so that the first output terminal 1 is in a logic high state. The lower limit of the first time interval (Tsd3-Tsd4) is greater than the upper limit of the second time interval (Tsd1-Tsd2).

[0061] That is, when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is in the first time interval (Tsd3-Tsd4), it is considered to be the falling edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is in the second time interval (Tsd1-Tsd2), it is considered to be the rising edge of the low-voltage logic signal. Alternatively, when the conduction time of the level conversion high-voltage tube 122 of the switch element 120 is in the first time interval (Tsd3-Tsd4), it is considered to be the rising edge of the low-voltage logic signal; when the conduction time of the level conversion high-voltage tube 122 is in the second time interval (Tsd1-Tsd2), it is considered to be the falling edge of the low-voltage logic signal. The present application uses a pulse method to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal. A level conversion high-voltage tube 122 can be used to achieve low-power level logic conversion of the control signal. No two level conversion high-voltage tubes 122 are required, which can ensure that the power loss of the level conversion high-voltage tube 122 is low.

[0062] In addition, since there is only one level conversion high voltage tube 122 in the level conversion circuit 100 , there is no common mode interference problem caused by two level conversion high voltage tubes 122 , and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0063] The present application can use the above-mentioned setting of the time sampling point to use the absolute time width as the standard for judging whether the low-voltage logic signal is at the rising edge and the falling edge, and can also use the comparison between any two adjacent pulse widths as the standard for judging whether the low-voltage logic signal is at the rising edge and the falling edge.

[0064] Specifically, the pulse width duration of the first pulse modulation signal is greater than the pulse width duration of the second pulse modulation signal adjacent to the first pulse modulation signal.

[0065] When the logic of the driving signal and the control signal outputted from the first output terminal 1 are the same, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is greater than the last on-time, so that the first output terminal 1 is in a logic high state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is not greater than the last on-time, so that the first output terminal 1 is in a logic low state.

[0066] When the logic of the driving signal and the control signal outputted from the first output terminal 1 are opposite, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is greater than the last on-time, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output the driving signal when the on-time of the switch element 120 is not greater than the last on-time, so that the first output terminal 1 is in a logic high state

[0067] In addition, the conduction of the switching element 120 can be controlled according to the corresponding relationship between the rising and falling edges of the control signal and the number of pulses generated by the pulse modulation generator 110 within a preset time, thereby controlling the pulse modulation modem to be in a logic high state or a logic low state.

[0068] It can be understood that when the control signal is a rising edge, the number of pulses generated by the pulse modulation generator 110 within the preset time is greater than the number of pulses generated by the pulse modulation generator 110 when the control signal is a falling edge, that is, the number of pulses of the first pulse modulation signal within the preset time is greater than the number of pulses of the second pulse modulation signal within the preset time. The preset time can be 1us, 1.1us, 1.2us, 1.3us, 1.4us, 1.5us, 1.6us, 1.7us, 1.8us, 2us or other values, which are not limited here.

[0069] For example, when the preset time is 1us, when the control signal is a rising edge, the pulse modulation generator 110 will generate 10 pulses within 1us, thereby controlling the switch element 120; when the control signal is a falling edge, the pulse modulation generator 110 will generate 5 pulses within the same 1us, thereby controlling the switch element 120.

[0070] At this time, the pulse modem 130 is used to detect the number of times the switch element 120 is turned on. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the number of times the switch element 120 is turned on is greater than the first value, so that the first output terminal 1 is in a logic high state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the number of times the switch element 120 is turned on is not greater than the second value, so that the first output terminal is in a logic low state. Alternatively, the pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the number of times the switch element 120 is turned on is greater than the first value, so that the first output terminal 1 is in a logic low state. The pulse modem 130 is used to control the first output terminal 1 and the second output terminal 2 to output a drive signal when the number of times the switch element 120 is not greater than the second value, so that the first output terminal 1 is in a logic high state. The second value is less than or equal to the first value.

[0071] Among them, the first value can be any natural number greater than or equal to 2 set by the user, and the second value can be any natural number less than or equal to the first value. For example, the first value and the second value can both be 2, or the first value can be 2 and the second value can be 1. There is no limitation here.

[0072] That is, when it is detected that the number of times the switch element 120 is turned on is greater than the first value, it is considered to be the rising edge of the low-voltage logic signal; when it is detected that the number of times the switch element 120 is turned on is not greater than the second value, it is considered to be the falling edge of the low-voltage logic signal. Alternatively, when it is detected that the number of times the switch element 120 is turned on is not greater than the first value, it is considered to be the rising edge of the low-voltage logic signal; when it is detected that the number of times the switch element 120 is turned on is greater than the second value, it is considered to be the falling edge of the low-voltage logic signal.

[0073] The present application uses a pulse method to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal. A level conversion high-voltage tube 122 can be used to achieve low-power level logic conversion of the control signal. No two level conversion high-voltage tubes 122 are required, which can ensure that the power loss of the level conversion high-voltage tube 122 is low.

[0074] In addition, since there is only one level conversion high voltage tube 122 in the level conversion circuit 100 , there is no common mode interference problem caused by two level conversion high voltage tubes 122 , and the occupied area of ​​the level conversion circuit 100 can also be reduced.

[0075] When the first output terminal 1 is in a logic high state, the voltage difference between the first output terminal 1 and the second output terminal 2 is 15V. When the first output terminal 1 is in a logic low state, the voltage difference between the first output terminal 1 and the second output terminal 2 is 0V. It can be understood that, in combination with Figure 2 It can be seen that when the voltage difference between the first output terminal 1 and the second output terminal 2 is 0V, that is, when the VPMG-VPMS voltage is equal to 0V, the switch element 120 in the level conversion circuit 100 is turned off; when the voltage difference between the first output terminal 1 and the second output terminal 2 is 15V, that is, when the VPMG-VPMS voltage is equal to 15V, the switch element 120 in the level conversion circuit 100 is turned on.

[0076] In this way, the switch element 120 in the level conversion circuit 100 of the present application is turned on only at the rising edge and the falling edge of the control signal, the power loss of the switch element 120 is reduced, and the level conversion high-voltage tube 122 can be prevented from overheating due to excessive power. The pulse modulation signal can be demodulated by detecting the on-time of the switch element 120 to achieve low-power level logic conversion of the control signal, thereby ensuring the reliability of the output high-voltage logic signal.

[0077] See also Figure 6The present application also provides a driving circuit 1000. The driving circuit 1000 includes the level conversion circuit 100 and the power tube 200 described in the above embodiment. The gate PMG of the power tube 200 is connected to the first output terminal 1. The structure of the level conversion circuit 100 is as described above and will not be repeated here.

[0078] The structure of the power tube 200 is as follows: Figure 6 As shown. The voltages at the PMD and PMS terminals may be below 0V, or may reach the withstand voltage of a high power tube, such as 600V or 1200V. The switching function of the power tube 200 is achieved by controlling the voltage difference between its gate PMG and source PMS. Figure 2 As shown, the voltage VPMG output by the level conversion circuit 100 controls the voltage of the gate PMG, and the voltage VPMS output by the level conversion circuit 100 controls the voltage of the source PMS. When the VPMG-VPMS voltage output by the level conversion circuit 100 is equal to 0V, the power tube 200 is turned off; when the VPMG-VPMS voltage output by the level conversion circuit 100 is equal to 15V, the power tube 200 is turned on.

[0079] The driving circuit 1000 has the following characteristics: the VS voltage can float in a larger range, such as 0-600V, where VS is the source voltage, but the VGS voltage is in a smaller range, such as 0-20V, where VGS is the gate voltage relative to the source. The driving circuit 1000 controls the on and off of the peripheral high-voltage power tube by converting a low-voltage logic signal into a logic signal whose voltage can float to a high voltage.

[0080] The level conversion circuit 100 in the driving circuit 1000 of the present application uses pulses to express the high level or low level (rising edge or falling edge) of the low-voltage logic signal, and only controls one switching element 120 to achieve low-power level logic conversion of the control signal.

[0081] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A level conversion circuit, characterized in that: include: A pulse modulation generator, configured to receive a control signal and generate a first pulse modulation signal according to a rising edge of the control signal, and generate a second pulse modulation signal according to a falling edge of the control signal; The duration of the pulse width of the first pulse modulation signal is greater than the duration of the pulse width of the second pulse modulation signal; A switch element, the switch element is connected to the pulse modulation generator, and the switch element is used to realize on-off control under the action of the first pulse modulation signal and the second pulse modulation signal; a pulse modem, the pulse modem being connected to the switch element, the pulse modem being used to detect the on-time of the switch element, and demodulating the first pulse modulation signal or the second pulse modulation signal according to the on-time of the switch element to control the first output end and the second output end to output a driving signal, so that the driving signal output by the first output end is the same as or opposite to the logic of the control signal; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is greater than the first time length, so that the first output terminal is in a logic high state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is not greater than the first time length, so that the first output terminal is in a logic low state; or The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is greater than the first time length, so that the first output terminal is in a logic low state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is not greater than a first time length, so that the first output terminal is in a logic high state.

2. The level conversion circuit according to claim 1, characterized in that: The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is greater than the second time length, so that the first output terminal is in a logic high state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is not greater than a third time length, so that the first output terminal is in a logic low state; or The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is greater than the second time length, so that the first output terminal is in a logic low state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is not greater than a third time length, so that the first output terminal is in a logic high state; The third duration is shorter than the second duration.

3. The level conversion circuit according to claim 1, characterized in that: The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is in the first time interval, so that the first output terminal is in a logic high state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is in the second time interval, so that the first output terminal is in a logic low state; or The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is in the first time interval, so that the first output terminal is in a logic low state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is in the second time interval, so that the first output terminal is in a logic high state; The lower limit of the first time interval is greater than the upper limit of the second time interval.

4. The level conversion circuit according to claim 1, characterized in that: A pulse width duration of the first pulse modulation signal is greater than a pulse width duration of the second pulse modulation signal adjacent to the first pulse modulation signal.

5. The level conversion circuit according to claim 4, characterized in that: The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is greater than the last conduction time, so that the first output terminal is in a logic high state; The pulse modem is used to control the first output terminal and the second output terminal to output the driving signal when the conduction time of the switch element is not greater than the last conduction time, so that the first output terminal is in a logic low state; or The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the on-time of the switch element is greater than the last on-time, so that the first output terminal is in a logic low state; The pulse modem is used for controlling the first output terminal and the second output terminal to output the driving signal when the on-time of the switch element is not greater than the last on-time, so that the first output terminal is in a logic high state.

6. The level conversion circuit according to claim 1, characterized in that: The number of pulses of the first pulse modulation signal within a preset time is greater than the number of pulses of the second pulse modulation signal within the preset time.

7. The level conversion circuit according to claim 6, characterized in that: The pulse modem is used to detect the number of times the switch element is turned on; The pulse modem is used to control the first output terminal and the second output terminal to output the driving signal when the conduction number is greater than a first value, so that the first output terminal is in a logic high state; The pulse modem is used to control the first output end and the second output end to output the driving signal when the conduction number is not greater than a second value, so that the first output end is in a logic low state; or The pulse modem is used to control the first output end and the second output end to output the driving signal when the conduction number is greater than a first value, so that the first output end is in a logic low state; The pulse modem is used to control the first output terminal and the second output terminal to output the driving signal when the conduction number is not greater than a second value, so that the first output terminal is in a logic high state; The second value is less than or equal to the first value.

8. The level conversion circuit according to claim 1, characterized in that: The switch element includes a level conversion high-voltage tube, a high-voltage capacitor and a coil for magnetic isolation.

9. A driving circuit, characterized in that: include: The level conversion circuit according to any one of claims 1 to 8; A power tube, wherein a gate of the power tube is connected to the first output end.

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