A hybrid integrated low-noise power circuit

Abstract

This invention relates to a hybrid integrated low-noise power circuit, comprising: a ground plane GND copper layer on the middle layer, and a high-frequency AC node L1-2 of inductor L1 in the blank space of the ground plane GND copper layer; an input Vin node L1-1 in the top layer is connected to the input terminal of inductor L1, and the other end of the inductor is connected to the SW terminal of controller N1 and connected to node L1-2; a diode V1 is provided in the bottom layer, the P terminal of which is connected to node L1-2, the output terminal of diode V1 is connected to capacitor C3, the other end of C3 is connected to the GND copper layer, the GND copper layer is connected to the GND of controller N1, and is also connected to the input GND terminal. The advantages of this invention are: the current flow loop through inductor L1 through three overlapping layers of Vin input is almost zero, greatly reducing the high-frequency magnetic flux variation and noise interference; at the same time, the high-frequency voltage variation nodes are enveloped by the ground plane copper layer (middle layer), greatly absorbing high-frequency noise spike voltages.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology in hybrid integrated circuit design, specifically a hybrid integrated low-noise power circuit. Background Technology

[0002] Hybrid integrated low-noise power circuit boards are widely used in signal processing, power supply design, and other technical fields. In low-noise power circuit boards, high-frequency power signal processing is often accompanied by significant noise. To reduce noise, in addition to noise reduction design in the circuit design itself, noise reduction design in the structural layout of the power circuit board is crucial.

[0003] A search using existing patent search tools revealed that invention application "A Power Circuit Board" (patent application number CN105592628A) discloses a power circuit board, such as... Figure 1 As shown, the circuit includes pins, bonding wires, power chips, resistors, diodes, driver chips, recesses, and a molding compound. Its key feature is the addition of recesses between the devices; three groups of power devices are placed within a "T"-shaped copper layer on the right side of the circuit board. The beneficial effects of this invention are: 1. With the same circuit board area and the same raw materials, this method of adding recesses effectively blocks the flow of solder paste and ensures more standardized positioning and spacing between devices, thus preventing short circuits. 2. It avoids short circuits caused by solder paste overflowing onto the chip surface and greatly improves production efficiency. This invention is beneficial for improving the manufacturing efficiency of power circuits and does not involve the optimization of circuit parameters.

[0004] A search using existing patent search tools revealed the following utility model patent: "Layout Structure of a Gain-Controllable Low-Noise Amplifier" (Patent Authorization Announcement CN211295102U). Figure 2 The diagram discloses a layout structure for a gain-controllable low-noise amplifier, comprising a first layout region, a second layout region, a third layout region, and a fourth layout region. The first, third, and fourth layout regions are connected to the second layout region. The first layout region is L-shaped. The second and third layout regions are arranged side-by-side inside the L-shape. The second layout region is adjacent to two right-angled sides of the inner side of the L-shape, and the third layout region is adjacent to one right-angled side of the inner side of the L-shape and the second layout region. A fourth layout region is located at the right angle between the second layout region and the inner side of the L-shape. This invention solves the problems of large amplifier layout and weak anti-interference capability while achieving gain controllability and low noise. However, this invention is a semiconductor bare-chip layout, which has a different design domain from the hybrid integrated circuit layout of this invention, and does not specifically address noise parameter reduction design.

[0005] A search using existing patent search tools revealed the utility model invention application "Layout Structure of Radio Frequency Low Noise Amplifier," application publication (Patent Application Publication CN205621731U). Figure 3 The diagram discloses a layout structure for a radio frequency low-noise amplifier (LNA), characterized by comprising a first layout region, a second layout region, a third layout region, a fourth layout region, a fifth layout region, a sixth layout region, a seventh layout region, an eighth layout region, and a ninth layout region. The second and third layout regions are located at the center, the first layout region is below the second and third layout regions, the eighth layout region is to the left of the second layout region, the ninth layout region is to the right of the third layout region, and the sixth layout region is above the eighth and second layout regions. The first, second, and sixth layout regions constitute a signal path, while the fifth, ninth, second, and eighth layout regions constitute a power path. This invention balances LNA performance, rationally allocates signal paths, optimizes layout, and reduces chip cost. This invention is a semiconductor bare chip layout, which has a different design domain from the hybrid integrated circuit layout of this invention. In addition, only the signal traces and power traces are perpendicular, which prevents power supply interference to signals. This is different from the layout layout noise reduction design technology of this invention. Summary of the Invention

[0006] The purpose of this invention is to provide a hybrid integrated low-noise power circuit that achieves high current output while reducing noise.

[0007] The technical solution adopted in this invention is as follows:

[0008] A hybrid integrated low-noise power circuit includes:

[0009] The middle layer is midlayer1, and a ground layer GND copper layer is fabricated on the middle layer. In the blank area of ​​the ground layer GND copper layer, a set of high-frequency AC nodes L1-2 of inductor L1 is fabricated, and node L1-2 leads to the bottom layer.

[0010] The top layer (toplayer) contains the power trace layout, power GND ground line, and sampling feedback circuit layer; the bottom layer (bottomlayer) contains the power trace and power GND ground line layer.

[0011] The top layer contains an inductor L1 and an SW terminal from the inductor L1 to the controller N1. The top layer also contains a node L1-1 that connects to the input Vin. Node L1-1 is connected to the input terminal of the inductor L1.

[0012] The bottom layer is the power trace and power GND ground layer. A rectifier diode V1 is provided in the bottom layer. The P terminal of V1 is connected to the corresponding node L1-2. The rectifier diode V1 is connected to the output terminal by capacitor C3, and the other end of C3 is connected to the GND terminal.

[0013] The specific connection relationships in this invention are as follows:

[0014] The inductor L1 is connected to the SW terminal of the N1 controller. The SW terminal is connected to the P terminal of the V1 rectifier diode in the ground plane through the intermediate layer L1-2 node. The N terminal of the V1 rectifier diode is connected to the Vo output terminal. The Vo output terminal is connected to the capacitor C3. The other end of the capacitor C3 is connected to the GND copper layer. The GND copper layer is connected to the GND of the N1 controller and is also connected to the input GND terminal.

[0015] The advantage of this invention is that the Vin input is connected to the SW terminal of the controller N1 via inductor L1 and the intermediate layer L1-2 node. That is, the controller's SW terminal connects to the intermediate layer L1-2 node, and then through L1-2 node to the P-terminal of the rectifier diode V1 in the bottom layer. The entire path is covered with a GND copper layer. From the rectifier diode V1 to the output terminal, the high-frequency noise component at the output terminal flows through the output capacitor C3 to the GND terminal, then to the ground copper layer (GND copper layer is present in the intermediate layer, top layer, and bottom layer), and finally to the controller ground layer. The current flow loop overlaps three layers, ensuring that the loop area is almost zero, greatly reducing the high-frequency magnetic flux variation and lowering noise interference. Simultaneously, the high-frequency voltage variation nodes are enveloped by ground copper layer (intermediate layer), significantly absorbing high-frequency noise spikes. This ensures that the output voltage noise is no greater than 20mV. p-p This is of great significance for reducing noise in power circuits. Attached Figure Description

[0016] The attached diagram is described below:

[0017] Appendix Figure 1 This is a diagram of the copper cladding and node surrounding layout of the midlayer 1 of this invention;

[0018] Appendix Figure 2 This is a diagram showing the top-level toplayer power trace layout, power ground trace, and sampling feedback circuit layout of the present invention.

[0019] Appendix Figure 3 This is a layout diagram of the bottom layer power traces and power ground lines of the present invention. Detailed Implementation

[0020] This invention provides a low-noise power layout and routing design, comprising:

[0021] middle layer midlayer1, such as Figure 1 As shown, the black area on the PCB is the ground plane GND copper layer. In the blank area of ​​the ground plane GND copper layer, a high-frequency AC node L1-2 of an inductor L1 is made. Node L1-2 leads to the bottom layer.

[0022] The top layer (toplayer) shows the power routing layout, power GND ground lines, and sampling feedback circuit layer; the bottom layer (bottomlayer) shows the power routing and power GND ground lines, as follows: Figure 2 and Figure 3 As shown;

[0023] The input Vin is connected to the SW terminal of the controller N1 via inductor L1, and then to the intermediate layer L1-2 node. This means the controller's SW terminal connects to the intermediate layer L1-2 node, and then through L1-2 node to the P-terminal of the rectifier diode V1 in the bottom layer. The entire path is protected by a copper ground plane (GND). From the rectifier diode V1 to the output, high-frequency noise components flow through the output capacitor C3 to the GND terminal, then to the copper ground plane (GND is present in the intermediate, top, and bottom layers), and finally to the controller ground. This three-layer overlap of the current flow path ensures a near-zero loop area, significantly reducing high-frequency magnetic flux variations and noise interference. Simultaneously, the copper ground plane (intermediate layer) at high-frequency voltage variation nodes greatly absorbs high-frequency noise spikes, ensuring the output voltage noise does not exceed 20mV. p-p .

[0024] The specific connection relationships in this invention are as follows:

[0025] The inductor L1 is connected to the SW terminal of the N1 controller. The SW terminal is connected to the P terminal of the V1 rectifier diode in the ground plane through the intermediate layer L1-2 node. The N terminal of the V1 rectifier diode is connected to the Vo output terminal. The Vo output terminal is connected to the capacitor C3. The other end of the capacitor C3 is connected to the GND copper layer. The GND copper layer is connected to the GND of the N1 controller and is also connected to the input GND terminal.

Claims

1. A hybrid integrated low-noise power circuit, characterized in that... include: a. Intermediate layer, on which a ground layer GND copper layer is formed. In the blank area of ​​the ground layer GND copper layer, a set of high-frequency AC nodes L1-2 of inductor L1 is formed, and node L1-2 leads to the bottom layer. b. Top layer, the top layer has inductor L1 and the SW terminal of controller N1 of inductor L1, the top layer also has node L1-1 connected to input Vin, node L1-1 is connected to the input terminal of inductor L1. c. Bottom layer: A rectifier diode V1 is provided in the bottom layer. The P terminal of V1 is connected to node L1-2. The output terminal of the rectifier diode V1 is connected to capacitor C3. The other end of capacitor C3 is connected to the GND copper layer. The inductor L1 is connected to the SW terminal of the N1 controller. The SW terminal is connected to the P terminal of the V1 rectifier diode in the ground plane through the intermediate layer L1-2 node. The N terminal of the V1 rectifier diode is connected to the Vo output terminal. The Vo output terminal is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to the GND copper layer. The GND copper layer is connected to the GND of the N1 controller and is also connected to the input GND terminal.

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