Semiconductor structure and method of forming the same, and electronic component

Abstract

This invention discloses a semiconductor structure, a method for forming the same, and electronic components. The method for forming the semiconductor structure includes: providing a semiconductor substrate; forming a mask layer comprising an SOG material layer, a SiON material layer, and a SOC material layer on the surface of the semiconductor substrate; and forming a photoresist layer on the surface of the mask layer. This invention adds a mask layer comprising an SOG material layer, a SiON material layer, and a SOC material layer between the photoresist and the silicon wafer. Subsequently, the mask layer is etched using a layer of photoresist as a mask to transfer the target pattern on the photoresist to the mask layer. The etching resistance of the mask layer is then used to etch the silicon wafer. During this process, the high resolution of the target pattern is maintained, thus improving the etching resistance without increasing the thickness of the photoresist film.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its formation method, as well as electronic components. Background Technology

[0002] Photolithography is a technique that uses light to transfer a pattern from a photomask onto a substrate using a photoresist (also known as a photoresist film). The main process is as follows: First, ultraviolet light passes through the photomask and irradiates the surface of the substrate coated with a thin film of photoresist, causing a chemical reaction in the exposed areas. Then, a development technique is used to dissolve and remove the photoresist from the exposed or unexposed areas (the former is called positive photoresist, and the latter is called negative photoresist), allowing the pattern on the photomask to be copied onto the photoresist film. Finally, an etching technique is used to transfer the pattern onto the substrate.

[0003] Therefore, photoresist needs to possess both high resolution and high etching resistance during the etching process. When etching a 3μm silicon wafer, if the photoresist thickness is too small, the photoresist layer is easily consumed excessively during subsequent etching, resulting in a lack of barrier properties during etching and affecting the structural performance of the semiconductor. To improve the etching resistance of the photoresist, the film thickness can be increased or the carbon content of the photoresist can be increased. However, these methods reduce the pattern resolution, making it impossible to resolve smaller patterns. In other words, the photoresist cannot simultaneously meet the requirements of etching resistance and high resolution. Summary of the Invention

[0004] This invention addresses the technical problem that existing single-layer photoresists cannot simultaneously meet the requirements of etch resistance and high resolution, and proposes a semiconductor structure, its formation method, and electronic components.

[0005] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, including:

[0006] S1: Provide a semiconductor substrate;

[0007] S2: A mask layer comprising an SOG material layer, a SiON material layer and a SOC material layer is formed on the surface of the semiconductor substrate;

[0008] S3: A photoresist layer is formed on the surface of the mask layer;

[0009] S4: The target pattern is formed on the photoresist layer by photolithography;

[0010] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0011] S6: Remove the photoresist layer;

[0012] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0013] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0014] In the above-described method for forming a semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.

[0015] Secondly, embodiments of this application provide a method for forming a semiconductor structure, including:

[0016] S1: Provide a semiconductor substrate,

[0017] S2: A mask layer comprising an APF material layer and a SOC material layer is formed on the surface of the semiconductor substrate;

[0018] S3: A photoresist layer is formed on the surface of the mask layer;

[0019] S4: The target pattern is formed on the photoresist layer by photolithography;

[0020] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0021] S6: Remove the photoresist layer;

[0022] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0023] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0024] The above-described method for forming a semiconductor structure, wherein step S2 includes:

[0025] S21: An APF material layer is formed on the surface of the semiconductor substrate;

[0026] S22: A SOC material layer is formed on the surface of the APF material layer.

[0027] In the above-described method for forming a semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.

[0028] Thirdly, embodiments of this application provide a method for forming a semiconductor structure, including:

[0029] S1: Provide a semiconductor substrate,

[0030] S2: A mask layer comprising an SOG material layer and a SOC material layer is formed on the surface of the semiconductor substrate;

[0031] S3: A photoresist layer is formed on the surface of the mask layer;

[0032] S4: The target pattern is formed on the photoresist layer by photolithography;

[0033] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0034] S6: Remove the photoresist layer;

[0035] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0036] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0037] The above-described method for forming a semiconductor structure, wherein step S2 includes:

[0038] S21: An SOG material layer is formed on the surface of the semiconductor substrate;

[0039] S22: A SOC material layer is formed on the surface of the SOG material layer.

[0040] In the above-described method for forming a semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.

[0041] Fourthly, embodiments of this application provide a semiconductor structure formed by the semiconductor structure forming method described in any of the preceding aspects.

[0042] Fifthly, embodiments of this application provide an electronic component, which includes the semiconductor structure described in the fourth aspect above.

[0043] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0044] This application adds an etch-resistant mask layer between the photoresist and the silicon wafer. The mask layer is etched using a photoresist with a thickness of 1.2μm to 5μm as a mask to transfer the target pattern on the photoresist to the mask layer. Then, the etch resistance of the mask layer is used to etch the silicon wafer. The high resolution of the pattern is maintained in the above process, thus improving the etch resistance without increasing the thickness of the photoresist. Attached Figure Description

[0045] Figure 1This is a cross-sectional view of a semiconductor structure in the prior art;

[0046] Figure 2 A schematic diagram of one step in the method for forming a semiconductor structure provided by the present invention;

[0047] Figure 3 The present invention provides a basis for Figure 2 A flowchart of step S2;

[0048] Figure 4 Provided by the present invention Figure 3 Cross-sectional view of the first type of semiconductor structure formed by the steps of forming the semiconductor structure;

[0049] Figure 5 A schematic diagram of another step in the method for forming a semiconductor structure provided by the present invention;

[0050] Figure 6 A cross-sectional view of the second semiconductor structure provided by the present invention;

[0051] Figure 7 A schematic diagram of another step in the method for forming a semiconductor structure provided by the present invention;

[0052] Figure 8 The present invention provides a basis for Figure 6 A flowchart of step S2;

[0053] Figure 9 Provided by the present invention Figure 7 Cross-sectional view of the third type of semiconductor structure formed corresponding to the steps in forming the semiconductor structure;

[0054] Figure 10 A schematic diagram of another step in the method for forming a semiconductor structure provided by the present invention;

[0055] Figure 11 The present invention provides a basis for Figure 9 A flowchart of step S2;

[0056] Figure 12 Provided by the present invention Figure 10 A cross-sectional view of the fourth type of semiconductor structure formed by the steps of forming the semiconductor structure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0058] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0059] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0060] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0061] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0062] like Figure 1 As shown, when etching a 3μm silicon wafer using a single layer of iline photoresist, the photoresist thickness is 1.2μm-5μm. Therefore, to prevent etching of the 3μm silicon wafer, the photoresist's etching resistance needs to be improved. This can be achieved by increasing the photoresist thickness or increasing the carbon content. However, increasing the film thickness or increasing the carbon content will reduce the resolution, resulting in insufficient pattern resolution and the inability to resolve smaller patterns. To ensure that both the photoresist's etching resistance and resolution meet the requirements simultaneously, this application proposes a semiconductor structure, a method for forming the same, and an electronic component.

[0063] Figure 2 A schematic diagram of one step of the method for forming a semiconductor structure provided by the present invention is shown below. Figure 2 As shown in the figure, this embodiment discloses a specific implementation of a method for forming a semiconductor structure (hereinafter referred to as the "method").

[0064] Specifically, the method disclosed in this embodiment mainly includes:

[0065] Step S1: Provide a semiconductor substrate;

[0066] Step S2: Form a mask layer comprising an SOG material layer, a SiON material layer and a SOC material layer on the surface of the semiconductor substrate;

[0067] Step S3: Form a photoresist layer on the surface of the mask layer;

[0068] In a specific implementation, the thickness of the semiconductor substrate is 3 μm; the thickness of the photoresist layer is 1.2 μm to 5 μm. In this embodiment, the semiconductor substrate is a silicon substrate. In other embodiments, the substrate material can also be other semiconductor materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate.

[0069] Furthermore, such as Figure 3 As shown, step S2 includes:

[0070] Step S21: Form an SOG material layer on the surface of the semiconductor substrate;

[0071] The SOG material layer refers to spin-on glass coating (SOG), which possesses corrosion resistance and planarity, and is a major localized planarization technology in semiconductor manufacturing. Specifically, SOG involves uniformly coating a liquid solvent containing dielectric material onto the wafer surface using a spin coating method to fill the voids in the deposited dielectric layer. Afterward, a heat treatment removes the solvent, leaving a cured dielectric material on the wafer surface that resembles silicon dioxide (SiO2).

[0072] Step S22: A SiON material layer is formed on the surface of the SOG material layer; wherein, SiON has very good corrosion resistance.

[0073] Step S23: Form a SOC material layer on the surface of the SiON material layer. The SOC material layer refers to spin-on carbon (SOC), a type of SiARC material, which has excellent etching resistance and planarization properties.

[0074] A cross-sectional view of the first semiconductor structure formed by the above steps is shown below. Figure 4 As shown, the photoresist layer can be formed on the SOC material layer by a process such as spin coating. In this embodiment, the SOC material layer provides a flat surface for the formation of the photoresist layer.

[0075] Furthermore, the formation order of the SOG material layer, SiON material layer, and SOC material layer can be adjusted according to the actual situation;

[0076] Optionally, step S2 may also include:

[0077] Step S211: Form a SOC material layer on the surface of the semiconductor substrate;

[0078] Step S212: Form a SiON material layer on the surface of the SOC material layer;

[0079] Step S213: Form an SOG material layer on the surface of the SiON material layer.

[0080] Optionally, step S2 may also include:

[0081] Step S221: Form a SiON material layer on the surface of the semiconductor substrate;

[0082] Step S222: Form a SOC material layer on the surface of the SiON material layer;

[0083] Step S223: Form an SOG material layer on the surface of the SOC material layer.

[0084] Optionally, step S2 may also include:

[0085] Step S231: Form an SOG material layer on the surface of the semiconductor substrate;

[0086] Step S232: Form a SOC material layer on the surface of the SOG material layer;

[0087] Step S233: Form a SiON material layer on the surface of the SOC material layer.

[0088] Optionally, step S2 may also include:

[0089] Step S241: Form a SiON material layer on the surface of the semiconductor substrate;

[0090] Step S242: Form an SOG material layer on the surface of the SiON material layer;

[0091] Step S243: Form a SOC material layer on the surface of the SOG material layer.

[0092] Optionally, step S2 may also include:

[0093] Step S251: Form a SOC material layer on the surface of the semiconductor substrate;

[0094] Step S252: Form an SOG material layer on the surface of the SOC material layer;

[0095] Step S253: Form a SiON material layer on the surface of the SOG material layer.

[0096] This embodiment utilizes the etching resistance of three materials: SOG, silicon oxynitride (SiON), and SOC, as well as the planarization function of SOG and SOC. Three layers of etching resistance are added between the silicon substrate and the photoresist, reducing the photoresist film thickness in the subsequent etching process and keeping the photoresist layer thickness between 1.2μm and 5μm. This enhances the etching resistance while increasing the pattern resolution, which is beneficial for resolving smaller patterns in the subsequent process.

[0097] Step S4: Form the target pattern on the photoresist layer using a photolithography process;

[0098] Specifically, the photoresist layer may contain, for example, a photosensitive material, which causes a change in chemical properties when the photoresist layer is exposed to light, and the target pattern can be formed on the photoresist by exposure and development.

[0099] Step S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0100] Step S6: Remove the photoresist layer.

[0101] Specifically, using a patterned photoresist layer as a mask, the target pattern is etched into the mask layer not covered by the photoresist layer. During etching, dry etching and / or wet etching processes can be used. Anisotropic dry etching is preferred, as its longitudinal etching rate is much higher than its transverse etching rate. This allows for highly accurate pattern transformation during the patterning of the mask layer, facilitating precise control of the mask layer's morphology. Etching gases include SF6, NF3, COS, Cl2, HBr, and fluorinated hydrocarbons with low carbon-fluorine ratios (CF4, CHF3). This etching process achieves an etching rate higher than the polymer deposition rate and good verticality of the etched lines. After the mask layer etching is complete, the photoresist layer can be removed using methods such as plasma ashing.

[0102] Step S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0103] Step S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0104] Specifically, using a patterned mask layer as a mask, grooves of the target pattern are etched into a semiconductor substrate not covered by the mask layer. The etching process used when etching the semiconductor substrate can be the dry etching process and / or wet etching process described in step S4 above.

[0105] In one embodiment of the present invention, combined with Figure 5 As shown, Figure 5 Another step of the method for forming a semiconductor structure provided by the present invention is illustrated; the method mainly includes:

[0106] S1: Provide a semiconductor substrate,

[0107] S2: A mask layer including an SOG material layer is formed on the surface of the semiconductor substrate;

[0108] S3: A photoresist layer is formed on the surface of the mask layer;

[0109] S4: The target pattern is formed on the photoresist layer by photolithography;

[0110] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0111] S6: Remove the photoresist layer;

[0112] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0113] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0114] The second semiconductor structure formed through the above steps is as follows: Figure 6 As shown; in this embodiment, the mask layer formed on the semiconductor substrate is an SOG material layer with etching resistance and planarization functions, and the photoresist layer can be formed on the SOG material layer by a process such as spin coating. The SOC material layer provides a planar surface for the formation of the photoresist layer.

[0115] In one embodiment of the present invention, combined with Figure 7 As shown, Figure 7 Another step of the method for forming a semiconductor structure provided by the present invention is illustrated; the method mainly includes:

[0116] S1: Provide a semiconductor substrate,

[0117] S2: A mask layer comprising an SOG material layer and a SOC material layer is formed on the surface of the semiconductor substrate;

[0118] S3: A photoresist layer is formed on the surface of the mask layer;

[0119] S4: The target pattern is formed on the photoresist layer by photolithography;

[0120] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0121] S6: Remove the photoresist layer;

[0122] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0123] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0124] Furthermore, in combination Figure 8 As shown, this is a method based on an embodiment of the present invention. Figure 7 A flowchart of step S2 includes:

[0125] Step S21: Form an SOG material layer on the surface of the semiconductor substrate;

[0126] Step S22: Form a SOC material layer on the surface of the SOG material layer.

[0127] The third semiconductor structure formed through the above steps is as follows: Figure 9 As shown, optionally, the formation order of the SOG material layer and the SOC material layer can be adjusted according to the actual situation; the mask layer is composed of an SOG material layer and a SOC material layer with corrosion resistance and planarization functions, and the photoresist layer can be formed on the SOC material layer by a process such as spin coating, wherein the SOC material layer provides a planar surface for the formation of the photoresist layer.

[0128] In one embodiment of the present invention, combined with Figure 10 As shown, Figure 10 Another schematic diagram of the method for forming a semiconductor structure provided by the present invention; including:

[0129] S1: Provide a semiconductor substrate,

[0130] S2: A mask layer comprising an APF material layer and a SOC material layer is formed on the surface of the semiconductor substrate;

[0131] S3: A photoresist layer is formed on the surface of the mask layer;

[0132] S4: The target pattern is formed on the photoresist layer by photolithography;

[0133] S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer;

[0134] S6: Remove the photoresist layer;

[0135] S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate;

[0136] S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

[0137] Furthermore, in combination Figure 11 The diagram shows a flowchart of another method for forming a semiconductor structure based on step S2, as provided in an embodiment of the present invention, which includes:

[0138] S21: An APF material layer is formed on the surface of the semiconductor substrate; wherein the APF material layer includes an advanced patterning film (APF) with planarization function and high corrosion resistance.

[0139] S22: A SOC material layer is formed on the surface of the APF material layer.

[0140] The fourth semiconductor structure formed through the above steps is as follows: Figure 12 As shown, in this embodiment, the mask layer consists of an APF material layer with corrosion resistance and planarization functions and a SOC material layer. The photoresist layer can be formed on the SOC material layer by a process such as spin coating. The SOC material layer provides a planar surface for the formation of the photoresist layer. Furthermore, the formation order of the APF material layer and the SOC material layer can be adjusted according to the actual situation.

[0141] Optionally, step S2 may also include:

[0142] S211: A SOC material layer is formed on the surface of the semiconductor substrate;

[0143] S212: An APF material layer is formed on the surface of the SOC material layer.

[0144] Embodiments of this application also provide a semiconductor structure formed by employing the semiconductor structure formation method described in any of the above embodiments.

[0145] Accordingly, embodiments of the present invention also provide an electronic component, including the semiconductor structure provided in any of the above embodiments.

[0146] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: S1: Provide a semiconductor substrate; S2: A mask layer comprising an SOG material layer, a SiON material layer and a SOC material layer is formed on the surface of the semiconductor substrate; An SOG material layer is formed on the surface of the semiconductor substrate; a SiON material layer is formed on the surface of the SOG material layer; and a SOC material layer is formed on the surface of the SiON material layer. S3: A photoresist layer is formed on the surface of the mask layer, the thickness of the photoresist layer being 1.2 μm to 5 μm; S4: The target pattern is formed on the photoresist layer by photolithography; S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer; S6: Remove the photoresist layer; S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate; S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

2. A method for forming a semiconductor structure, characterized in that, include: S1: Provide a semiconductor substrate, S2: A mask layer comprising an APF material layer and a SOC material layer is formed on the surface of the semiconductor substrate; An APF material layer is formed on the surface of the semiconductor substrate; a SOC material layer is formed on the surface of the APF material layer; S3: A photoresist layer is formed on the surface of the mask layer, the thickness of the photoresist layer being 1.2 μm to 5 μm; S4: The target pattern is formed on the photoresist layer by photolithography; S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer; S6: Remove the photoresist layer; S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate; S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

3. A method for forming a semiconductor structure, characterized in that, include: S1: Provide a semiconductor substrate, S2: A mask layer comprising an SOG material layer and a SOC material layer is formed on the surface of the semiconductor substrate; An SOG material layer is formed on the surface of the semiconductor substrate; a SOC material layer is formed on the surface of the SOG material layer. S3: A photoresist layer is formed on the surface of the mask layer, the thickness of the photoresist layer being 1.2 μm to 5 μm; S4: The target pattern is formed on the photoresist layer by photolithography; S5: Using the photoresist layer as a mask, etch the mask layer to transfer the target pattern to the mask layer; S6: Remove the photoresist layer; S7: Using the mask layer as a mask, etch the semiconductor substrate to etch the target pattern on the semiconductor substrate; S8: After etching the target pattern on the semiconductor substrate, remove the mask layer.

4. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1-3.

5. An electronic component, characterized in that, The electronic components include the semiconductor structure described in claim 4.

Images