A real-time digital channelization method for 8192 channels based on FPGA

Abstract

The present invention discloses a 8192-channel real-time digital channelization method based on FPGA, including sequentially performing first-level channelization, second-level channelization and third-level channelization on input signals. In order to meet the performance requirements of large-bandwidth multi-channel simultaneous reception, the method introduces a 32×32×8 three-level channelization calculation structure, and at the same time, data reorganization is achieved through each ping-pong BRAM module, and a sequential output method is adopted in the output timing, as well as multi-channel time division multiplexing of the FIR filter IP core, so that the requirements of large-bandwidth multi-channel real-time digital channelization are achieved within limited resources, and there is no need to cascade multiple FPGAs for processing, thereby reducing costs, system volume, and power consumption.

Description

Technical Field

[0001] The invention belongs to the field of communication, and in particular relates to an 8192-channel real-time digital channelization method implemented based on FPGA. Background Art

[0002] With the rapid development of radar and communication technology, there are a large number of radio equipment in the modern electronic warfare battlefield. The electromagnetic environment of the battlefield is inevitably accompanied by a large number of radio signals with different carrier frequencies, different modulation types, and different bandwidths. In the electronic countermeasure system under complex electromagnetic environment, the receiver is an important device for receiving the radio signals of the own side and detecting the enemy. In view of the problem of parallel reception of a large number of radio signals arriving at the same time, people have put forward higher requirements on the performance of the receiver.

[0003] Compared with traditional analog receivers, digital channelized receivers have the advantages of wide coverage frequency bandwidth, large dynamic range, and parallel signal processing. Currently, in the design of digital channelized receivers, DSP or FPGA is usually used as the development platform for channelized algorithms. However, under the requirements of large bandwidth and multi-channel parallel reception, the receiver will face high concurrent computing. Compared with DSP, FPGA with a natural parallel structure is more suitable as a platform for the implementation of real-time channelized processing.

[0004] At present, the preferred method in engineering for multi-channel parallel reception and processing of large bandwidth signals is to use FPGA to implement digital channelization algorithm structure, such as Figure 8 As shown in the figure, the algorithm structure uses polyphase filtering technology and parallel IDFT algorithm to achieve uniform digital channelization. In order to ensure high dynamic range, FPGA needs to ensure full precision processing during the entire channelization process, and then truncate and restore the output results after the IDFT calculation is completed, which will consume a lot of LUT and DSP resources. When the receiving bandwidth and the number of parallel channelization requirements are large, if directly using Figure 8 The channelized algorithm structure is designed, and the number of multiplications performed simultaneously will far exceed the number of DSP resources of the FPGA, which cannot meet the performance requirements of a single FPGA to achieve simultaneous reception of multiple channels. Therefore, multiple FPGAs have to be cascaded for collaborative processing, which will inevitably lead to a sharp increase in the size, power consumption and cost of the system, making it unsuitable for harsh working environments. Summary of the invention

[0005] The purpose of the present invention is to solve the problem raised in the background technology and to propose an 8192-channel real-time digital channelization method based on FPGA.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] The present invention provides an 8192-channel real-time digital channelization method based on FPGA, which comprises sequentially performing primary channelization, secondary channelization and tertiary channelization on input signals.

[0008] In the first-level channelization, the input signal is converted from 4 to 32 channels in serial-to-parallel mode, multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filter of 32 multi-phase filter groups for multi-phase filtering. It is then IQ deinterleaved according to the first-in-first-out principle to achieve IQ parallel output. Finally, after a 32-point IFFT operation, 32 channels are output to complete the first-level channelization.

[0009] During the secondary channelization, the 32 IQ data output by the primary channelization are input one by one to 32 pairs of first ping-pong BRAM modules at the same time to realize parallel write, polling and read operations. Then, the output results of each ping-pong BRAM module are multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filters of 32 multi-phase filter groups for multi-phase filtering. Then, IQ deinterleaving is performed according to the first-in-first-out principle to realize IQ parallel output. Finally, after a 32-point IFFT operation, 1024 channels are output in time-sharing to complete the secondary channelization.

[0010] During the third-level channelization, the 1024 IQ data output by the second-level channelization are respectively input into 8 pairs of second ping-pong BRAM modules to realize polling write and parallel read operations. Then, the output results of the 8 pairs of second ping-pong BRAM modules are multiplied by the rotation factor and input into 8 FIR filters of polyphase filters for polyphase filter processing. Finally, after an 8-point IFFT operation, 8192 channels are output in time-sharing mode, thereby completing the third-level channelization.

[0011] Preferably, the 32 channels of IQ data output by the first-level channelization are simultaneously inputted into 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence to implement a parallel write-polling-read operation, including:

[0012] Through the control of the write state machines of each first ping-pong BRAM module, the 32-way IQ data output by the first-level channelization are simultaneously written into the ping areas of 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and then the 32-way IQ data output by the first-level channelization are simultaneously written into the pong areas of 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and when writing into the pong areas of the 32 pairs of first ping-pong BRAM modules, the 32-way IQ data are complemented to complete the sign conversion operation.

[0013] Through the control of the read state machines of the first ping-pong BRAM modules, the data of each region in the 32 pairs of first ping-pong BRAM modules are read in sequence.

[0014] Preferably, the 1024 channels of IQ data output by the secondary channelization are respectively input into 8 pairs of second ping-pong BRAM modules to implement polling write and parallel read operations, including:

[0015] Through the control of the write state machines of each second ping-pong BRAM module, the 1024-channel IQ data output by the second-level channelization are respectively written into the ping areas of 8 pairs of second ping-pong BRAM modules, and then the 1024-channel IQ data output by the second-level channelization are respectively written into the pong areas of 8 pairs of second ping-pong BRAM modules. When writing into the pong areas of the 8 pairs of second ping-pong BRAM modules, the 1024-channel IQ data are complemented to complete the sign conversion operation.

[0016] Through the control of the read state machines of the second ping-pong BRAM modules, data of each region in the eight pairs of second ping-pong BRAM modules are read simultaneously.

[0017] Preferably, a read bandwidth of each of the first ping-pong BRAM module and the second ping-pong BRAM module is greater than or equal to a write bandwidth.

[0018] Preferably, the 32-point IFFT operation in the primary channelization and the secondary channelization includes:

[0019] A five-level butterfly operation is adopted. The first-level butterfly operation performs 16 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 8 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 4 8-point DFT operations in time-sharing and then outputs to the fourth-level butterfly operation. The fourth-level butterfly operation performs 2 16-point DFT operations in time-sharing and then outputs to the fifth-level butterfly operation. The fifth-level butterfly operation performs 1 32-point DFT operation and then outputs, thereby completing the 32-point IFFT operation.

[0020] Preferably, the 8-point IFFT operation in the three-level channelization includes:

[0021] A three-level butterfly operation is adopted. The first-level butterfly operation performs 4 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 2 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 1 8-point DFT operation and then outputs, thereby completing the 8-point IFFT operation.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] In order to meet the performance requirements of simultaneous reception of large-bandwidth multi-channels, this method introduces a 32×32×8 three-level channelized computing structure. At the same time, data is reorganized through each ping-pong BRAM module, and a sequential output method is adopted in the output timing, as well as multi-channel time-division multiplexing of the FIR filter IP core. The requirements of real-time digital channelization of large-bandwidth multi-channels are realized within limited resources, and there is no need to cascade multiple FPGAs for processing, thereby reducing costs and reducing system volume and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a module block diagram of the 8192-channel real-time digital channelization method implemented based on FPGA of the present invention;

[0025] Figure 2 It is a schematic diagram of the structure of each level of channelization of the present invention;

[0026] Figure 3 It is a schematic diagram of the output timing of the secondary channelization and the tertiary channelization of the present invention;

[0027] Figure 4 This is a schematic diagram of parallel write, poll and read of the first ping-pong BRAM module of the secondary channelization of the present invention;

[0028] Figure 5 A schematic diagram of polling and writing in parallel with reading of the second ping-pong BRAM module of the three-level channelization of the present invention;

[0029] Figure 6 It is a schematic diagram of input and output of a FIR filter for performing polyphase filter processing in the polyphase filter rent in the three-stage channelization of the present invention;

[0030] Figure 7 It is a schematic diagram of the timing structure of the first-level channelized 32-point IFFT operation of the present invention;

[0031] Figure 8 The invention is a digital channelization algorithm structure realized by using FPGA in the prior art. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] It should be noted that when a component is referred to as being "connected" to another component, it may be directly connected to the other component or there may be an intermediate component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] like Figure 1-7 As shown, a 8192-channel real-time digital channelization method based on FPGA includes sequentially performing primary channelization, secondary channelization and tertiary channelization on the input signal.

[0035] In this embodiment, Figure 1 As shown, the input is a 655.36MHz sampling rate and a 500MHz bandwidth. The first-level channelization outputs 32 time domain channels, each with a bandwidth of 20.48MHz. The second-level channelization outputs 1024 time domain channels, each with a bandwidth of 640kHz. The third-level channelization outputs 8192 time domain channels, each with a bandwidth of 80kHz.

[0036] It should be noted that the present invention realizes the function of 8192-channel real-time digital channelization on a single xc7vx690t FPGA. The design parameters of the FIR filter are shown in the following table:

[0037]

[0038] Taking the 16-bit ADC output signal as an example, the above table shows the key design parameters of each prototype filter in the algorithm implementation. It can be found from the above table that the output bit width of each filter is 32 bits, but in fact, because the filter coefficients are converted to Q format, the coefficients of each filter are magnified by a power of 2. We need to truncate the 32-bit bit width data of the filter output to obtain the true filtering result. However, the RF signal is usually very weak, and the signal input to the filter may not even reach a 5-bit signed number. The output result after filtering is a decimal of a few tenths of a decimal. If the output of the filter is divided and then rounded at this time, the output result will be "-1", "0" and "1". Therefore, it is not possible to directly perform division at the output end of the filter to restore the true filtering data. The truncation needs to be transferred to the final output position of each level of channelization operation. Therefore, the schematic diagram of the designed channelization structure at each level is as follows. Figure 2 As shown, the calculation results can be directly truncated to obtain the real data with high precision.

[0039] Step S1, during the first-level channelization, the input signal is converted from 4 to 32 channels in serial-to-parallel mode, multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filter of 32 polyphase filter groups for polyphase filtering. Then, IQ deinterleaving is performed according to the first-in-first-out principle to achieve IQ parallel output. Finally, after a 32-point IFFT operation, 32 channels are output to complete the first-level channelization.

[0040] Specifically, the 32-point IFFT operation in the first-level channelization includes:

[0041] A five-level butterfly operation is adopted. The first-level butterfly operation performs 16 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 8 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 4 8-point DFT operations and then outputs to the fourth-level butterfly operation. The fourth-level butterfly operation performs 2 16-point DFT operations and then outputs to the fifth-level butterfly operation. The fifth-level butterfly operation performs 1 32-point DFT operation and then outputs, thereby completing the 32-point IFFT operation.

[0042] Step S2, during the secondary channelization, the 32 IQ data output by the primary channelization are input one by one to 32 pairs of first ping-pong BRAM modules at the same time to realize parallel write polling read operations, and then the output results of each ping-pong BRAM module are multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filter of 32 polyphase filter groups for polyphase filtering processing, and then IQ deinterleaved according to the first-in-first-out principle to realize IQ parallel output, and finally after a 32-point IFFT operation, 1024 channels are output in time-sharing to complete the secondary channelization.

[0043] Specifically, Figure 4 As shown, the 32 channels of IQ data output by the first-level channelization are simultaneously input into 32 pairs of first ping-pong BRAM modules one by one to implement the parallel write-polling-read operation, including:

[0044] Through the control of the write state machines of each first ping-pong BRAM module, the 32-way IQ data output by the first-level channelization are simultaneously written into the ping areas of the 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and then the 32-way IQ data output by the first-level channelization are simultaneously written into the pong areas of the 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and when writing into the pong areas of the 32 pairs of first ping-pong BRAM modules, the 32-way IQ data are complemented to complete the sign conversion operation;

[0045] Through the control of the read state machines of the first ping-pong BRAM modules, the data of each region in the 32 pairs of first ping-pong BRAM modules are read in sequence.

[0046] In order to ensure that the first ping-pong BRAM module completes reading of all data before the next writing, the reading bandwidth of the first ping-pong BRAM module is greater than or equal to the writing bandwidth.

[0047] 32-point IFFT operation in secondary channelization, including:

[0048] A five-level butterfly operation is adopted. The first-level butterfly operation performs 16 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 8 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 4 8-point DFT operations in time-sharing and then outputs to the fourth-level butterfly operation. The fourth-level butterfly operation performs 2 16-point DFT operations in time-sharing and then outputs to the fifth-level butterfly operation. The fifth-level butterfly operation performs 1 32-point DFT operation and then outputs, thereby completing the 32-point IFFT operation.

[0049] The output timing of the secondary channelization is as follows Figure 3 As shown, the secondary channelization is to perform 32-channel channelization processing on the 32 channels output by the primary channelization, and the algorithm structure of the 32 channels in each secondary channelization is exactly the same. Therefore, the secondary channelization only needs to complete 32 channels of the same structure 32 times in one cycle of 640kHz, and output them in sequence.

[0050] In step S3, during the third-level channelization, the 1024 IQ data output by the second-level channelization are respectively input into 8 pairs of second ping-pong BRAM modules to implement polling write and parallel read operations, and then the output results of the 8 pairs of second ping-pong BRAM modules are multiplied by the rotation factor and input into 8 FIR filters of polyphase filters for polyphase filter processing, and finally, after an 8-point IFFT operation, 8192 channels are output in time-sharing, thereby completing the third-level channelization.

[0051] Specifically, Figure 5 As shown, the 1024 channels of IQ data output by the secondary channelization are respectively input into 8 pairs of second ping-pong BRAM modules to implement polling write and parallel read operations, including:

[0052] Through the control of the write state machines of the second ping-pong BRAM modules, the 1024-channel IQ data output by the second-level channelization are respectively written into the ping areas of the 8 pairs of second ping-pong BRAM modules, and then the 1024-channel IQ data output by the second-level channelization are respectively written into the pong areas of the 8 pairs of second ping-pong BRAM modules, and when writing into the pong areas of the 8 pairs of second ping-pong BRAM modules, the 1024-channel IQ data are complemented to complete the sign conversion operation;

[0053] Through the control of the read state machines of the second ping-pong BRAM modules, data of each region in the eight pairs of second ping-pong BRAM modules are read simultaneously.

[0054] In order to ensure that the second ping-pong BRAM module completes reading of all data before the next writing, the reading bandwidth of the second ping-pong BRAM module is greater than or equal to the writing bandwidth.

[0055] The 8-point IFFT operation in the three-level channelization includes:

[0056] A three-level butterfly operation is adopted. The first-level butterfly operation performs 4 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 2 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 1 8-point DFT operation and then outputs, thereby completing the 8-point IFFT operation.

[0057] The output timing of the three-level channelization is as follows Figure 3 As shown, according to the output timing of the two-level channelization, it can be obtained that the three-level channelization only needs to complete 1024 times of 8-way channelization of the same structure in one cycle of 80kHz, and the output is sequential.

[0058] like Figure 6 As shown in FIG. 1 , it is a schematic diagram of the input and output of the FIR filter of the polyphase filter group in the three-stage channelization for polyphase filter processing. The provided FIR filter IP core supports a maximum of 1024 multi-channel time division multiplexing functions. Therefore, the three-stage 8-channel channelization structure uses 8 pairs of IP cores to achieve the FIR filtering requirements of 1024 8-channel IQ signals. The input and output of the FIR filter of the polyphase filter group in the remaining first-stage channelization and second-stage channelization for polyphase filter processing are similar. Figure 6 , no more details.

[0059] like Figure 7 The following is a schematic diagram of the timing structure of the first-level channelized 32-point IFFT operation. The timing of the second-level channelized 32-point IFFT operation and the timing of the third-level channelized 8-point IFFT operation are similar. Figure 7 , no more details.

[0060] In order to meet the performance requirements of simultaneous reception of large-bandwidth multi-channels, this method introduces a 32×32×8 three-level channelized computing structure. At the same time, data is reorganized through each ping-pong BRAM module, and a sequential output method is adopted in the output timing, as well as multi-channel time-division multiplexing of the FIR filter IP core. The requirements of real-time digital channelization of large-bandwidth multi-channels are realized within limited resources, and there is no need to cascade multiple FPGAs for processing, thereby reducing costs and reducing system volume and power consumption.

[0061] In order to meet the performance requirements of simultaneous reception of large-bandwidth multi-channels, this method introduces a 32×32×8 three-level channelized computing structure. At the same time, data is reorganized through each ping-pong BRAM module, and a sequential output method is adopted in the output timing, as well as multi-channel time-division multiplexing of the FIR filter IP core, thus realizing the real-time digital channelization requirements of large-bandwidth multi-channels within limited resources.

[0062] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above-described embodiments only express the more specific and detailed embodiments described in this application, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this application, which all belong to the protection scope of this application. Therefore, the protection scope of the patent application shall be based on the attached claims.

Claims

1. A 8192-channel real-time digital channelization method based on FPGA, characterized by: The 8192-channel real-time digital channelization method based on FPGA includes: performing primary channelization, secondary channelization and tertiary channelization on the input signal in sequence; In the first-level channelization, the input signal is converted from 4 to 32 channels in serial-to-parallel mode, multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filter of 32 polyphase filter banks for polyphase filtering. Then, IQ deinterleaving is performed according to the first-in-first-out principle to achieve IQ parallel output. Finally, after a 32-point IFFT operation, 32 channels are output to complete the first-level channelization. During the secondary channelization, the 32 IQ data outputted by the primary channelization are inputted into 32 pairs of first ping-pong BRAM modules one by one to realize the parallel write polling read operation. Then, the output results of each ping-pong BRAM module are multiplied by the rotation factor, and then IQ interleaved according to the first-in-first-out principle and output to the FIR filter of 32 polyphase filter groups for polyphase filtering. Then, IQ deinterleaving is performed according to the first-in-first-out principle to realize IQ parallel output. Finally, after a 32-point IFFT operation, 1024 channels are outputted in time-sharing mode to complete the secondary channelization. In the case of three-level channelization, the 1024 IQ data outputted by the second-level channelization are respectively inputted into 8 pairs of second ping-pong BRAM modules to realize polling write and parallel read operations, and then the output results of the 8 pairs of second ping-pong BRAM modules are multiplied by the rotation factor and inputted into the FIR filter of 8 polyphase filters for polyphase filter processing, and finally, after the 8-point IFFT operation, 8192 channels are outputted in time-sharing, thereby completing the three-level channelization; The method of inputting 32 channels of IQ data outputted by the primary channelization into 32 pairs of first ping-pong BRAM modules one by one to realize the operation of parallel write, poll and read includes: Through the control of the write state machines of each first ping-pong BRAM module, the 32-way IQ data output by the first-level channelization are simultaneously written into the ping areas of the 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and then the 32-way IQ data output by the first-level channelization are simultaneously written into the pong areas of the 32 pairs of first ping-pong BRAM modules in a one-to-one correspondence, and when writing into the pong areas of the 32 pairs of first ping-pong BRAM modules, the 32-way IQ data are complemented to complete the sign conversion operation; Reading data of each region in 32 pairs of first ping-pong BRAM modules in sequence through the control of each first ping-pong BRAM module read state machine; The 1024-channel IQ data output by the secondary channelization are respectively inputted into 8 pairs of second ping-pong BRAM modules to implement polling write and parallel read operations, including: Through the control of the write state machines of the second ping-pong BRAM modules, the 1024-channel IQ data output by the second-level channelization are respectively written into the ping areas of the 8 pairs of second ping-pong BRAM modules, and then the 1024-channel IQ data output by the second-level channelization are respectively written into the pong areas of the 8 pairs of second ping-pong BRAM modules, and when writing into the pong areas of the 8 pairs of second ping-pong BRAM modules, the 1024-channel IQ data are complemented to complete the sign conversion operation; Through the control of the read state machines of the second ping-pong BRAM modules, data of each region in the eight pairs of second ping-pong BRAM modules are read simultaneously.

2. The 8192-channel real-time digital channelization method based on FPGA as claimed in claim 1, characterized in that: The read bandwidth of each of the first ping-pong BRAM module and the second ping-pong BRAM module is greater than or equal to the write bandwidth.

3. The 8192-channel real-time digital channelization method based on FPGA as claimed in claim 1, characterized in that: The 32-point IFFT operation in the primary channelization and the secondary channelization includes: A five-level butterfly operation is adopted. The first-level butterfly operation performs 16 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 8 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 4 8-point DFT operations in time-sharing and then outputs to the fourth-level butterfly operation. The fourth-level butterfly operation performs 2 16-point DFT operations in time-sharing and then outputs to the fifth-level butterfly operation. The fifth-level butterfly operation performs 1 32-point DFT operation and then outputs, thereby completing the 32-point IFFT operation.

4. The 8192-channel real-time digital channelization method based on FPGA as claimed in claim 1, characterized in that: The 8-point IFFT operation in the three-level channelization includes: A three-level butterfly operation is adopted. The first-level butterfly operation performs 4 2-point DFT operations and then outputs to the second-level butterfly operation. The second-level butterfly operation performs 2 4-point DFT operations and then outputs to the third-level butterfly operation. The third-level butterfly operation performs 1 8-point DFT operation and then outputs, thereby completing the 8-point IFFT operation.

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