Power Adjustment Method and Circuit

Abstract

The present invention discloses a power regulation method and circuit. The method comprises: obtaining a gear position analog value through a gear setting circuit of a controlled circuit; obtaining a level signal through a level setting circuit of the controlled circuit; and outputting a power regulation signal based on the magnitude of the gear position analog value and the level signal. The present invention doubles the adjustable gear positions of the controlled circuit, enabling multi-level power regulation using two I / O ports. The method has the advantages of low cost and high power regulation accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of driving power supplies, and in particular to a power regulation method and circuit. Background Art

[0002] As smart appliances become increasingly popular, especially lamps and electric heaters, they often use regulation circuits to adjust the power of their driver circuits to achieve adjustable effects, such as dimming and temperature control. Currently, there are many different types of regulation circuits on the market. Some regulation circuits with high regulation accuracy often suffer from complex circuit structures, occupy a large number of processor IO port resources, and lead to high costs. Meanwhile, some regulation circuits with low regulation accuracy, while lower in cost, suffer from low regulation accuracy, resulting in a poor user experience. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a power regulation method and circuit.

[0004] The technical solution adopted by the present invention to solve the technical problem is to construct a power regulation method for regulating the output power of a controlled circuit, comprising:

[0005] Acquiring a gear position analog value through a gear position setting circuit of the controlled circuit;

[0006] obtaining a level signal through a level setting circuit of the controlled circuit;

[0007] A power adjustment signal is output according to the size of the gear position analog quantity and the level signal.

[0008] Preferably, the gear setting circuit includes a plurality of gear setting units;

[0009] The gear setting units are sequentially connected in series to form a series chain; one end of the series chain is used to output the gear analog value, and the other end is grounded;

[0010] The configurable states of each of the gear setting units include a first state and a second state; each of the gear setting units outputs several gear analog quantities in different voltage value ranges through switching and coordination of the configurable states.

[0011] Preferably, the first state is a high-impedance state, and the second state is a low-impedance state;

[0012] The power regulation method further includes:

[0013] The impedance of each of the gear setting units when in the high-impedance state is set to decrease from large to small based on a preset proportional range.

[0014] Preferably, the preset ratio range is 0.47-0.52.

[0015] Preferably, the number of the gear setting units is 4.

[0016] Preferably, the step of outputting a power adjustment signal according to the size of the gear position analog quantity and the level signal includes:

[0017] Comparing the gear position analog value with gear position threshold data to confirm the gear position value of the gear position analog value; wherein the gear position threshold data includes a plurality of gear levels corresponding to the number of the voltage value ranges and comparison thresholds corresponding to each of the gear levels;

[0018] The power adjustment signal is set and output according to the gear value and the level signal.

[0019] Preferably, the step of comparing the gear position analog quantity with the gear position threshold data to confirm the gear position value of the gear position analog quantity includes:

[0020] The gear level corresponding to the comparison threshold value that is smaller than the gear analog value and closest in size is set as the gear value of the gear analog value.

[0021] Preferably, the step of setting and outputting the power adjustment signal according to the gear value and the level signal includes:

[0022] Dividing the adjustable range of the power adjustment signal into a first level interval and a second level interval;

[0023] Dividing the first level interval and the second level interval into a set number of interval blocks respectively, and assigning one-to-one correspondence between each of the gear levels and the boundary values of each of the interval blocks of the first level interval and the second level interval based on the size;

[0024] If the level signal is in the first level state, the output value of the power adjustment signal is set to a boundary value corresponding to the gear level that is the same as the gear value in the first level interval;

[0025] If the level signal is in the second level state, the output value of the power adjustment signal is set to a boundary value corresponding to the gear level that is the same as the gear value in the second level interval;

[0026] Output the set power adjustment signal.

[0027] Preferably, the power regulation method further includes:

[0028] Calculating theoretical gear position analog quantities corresponding to each gear level according to design parameters of the gear setting circuit;

[0029] The average value of the theoretical gear analog value corresponding to the gear level and the theoretical gear analog value of the next decreasing gear is set as the comparison threshold corresponding to the gear level.

[0030] The present invention also constructs a power regulation circuit, comprising:

[0031] The gear setting circuit is used to output the gear analog value;

[0032] a level setting circuit for generating a level signal;

[0033] A processor is connected to the gear setting circuit and the level setting circuit, and is used to output a power adjustment signal according to the size of the gear analog quantity and the level signal.

[0034] Preferably, the gear setting circuit includes a first resistor RP5, a second resistor RP7, a third resistor RP6, a fourth resistor RP9, a fifth resistor RP11, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4;

[0035] A first end of the first resistor RP5 is connected to a first DC voltage, a second end of the first resistor RP5 is connected to a gear position analog input end of the processor, and a second end of the first resistor RP5 is further connected to ground via the second resistor RP7, the third resistor RP6, the fourth resistor RP9, and the fifth resistor RP11 in sequence. The first switch S1 is connected in parallel with the second resistor RP7, the second switch S2 is connected in parallel with the third resistor RP6, the third switch S3 is connected in parallel with the fourth resistor RP9, and the fourth switch S4 is connected in parallel with the fifth resistor RP11.

[0036] By setting the on-off combination of the first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 , gear position analog quantities in different voltage value ranges can be output.

[0037] Preferably, the impedances of the second resistor RP7 , the third resistor RP6 , the fourth resistor RP9 and the fifth resistor RP11 are decreased from large to small based on a preset ratio range.

[0038] Preferably, the level setting circuit includes a sixth resistor RP16, a seventh resistor RP18 and a level setting unit for setting the level of the level signal;

[0039] The first end of the sixth resistor RP16 is connected to the output end of the level setting unit, the second end of the sixth resistor RP16 is connected to the level signal input end of the processor as the level signal output end, and the second end of the sixth resistor RP16 is also connected to the ground via the seventh resistor RP18.

[0040] By implementing the technical solution of the present invention, the gear analog quantity can be obtained through the gear setting circuit of the controlled circuit, and then the level signal can be obtained through the level setting circuit of the controlled circuit. Then, the power adjustment signal is output according to the size of the gear analog quantity and the level signal, thereby doubling the adjustable gear of the controlled circuit, which has the advantages of low cost and high power adjustment accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0042] Figure 1 is a schematic flow chart of a power regulation method in some embodiments of the present invention;

[0043] Figure 2 is a schematic diagram of the structure of the cascade chain in some embodiments of the present invention;

[0044] Figure 3 is a schematic structural diagram of a power regulation circuit in some embodiments of the present invention;

[0045] Figure 4 is a circuit diagram of a gear setting circuit in some embodiments of the present invention;

[0046] Figure 5 is a circuit diagram of a level setting circuit in some embodiments of the present invention. DETAILED DESCRIPTION

[0047] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0048] It should be noted that the flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all content and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0049] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor (3) devices and / or microcontroller devices.

[0050] refer to Figure 1FIG. 1 is a flow chart of a power regulation method provided by the present invention. The regulation method of this embodiment is applied to a processor of a controlled circuit to regulate the output power of the controlled circuit. The controlled circuit may be a driving power supply for an electrical appliance such as a lamp or an electric heater. In addition, the controlled circuit also includes a gear setting circuit and a level setting circuit. The power regulation method includes:

[0051] A gear position analog quantity is obtained through a gear setting circuit of the controlled circuit; a level signal is obtained through a level setting circuit of the controlled circuit; and a power adjustment signal is output according to the size of the gear position analog quantity and the level signal.

[0052] In this embodiment, the gear analog quantity is an analog voltage signal. The processor detects the size of the gear analog quantity through its IO port to determine the gear value, and each gear value corresponds to at least two power adjustment signals; then, the power adjustment signal corresponding to the gear value in the adjustment process is determined according to the level signal, thereby doubling the adjustable gear of the controlled circuit, so that the effect of multi-gear power adjustment can be achieved by using two IO ports. Not only does it occupy less IO port resources of the processor, but it also has high accuracy in determining the gear value corresponding to the gear analog quantity, thereby improving the power adjustment accuracy of the controlled circuit, and playing a positive role in reducing the development difficulty and cost of the controlled circuit.

[0053] In a preferred embodiment, Figure 2 As shown, the gear setting circuit includes a plurality of gear setting units. Each gear setting unit is sequentially connected in series to form a series chain 4; one end of the series chain 4 is used to output the gear analog quantity, and the other end is grounded; each gear setting unit can be set to a first state and a second state; each gear setting unit can output a gear analog quantity in a plurality of different voltage value ranges by switching and coordinating the settable states. In this embodiment, the first state and the second state can be states corresponding to different impedances or different voltage outputs. In other words, the state switching of each gear setting unit will cause the gear analog quantity to change in voltage. Therefore, the processor can set different gears by detecting the voltage value of the gear analog quantity. In addition, the more gear setting units there are, the more types of voltage value ranges of the gear analog quantity.

[0054] Furthermore, in a preferred embodiment, the first state is a high-impedance state, and the second state is a low-impedance state. Accordingly, the power regulation method further includes: setting the impedance of each gear setting unit in the high-impedance state to decrease from high to low based on a preset proportional range. In this embodiment, the low-impedance state is a state close to 0 ohms, and the impedance of each gear setting unit in the high-impedance state is set to decrease from high to low based on a preset proportional range. This maximizes the number of impedance combinations for each gear setting unit, thereby improving output power control accuracy. Furthermore, the impedance difference of each impedance combination is approximately equal, which facilitates accurate determination of the gear value corresponding to the gear analog quantity and reduces the hardware requirements of the gear setting circuit. Taking three gear setting units as an example, their high-impedance state impedances are 20 kilo-ohms, 10 kilo-ohms, and 5 kilo-ohms, respectively, and their low-impedance state impedances are all 0 ohms. Thus, each gear setting unit has a total of eight configurable high-impedance state impedance combinations, enabling eight gears of output power regulation for the controlled circuit. In addition, it should be noted that in this embodiment, the switching between the first state and the second state is a conversion of different impedances, so a pull-up voltage needs to be connected to the gear analog output end of the series chain 4, and the pull-up voltage can be implemented by a pull-up circuit.

[0055] In a specific embodiment, the high-impedance impedance setting of the gear setting unit can be achieved through resistors. In order to improve the flexibility of selecting resistors and to select resistors with standard impedance as much as possible to reduce costs, the preset ratio range can be 0.47-0.52.

[0056] Since the processor's IO port can detect a limited voltage range, the more types of voltage value ranges there are, the shorter the span of each voltage range will be. Also, due to the inevitable hardware errors in the gear setting unit, when determining the gear value based on the size of the gear analog quantity, the probability of misjudging the target gear value as the gear value adjacent to it increases, which ultimately leads to a decrease in the accuracy of the adjusted output power and a reduction in user experience. In order to ensure high-precision adjustment of the output power, in a preferred embodiment, the number of gear setting units can be 4.

[0057] Furthermore, in a preferred embodiment, the power adjustment signal can be output according to the size and level signal of the gear position analog quantity in the following manner:

[0058] The gear position analog value is compared with gear position threshold data to confirm the gear position value of the gear position analog value; wherein the gear position threshold data includes a number of gear levels corresponding to the number of voltage value ranges and a comparison threshold value corresponding to each gear level; and the output power adjustment signal is set according to the gear value and level signal. In this embodiment, the number of gear setting units is 4, and accordingly, the number of gear levels and comparison threshold values is 16.

[0059] In a specific embodiment, the gear value of the gear analog quantity can be confirmed by the following method:

[0060] The gear level corresponding to the comparison threshold value that is smaller than the gear analog value and closest in size is set as the gear value of the gear analog value. Specifically, assuming that the 16 comparison threshold values are 3.3V, 3.1V, 2.9V, ..., 0.3V, and correspond one-to-one with the 16 gear levels in an ascending manner (i.e., one-to-one with 0 gear, 1 gear, 2 gear, ..., 15 gear), the gear analog value is equal to 2.91V, then the comparison threshold values below 2.9V are all smaller than the gear analog value, and the comparison threshold value closest to 3.11V is 2.9V. Therefore, in this example, the gear value corresponding to the gear analog value is 2 gear.

[0061] Furthermore, in a specific embodiment, the output power adjustment signal can be set according to the gear value and the level signal in the following manner:

[0062] The adjustable range of the power regulation signal is divided into a first level interval and a second level interval; the first level interval and the second level interval are respectively divided into a set number of interval blocks, and each gear level is respectively corresponded to the boundary value of each interval block of the first level interval and the second level interval based on the size; if the level signal is in a first level state, the output setting value of the power regulation signal is set to the boundary value corresponding to the gear level with the same gear value in the first level interval; if the level signal is in a second level state, the output setting value of the power regulation signal is set to the boundary value corresponding to the gear level with the same gear value in the second level interval; and the set power regulation signal is output.

[0063] In this embodiment, the span range of the first level interval and the second level area can be determined based on the relationship between the output current of the controlled circuit and the actual effect. Taking LED lamps as an example, since the current and brightness of LED lamp beads are not linearly related, and the current gain coefficient will gradually decrease as it gradually increases, the first level interval can be 100%-53%, and the corresponding second level interval is 50%-22%.

[0064] Furthermore, in this embodiment, the set number of interval blocks is equal to the number of types of voltage value ranges minus one, that is, for an embodiment in which the number of types of voltage value ranges is 16, the set number is 15. In this way, the first-level interval and the second-level interval each obtain 16 boundary values, and then correspond one-to-one with the 16 gear levels based on size. Taking 16 boundary values and 16 gear levels as an example, the 16 boundary values are 100%, 97%, 94%, ..., 52%, and the 16 gear levels are 0, 1, 2, ..., 15, and the corresponding relationship is (100%, 0), (97%, 1), (94%, 2), ..., (52%, 0). It should be noted that in this example, the interval blocks are divided evenly, but in actual applications, the size (span) of each interval block can be customized as needed.

[0065] Furthermore, in this embodiment, the level signal is a digital signal. Therefore, the first level state and the second level state are high level and low level (or low level and high level) respectively, corresponding to the first level interval and the second level interval, so as to determine the level interval in which the power adjustment signal to be output is located by detecting the level of the level signal; taking the second level interval as an example, assuming that the correspondence between its boundary value and the gear level is (50%, 0 gear), (48%, 1 gear), (46%, 2 gear), ..., (22%, 0 gear), it includes 16 boundary values and 16 gear levels. When the level signal is in the second level state, the gear value corresponds to 2 gear. Therefore, in this example, the power adjustment signal is set to 46%. In addition, the method for judging high and low levels can be implemented by the method of the prior art.

[0066] Furthermore, in a preferred embodiment, the power regulation method further includes:

[0067] The theoretical gear analog quantity corresponding to each gear level is calculated according to the design parameters of the gear setting circuit; the average value of the theoretical gear analog quantity corresponding to the gear level and the theoretical gear analog quantity of the next decreasing gear is set as the comparison threshold corresponding to the gear level.

[0068] In this embodiment, the high-impedance state impedance setting of the gear setting unit in the gear setting circuit is set by a resistor, while the low-impedance state impedance is close to 0 ohm, and the gear analog value is positively correlated with the series chain 4 formed by the combination of the gear setting units. Taking the gear setting circuit as an example, in which the number of gear setting units is 4, the highest high-impedance state impedance of the 4 gear setting units is X ohms, the preset ratio range is 0.5, and the number of gear levels is 16, it can be seen that the high-impedance state impedances of the 4 gear setting units are X, 0.5X, 0.25X, and 0.1 respectively. 25X, then the impedance types obtained by the gear setting unit combination are 1.875X, 1.75X, 1.625X, ..., 0X (0 ohm) from large to small, which correspond to the 16 gear levels one by one, and the corresponding relationship is (1.875X, 0 gear), (1.75X, 1 gear), (1.625X, 2 gear), ..., (0X, 0 gear). Then for 0 gear, its next decreasing gear is 1 gear. Therefore, the comparison threshold corresponding to 0 gear is: 1.8125X=(1.875X+1.75X) / 2.

[0069] refer to Figure 3 , which is a schematic structural diagram of a power regulation circuit provided by the present invention, the power regulation circuit includes: a gear setting circuit 1, a level setting circuit 2 and a processor 3.

[0070] The gear setting circuit 1 is used to output the gear analog quantity; the level setting circuit 2 is used to generate the level signal; the processor 3 is connected to the gear setting circuit 1 and the level setting circuit 2, and is used to output the power adjustment signal according to the size of the gear analog quantity and the level signal.

[0071] The processor 3 can be a single chip microcomputer or microcontroller commonly used in the prior art, which includes a gear analog input terminal and a level signal input terminal, corresponding to two IO ports in the processor 3, responsible for collecting the gear analog quantity and the level signal.

[0072] Furthermore, in a preferred embodiment, Figure 4As shown, the gear setting circuit 1 includes a first resistor RP5, a second resistor RP7, a third resistor RP6, a fourth resistor RP9, a fifth resistor RP11, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. Specifically, the first end of the first resistor RP5 is connected to a first DC voltage, the second end of the first resistor RP5 is connected to the gear analog input terminal of the processor 3, and the second end of the first resistor RP5 is further connected to ground via the second resistor RP7, the third resistor RP6, the fourth resistor RP9, and the fifth resistor RP11. The first switch S1 is connected in parallel with the second resistor RP7, the second switch S2 is connected in parallel with the third resistor RP6, the third switch S3 is connected in parallel with the fourth resistor RP9, and the fourth switch S4 is connected in parallel with the fifth resistor RP11. By setting the opening and closing combinations of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, the gear analog value of different voltage value ranges can be output. The first resistor RP5 is used to prevent the first DC voltage from being grounded when the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all closed.

[0073] It should be noted that, in this embodiment, the level setting circuit 2 includes four gear setting units, each of which is composed of a resistor and a switch connected in parallel with the resistor. Figure 4 As shown, the second resistor RP7 and the first switch S1 form a first gear setting unit, the third resistor RP6 and the second switch S2 form a second gear setting unit, the fourth resistor RP9 and the third switch S3 form a third gear setting unit, and the fifth resistor RP11 and the fourth switch S4 form the first gear setting unit. The first DC voltage can be provided by a switching power supply or a linear power supply commonly used in the prior art.

[0074] In a specific embodiment, the first switch S1 , the second switch S2 , the third switch S3 and the fourth switch S4 may be dip switches.

[0075] In a specific embodiment, the impedances of the second resistor RP7, the third resistor RP6, the fourth resistor RP9, and the fifth resistor RP11 can be set in the following manner:

[0076] The impedances of the second resistor RP7, the third resistor RP6, the fourth resistor RP9, and the fifth resistor RP11 are decreased from large to small based on a preset proportional range, thereby causing the gear setting circuit 1 to output gear position analog quantities in 16 different voltage value ranges. In this embodiment, the second resistor RP7, the third resistor RP6, the fourth resistor RP9, and the fifth resistor RP11 can be resistors with an accuracy of 5% or less to ensure the accuracy of the gear position analog quantity detection.

[0077] In a specific embodiment, Figure 4As shown, the gear setting circuit 1 also includes an eighth resistor RP14. The second end of the fifth resistor RP11 is connected to the ground via the eighth resistor RP14. When all switches are closed, it is equivalent to providing a basic impedance for the gear analog input terminal of the processor 3, which is beneficial to improving the detection of the gear analog quantity, especially the 15th gear; in addition, the impedance ratio of the fifth resistor RP11 and the eighth resistor RP14 is within the preset ratio range, which has a better effect on improving the detection accuracy.

[0078] Furthermore, in a preferred embodiment, Figure 5 As shown, the level setting circuit 2 includes a sixth resistor RP16, a seventh resistor RP18, and a level setting unit 21 for setting the level of the level signal. Specifically, a first end of the sixth resistor RP16 is connected to the output end of the level setting unit 21, a second end of the sixth resistor RP16 is connected to the level signal input end of the processor 3 as the level signal output end, and a second end of the sixth resistor RP16 is further connected to ground via the seventh resistor RP18.

[0079] In a specific embodiment, the level setting unit 21 includes a switch or a diode. Figure 5 The level setting unit 21 in the illustrated embodiment includes a diode DP2, the anode of which is connected to a first DC voltage, and the cathode of which is connected to the first end of a sixth resistor RP16. In this embodiment, the level of the level signal is fixed at a high level. If the level of the level signal needs to be set to a low level, the diode DP2 and / or the sixth resistor RP16 can be removed from the soldering before the level setting circuit 2 leaves the factory. It will be appreciated that in an embodiment (not shown) where the diode DP2 is replaced with a switch (which may be a self-locking switch), the high and low levels of the level signal can be controlled by controlling the opening and closing of the switch, thus providing greater flexibility. Furthermore, the implementation scheme of the level setting unit 21 can be selected based on the actual needs of the user.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0081] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0082] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, software modules executed by a processor (3), or a combination of the two. The software modules may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0083] It is understandable that the above embodiments only express the preferred implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the patent scope of the present invention. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can be made, all of which fall within the scope of protection of the present invention. Therefore, all equivalent changes and modifications made to the scope of the claims of the present invention should fall within the scope of coverage of the claims of the present invention.

Claims

1. A power regulation method for regulating the output power of a controlled circuit, characterized in that: include: Acquiring a gear position analog value through a gear position setting circuit of the controlled circuit; obtaining a level signal through a level setting circuit of the controlled circuit; Outputting a power adjustment signal according to the size of the gear position analog quantity and the level signal; The gear setting circuit includes a plurality of gear setting units; the gear setting units are sequentially connected in series to form a series chain; one end of the series chain is used to output the gear analog quantity, and the other end is grounded; each of the gear setting units has a settable state including a first state and a second state; each of the gear setting units outputs a plurality of gear analog quantities in different voltage value ranges by switching and coordinating the settable states; The first state is a high-impedance state, and the second state is a low-impedance state; The power regulation method further includes: setting the impedance of each of the gear setting units when in the high impedance state to decrease from large to small based on a preset proportional range; The step of outputting a power adjustment signal according to the magnitude of the gear position analog quantity and the level signal includes: comparing the gear position analog quantity with gear position threshold data to confirm the gear value of the gear position analog quantity; wherein the gear position threshold data includes a plurality of gear levels corresponding to the number of the voltage value ranges and comparison thresholds corresponding to each of the gear levels; and setting and outputting the power adjustment signal according to the gear value and the level signal; In the step of setting and outputting the power adjustment signal according to the gear value and the level signal, it includes: dividing the adjustable range of the power adjustment signal into a first level interval and a second level interval; dividing the first level interval and the second level interval into a set number of interval blocks respectively, and corresponding each of the gear levels to the boundary values of each of the interval blocks of the first level interval and the second level interval based on the size; if the level signal is in a first level state, setting the output setting value of the power adjustment signal to the boundary value corresponding to the gear level with the same gear value in the first level interval; if the level signal is in a second level state, setting the output setting value of the power adjustment signal to the boundary value corresponding to the gear level with the same gear value in the second level interval; and outputting the set power adjustment signal.

2. The power regulation method according to claim 1, wherein: The preset ratio range is 0.47-0.

52.

3. The power regulation method according to claim 1, wherein: The number of the gear setting units is 4.

4. The power regulation method according to claim 1, wherein: The step of comparing the gear position analog value with the gear position threshold data to confirm the gear position value of the gear position analog value includes: The gear level corresponding to the comparison threshold value that is smaller than the gear analog value and closest in size is set as the gear value of the gear analog value.

5. The power regulation method according to claim 1, wherein: Also includes: Calculating theoretical gear position analog quantities corresponding to each gear level according to design parameters of the gear setting circuit; The average value of the theoretical gear analog value corresponding to the gear level and the theoretical gear analog value of the next decreasing gear is set as the comparison threshold corresponding to the gear level.

6. A power regulation circuit, characterized in that: include: A gear setting circuit (1) is used to output a gear position analog value; A level setting circuit (2) for generating a level signal; A processor (3) is connected to the gear setting circuit (1) and the level setting circuit (2), and is used to output a power adjustment signal according to the size of the gear analog quantity and the level signal; the outputting of the power adjustment signal according to the size of the gear analog quantity and the level signal includes: comparing the gear analog quantity with gear threshold data to confirm the gear value of the gear analog quantity; wherein the gear threshold data includes a number of gear levels corresponding to the number of voltage value ranges and comparison thresholds corresponding to each of the gear levels; setting and outputting the power adjustment signal according to the gear value and the level signal; the setting and outputting of the power adjustment signal according to the gear value and the level signal includes: dividing the adjustable range of the power adjustment signal into a first level interval and a second level interval; dividing the first level interval and the second level interval into a set number of interval blocks, and corresponding each of the gear levels to the boundary values of each of the interval blocks of the first level interval and the second level interval based on the size; If the level signal is in a first level state, setting the output value of the power adjustment signal to a boundary value corresponding to the gear level that is the same as the gear value in the first level interval; if the level signal is in a second level state, setting the output value of the power adjustment signal to a boundary value corresponding to the gear level that is the same as the gear value in the second level interval; and outputting the set power adjustment signal; The gear setting circuit (1) includes a first resistor RP5, a second resistor RP7, a third resistor RP6, a fourth resistor RP9, a fifth resistor RP11, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; The first end of the first resistor RP5 is connected to a first DC voltage, the second end of the first resistor RP5 is connected to the gear analog input end of the processor (3), the second end of the first resistor RP5 is also connected to the ground via the second resistor RP7, the third resistor RP6, the fourth resistor RP9 and the fifth resistor RP11 in sequence, the first switch S1 is connected in parallel with the second resistor RP7, the second switch S2 is connected in parallel with the third resistor RP6, the third switch S3 is connected in parallel with the fourth resistor RP9, and the fourth switch S4 is connected in parallel with the fifth resistor RP11; By setting the on / off combination of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4, the gear position analog quantity with different voltage value ranges can be output; The impedances of the second resistor RP7 , the third resistor RP6 , the fourth resistor RP9 and the fifth resistor RP11 decrease gradually from large to small based on a preset ratio range.

7. The power regulation circuit according to claim 6, characterized in that: The level setting circuit (2) includes a sixth resistor RP16, a seventh resistor RP18 and a level setting unit (21) for setting the level of the level signal; The first end of the sixth resistor RP16 is connected to the output end of the level setting unit (21), the second end of the sixth resistor RP16 is connected to the level signal input end of the processor (3) as the level signal output end, and the second end of the sixth resistor RP16 is also connected to the ground via the seventh resistor RP18.

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