Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel, wherein an active layer is arranged on a substrate; a gate is arranged on a substrate, and the gate is arranged in a different layer from the active layer; a first metal layer is arranged above the gate and the active layer, and the first metal layer is arranged in a different layer from the gate and the active layer respectively; the first metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer; a first insulating layer covers the first metal layer; a second metal layer is arranged on the first insulating layer, and the second metal layer includes a data line, and the data line is connected to the source electrode; and a flat layer covers the second metal layer and the first insulating layer. The present application adopts the arrangement of data lines and drain electrodes in different layers, which reduces the distance between the two in layout, thereby improving the resolution; at the same time, the data line is arranged on the upper layer of the drain electrode. Compared with the prior art, the embodiment of the present application avoids the situation where the contact hole between the drain electrode and the active layer is too deep, thereby solving the process problem caused by the excessive hole depth.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In conventional array substrate designs, the data line and the drain electrode are on the same layer. As the resolution increases, the pixel pitch becomes smaller and smaller, and the space between the data line and the drain electrode cannot be reduced any further.

[0003] In the process of research and practice of the prior art, the inventor of the present application found that the existing design places the data line below the layer where the drain is located to solve this problem, but this also creates the problem that the depth of the hole connecting the drain and the active layer exceeds the process limit and is difficult to control. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can reduce the distance between the data line and the drain of the thin film transistor and solve the process problem caused by the excessive hole depth.

[0005] The present application provides an array substrate, which includes:

[0006] substrate;

[0007] an active layer, the active layer being disposed on the substrate;

[0008] A gate, the gate being disposed on the substrate, and the gate and the active layer being disposed in different layers;

[0009] A first metal layer, wherein the first metal layer is disposed above the gate electrode and the active layer, and the first metal layer is disposed in different layers from the gate electrode and the active layer respectively; the first metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer;

[0010] a first insulating layer, wherein the first insulating layer covers the first metal layer;

[0011] a second metal layer, the second metal layer being disposed on the first insulating layer, the second metal layer comprising a data line, the data line being connected to the source electrode; and

[0012] A planarization layer covers the second metal layer and the first insulating layer.

[0013] Optionally, in some embodiments of the present application, the array substrate further includes a pixel electrode, and the pixel electrode is disposed on the planar layer;

[0014] The first insulating layer is provided with a first opening, the first opening exposing the drain electrode; the flat layer is provided with a second opening, the second opening corresponds to and is connected to the first opening, and the hole wall of the second opening is arranged at intervals on the outside of the hole wall of the first opening;

[0015] The pixel electrode covers the second opening and the first opening, and is connected to the drain.

[0016] Optionally, in some embodiments of the present application, the array substrate further includes a pixel electrode, and the pixel electrode is disposed on the planar layer;

[0017] The first insulating layer is provided with a first opening, the first opening exposing the drain electrode; the flat layer is provided with a second opening, the second opening corresponds to and is connected to the first opening, and the hole wall of the second opening is connected to the hole wall of the first opening;

[0018] The pixel electrode covers the second opening and the first opening, and is connected to the drain.

[0019] Optionally, in some embodiments of the present application, the first opening and the second opening are coaxially arranged.

[0020] Optionally, in some embodiments of the present application, the array substrate further includes a second insulating layer, a common electrode and an organic body, the second insulating layer covers the pixel electrode and the planar layer, and the common electrode is arranged on the second insulating layer;

[0021] Part of the second insulating layer covers the first opening and the second opening to form a first groove; part of the common electrode covers the first groove to form a second groove;

[0022] The organic body is arranged in the second groove; the organic body is used for supporting the spacer column.

[0023] Optionally, in some embodiments of the present application, the common electrode includes a first part and a second part that are connected, the first part is arranged in the second groove, the second part is arranged outside the second groove, and the thickness of the first part is greater than the thickness of the second part.

[0024] Optionally, in some embodiments of the present application, the second metal layer further includes a connection pad, and the common electrode is connected to the connection pad through a third via hole.

[0025] Correspondingly, an embodiment of the present application further provides a display panel, which includes a color filter substrate and an array substrate as described in any of the above embodiments, wherein the color filter substrate is arranged opposite to the array substrate.

[0026] Optionally, in some embodiments of the present application, the color filter substrate includes a spacer column; the spacer column and the organic body are arranged to overlap.

[0027] Optionally, in some embodiments of the present application, the organic body, the common electrode, the pixel electrode and the drain electrode are arranged to overlap with each other.

[0028] The embodiment of the present application adopts different layers for setting the data line and the drain electrode, which reduces the distance between the two in layout, thereby improving the resolution; at the same time, the data line is set in the upper layer of the drain electrode. Compared with the prior art in which the data line is set in the lower layer of the drain electrode, the embodiment of the present application avoids the situation where the contact hole between the drain electrode and the active layer is too deep, thereby solving the process problem caused by excessive hole depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0031] Figure 2 is another structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of step B1 of the method for preparing an array substrate provided in an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of step B2 of the method for preparing an array substrate provided in an embodiment of the present application;

[0034] Figure 5 is a schematic diagram of step B3 of the method for preparing an array substrate provided in an embodiment of the present application;

[0035] Figure 6 is a schematic diagram of step B4 of the method for preparing an array substrate provided in an embodiment of the present application;

[0036] Figure 7 is a schematic diagram of step B5 of the method for preparing an array substrate provided in an embodiment of the present application;

[0037] Figure 8 is a schematic diagram of step B6 of the method for preparing an array substrate provided in an embodiment of the present application;

[0038] Fig. 9is a schematic diagram of step B7 of the method for preparing an array substrate provided in an embodiment of the present application;

[0039] Fig.10 is a schematic diagram of step B8 of the method for preparing an array substrate provided in an embodiment of the present application;

[0040] Fig.11 is another schematic diagram of step B8 of the method for preparing an array substrate provided in an embodiment of the present application;

[0041] Fig.12 is a schematic diagram of step B9 of the method for preparing an array substrate provided in an embodiment of the present application;

[0042] Fig.13 is a schematic diagram of step B10 of the method for preparing an array substrate provided in an embodiment of the present application;

[0043] Fig.14 is a schematic diagram of step B11 of the method for preparing an array substrate provided in an embodiment of the present application;

[0044] Fig.15 is a schematic diagram of step B12 of the method for preparing an array substrate provided in an embodiment of the present application;

[0045] Fig.16 It is a schematic diagram of the structure of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0047] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0048] Please refer to Figure 1 The embodiment of the present application provides an array substrate 100 , which includes a substrate 11 , an active layer 12 , a gate 13 , a first metal layer m1 , a first insulating layer g1 , a second metal layer m2 and a planar layer 14 .

[0049] The active layer 12 is disposed on the substrate 11. The gate 13 is disposed on the substrate 11. The gate 13 and the active layer 12 are disposed in different layers.

[0050] The first metal layer m1 is disposed above the gate 13 and the active layer 12. The first metal layer m1 is disposed in a different layer from the gate 13 and the active layer 12. The first metal layer m1 includes a source electrode s and a drain electrode d, and the source electrode s and the drain electrode d are connected to the active layer 12, respectively.

[0051] The first insulating layer g1 covers the first metal layer m1. The second metal layer m2 is disposed on the first insulating layer g1. The second metal layer m2 includes a data line data, and the data line data is connected to the source electrode s. The planar layer 14 covers the second metal layer m2 and the first insulating layer g1.

[0052] The array substrate 100 of the embodiment of the present application adopts the arrangement of the data line data and the drain electrode d in different layers, which reduces the distance between the two in layout, thereby improving the resolution; at the same time, the data line data is arranged on the upper layer of the drain electrode d. Compared with the prior art in which the data line data is arranged on the lower layer of the drain electrode d, the embodiment of the present application avoids the situation in which the contact hole between the drain electrode d and the active layer 12 is too deep, thereby solving the process problem caused by the excessive hole depth.

[0053] It should be noted that when the gate 13 is located above the active layer 12, the thin film transistor of the array substrate 100 has a top gate structure; when the gate 13 is located below the active layer 12, the thin film transistor of the array substrate 100 has a bottom gate structure; of course, there are also thin film transistors with dual gate structures.

[0054] The array substrate 100 of this embodiment is described by taking the case where the gate 13 is located above the active layer 12 as an example.

[0055] In the array substrate 100 of the present embodiment, the array substrate 100 further includes a light shielding layer 15 , a buffer layer 16 , a gate insulating layer 17 and an interlayer dielectric layer 18 .

[0056] The light shielding layer 15 is disposed on the substrate 11. The buffer layer 16 covers the light shielding layer 15 and the substrate 11. The active layer 12 is disposed on the buffer layer 16 and overlaps with the light shielding layer 15. The gate insulating layer 17 covers the active layer 12 and the buffer layer 16. The gate 13 is disposed on the gate insulating layer 17 and is disposed corresponding to the active layer 12. The interlayer dielectric layer 18 covers the gate 13 and the gate insulating layer 17. The first metal layer m1 is disposed on the interlayer dielectric layer 18.

[0057] Optionally, the light shielding layer 15 is used to shield the substrate 11 from light, so as to prevent the light from irradiating the active layer 12. The material of the light shielding layer 15 can be a metal material, such as Cr (chromium), Mo (molybdenum), Mn (manganese), etc., or a metal oxide material, such as CrO x 、MoO x , MnO2, etc., or a mixed film layer formed by metal and metal oxide; it can also be an organic black resin material, such as black polystyrene, black photoresist, etc.

[0058] Alternatively, the material of the active layer 12 may be formed of single crystal silicon, polycrystalline silicon (poly-Si) or an oxide semiconductor. The oxide semiconductor may include an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In) and a composite oxide thereof (such as indium gallium zinc oxide (InGaZnO4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), indium aluminum oxide (In-Al -O), indium zinc aluminum oxide (In-Zn-Al-O), indium tin aluminum oxide (In-Sn-Al-O), indium aluminum gallium oxide (In-Al-Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O) and hafnium indium zinc oxide (Hf-In-Zn-O)).

[0059] The first insulating layer g1, the buffer layer 16, the gate insulating layer 17, the interlayer dielectric layer 18 and the second insulating layer g2 described above may be formed by stacking a plurality of inorganic layers in an alternating manner. For example, the buffer layer 16, the gate insulating layer 17 and the interlayer dielectric layer 18 may be formed by stacking a plurality of inorganic layers including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), an inorganic layer of at least one of aluminum oxide, magnesium oxide and titanium oxide, or a double layer formed by alternately stacking an inorganic layer including silicon oxide (SiO x), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), an inorganic layer of at least one of aluminum oxide, magnesium oxide and titanium oxide. However, the present disclosure is not limited thereto, and the buffer layer 16, the gate insulating layer 17 and the interlayer dielectric layer 18 may be formed as a single inorganic layer including the above insulating materials. In addition, in one or more embodiments, the interlayer dielectric layer 18 may be made of an organic insulating material such as polyimide (PI).

[0060] The gate 13, the first metal layer m1 and the second metal layer m2 can be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), zinc (Zn), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0061] The material of the planar layer 14 may be an organic transparent film layer, such as transparent photoresist, epoxy resin, polyimide, polyvinyl alcohol, polymethyl methacrylate, polystyrene, etc.

[0062] Optionally, the array substrate 100 of this embodiment further includes a pixel electrode 19 , and the pixel electrode 19 is disposed on the planar layer 14 .

[0063] The first insulating layer g1 is provided with a first opening k1, and the first opening k1 exposes the drain electrode d. The flat layer 14 is provided with a second opening k2, and the second opening k2 corresponds to and is connected to the first opening k1. The hole wall of the second opening k2 is spaced outside the hole wall of the first opening k1.

[0064] The pixel electrode 19 covers the second opening k2 and the first opening k1 and is connected to the drain electrode d.

[0065] The first opening k1 and the second opening k2 are each formed by etching using a photomask process.

[0066] In some embodiments, Figure 2 As shown, the hole wall of the second opening k2 is connected to the hole wall of the first opening k1. The first opening k1 and the second opening k2 are formed by etching using a single photomask process. Compared with the formation process of the first opening k1 and the second opening k2 in the above-mentioned embodiment, the array substrate 100 of this embodiment uses a single photomask process to form the first opening k1 and the second opening k2, which solves the problem that the first opening k1 and the second opening k2 are misaligned and overlapped due to the exposure accuracy problem.

[0067] Optionally, the first opening k1 and the second opening k2 are coaxially arranged. That is, when the first opening k1 and the second opening k2 are circular holes, they are concentrically arranged.

[0068] It is understandable that the pixel electrode 19 can be a pixel electrode applied to a liquid crystal display, or can be an anode applied to an electroluminescent display. In this embodiment, the application to a liquid crystal display is taken as an example.

[0069] In the array substrate 100 of the embodiment, the array substrate 100 further includes a second insulating layer g2, a common electrode 20 and an organic body 21. The second insulating layer g2 covers the pixel electrode 19 and the planar layer 14. The common electrode 20 is disposed on the second insulating layer g2.

[0070] Part of the second insulating layer g2 covers the first opening k1 and the second opening k2 to form a first groove mk1. Part of the common electrode 20 covers the first groove mk1 to form a second groove mk2.

[0071] The organic body 21 is disposed in the second groove mk2 and is used to support the spacer column.

[0072] In this embodiment, the second groove mk2 is filled with an organic body 21, so that the second groove mk2 is filled. When the array substrate 100 is used to form a liquid crystal box, the spacer of the color filter substrate contacts the organic body 21, so that the spacer does not extend into the second groove mk2, thereby ensuring the spacing of the liquid crystal box.

[0073] In addition, the organic body 21 is used to correspond to the spacer column. When the liquid crystal box is squeezed, the organic body 21 can release part of the compressive stress of the spacer column.

[0074] In this embodiment, the common electrode 20 includes a first portion 2a and a second portion 2b connected to each other. The first portion 2a is disposed in the second groove mk2, and the second portion 2b is disposed outside the second groove 2b. The thickness of the first portion 2a is greater than that of the second portion 2b.

[0075] The thickness of the second part 2b is smaller than that of the first part 2a. On the one hand, the thinner second part 2b is set in the second groove mk2 to ensure that the overall thickness of the array substrate 100 is not large; on the other hand, the thicker first part 2a is set in the second groove mk2 to improve the supporting performance.

[0076] Optionally, the thickness of the pixel electrode 19 in the first groove mk1 is greater than the thickness of the pixel electrode 19 outside the first groove mk1. This configuration not only improves the conductivity, but also further improves the effect of supporting the spacer column and avoids the risk of excessive deformation of the organic body 21.

[0077] Optionally, the second metal layer m2 further includes a connection pad j1. The common electrode 20 is connected to the connection pad j1 through the third opening k3. The first metal layer m1 further includes a wiring j2, and the connection pad j1 is connected to the wiring j2.

[0078] Optionally, the material of the pixel electrode 19 and the common electrode 20 may include metal oxides, such as indium tin oxide, indium zinc oxide, etc.

[0079] It should be noted that the method for preparing the array substrate 100 of this embodiment is as follows:

[0080] Step B1, sequentially forming a light shielding layer 15 and a buffer layer 16 on the substrate 11. Figure 3 shown.

[0081] Optionally, a light-shielding metal layer is first formed on the substrate 11, and then the light-shielding metal layer is patterned to form a light-shielding layer 15. The light-shielding layer 15 shields the bottom of the thin film transistor to be formed subsequently.

[0082] Step B2, forming an active layer 12 on the buffer layer 16. Figure 4 shown.

[0083] Optionally, a silicon material layer is formed on the buffer layer 16, and then the silicon material layer is patterned, and then the patterned silicon material layer is subjected to excimer laser annealing to form an active layer 12; secondly, phosphorus ions are doped in the heavily doped region of the active layer 12 to form an N+ doped region.

[0084] Step B3, forming a gate insulating layer 17 and a gate 13 on the buffer layer 16 in sequence. Figure 5 shown.

[0085] Optionally, a gate insulating layer 17 is formed on the buffer layer 16; a gate material layer is then formed on the gate insulating layer 17; the gate material layer is then etched by exposure to form a gate 13; finally, phosphorus ion light doping is performed using the gate 13 as a shield to form an N-doped region.

[0086] Step B4, forming an interlayer dielectric layer 18 on the gate insulating layer 17. Figure 6 shown.

[0087] Optionally, an interlayer dielectric layer 18 is deposited on the gate insulating layer 17 , followed by a rapid annealing process, and then an exposure and etching process to form source and drain vias.

[0088] Step B5, forming a first metal layer m1 on the interlayer dielectric layer 18, wherein the first metal layer m1 includes a source electrode s, a drain electrode d and a wiring j2. Figure 7 shown.

[0089] Optionally, a metal material layer is deposited on the interlayer dielectric layer 18, and a source electrode s, a drain electrode d and a wiring j2 are formed by exposure and etching. The source electrode s and the drain electrode d are connected to the active layer 12 respectively.

[0090] Step B6, forming a first insulating layer g1 covering the first metal layer m1 on the interlayer dielectric layer 18. Figure 8 shown.

[0091] Step B7, forming a second metal layer m2 on the first insulating layer g1. Fig. 9 shown.

[0092] Optionally, the second metal layer m2 includes a data line data and a connection pad j1. The data line data is connected to the source electrode s. The connection pad j1 is connected to the wiring j2.

[0093] Step B8, forming a planarization layer 14 on the first insulating layer g1.

[0094] Optionally, a planar layer 14 is formed on the first insulating layer g1, and then a second opening k2 is formed on the planar layer 14 by exposure and etching; and then another exposure and etching process is performed to form the first opening k1 on the first insulating layer g1. Fig.10 shown.

[0095] In some embodiments, a flat layer 14 may be formed on the first insulating layer g1, and then a photoresist is coated on the surface of the flat layer, and an exposure hole is formed by exposure, and then a second opening k2 is formed on the flat layer 14 and a first opening k1 is formed on the first insulating layer g1 by an etching process. Fig.11 shown.

[0096] Step B9, forming a pixel electrode 19 on the planar layer 14. Fig.12 shown.

[0097] Optionally, an oxide semiconductor layer is deposited on the planar layer 14, and then the pixel electrode 19 is formed by exposure and etching. The pixel electrode 19 is connected to the drain electrode d through the first opening k1 and the second opening k2.

[0098] Step B10, forming a second insulating layer g2 on the planar layer 14. Fig.13 shown.

[0099] Optionally, a portion of the second insulating layer g2 covers the first opening k1 and the second opening k2 to form a first groove mk1.

[0100] Step B11, forming a common electrode 20 on the second insulating layer g2. Fig.14 shown.

[0101] Optionally, an oxide semiconductor layer is deposited on the second insulating layer g2, and then exposed and etched to form a common electrode 20. The common electrode 20 is connected to the connection pad j1. The common electrode 20 partially covers the first groove mk1 to form a second groove mk2.

[0102] Step B12, filling the second groove mk2 with organic material to form an organic body 21. Fig.15 shown.

[0103] Optionally, the organic body 21 fills up the second groove mk2.

[0104] In this way, the preparation process of the array substrate 100 of the embodiment of the present application is completed.

[0105] Please refer to Fig.16 The embodiment of the present application further provides a display panel 1000, which includes a color filter substrate 200 and an array substrate 100 of any of the above embodiments. The color filter substrate 200 is arranged opposite to the array substrate 100. A liquid crystal (not shown in the figure) is also arranged between the color filter substrate 200 and the array substrate 100.

[0106] Optionally, the color filter substrate 200 includes a spacer 20a. The spacer 20a is overlapped with the organic body 21. The display panel 1000 of this embodiment uses the organic body 21 to fill the second groove mk2, so that the second groove mk2 is filled. The spacer 20a of the color filter substrate 200 contacts the organic body 21, so that the spacer 20a does not extend into the second groove mk2, thereby ensuring the spacing of the liquid crystal box.

[0107] In addition, the organic body 21 is used to correspond to the spacer column 20a. When the liquid crystal box is squeezed, the organic body 21 can release part of the compressive stress of the spacer column 20a.

[0108] Optionally, the common electrode 20 , the pixel electrode 19 and the drain electrode d are arranged to overlap each other. The overlapping structure of the three improves the support performance of the spacer 20 a to supplement the flexibility of the organic body 21 .

[0109] It should be noted that, for the description of the array substrate 100 of the display panel 1000 of this embodiment, please refer to the contents of the array substrate 100 of the above embodiment, which will not be repeated here.

[0110] The display panel 1000 of the embodiment of the present application adopts the data line data and the drain electrode d to be arranged in different layers, which reduces the distance between the two in layout, thereby improving the resolution; at the same time, the data line data is arranged in the upper layer of the drain electrode d. Compared with the prior art in which the data line is arranged in the lower layer of the drain electrode, the embodiment of the present application avoids the situation in which the contact hole between the drain electrode d and the active layer 12 is too deep, thereby solving the process problem caused by the excessive hole depth.

[0111] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; an active layer, the active layer being disposed on the substrate; A gate, the gate being disposed on the substrate, and the gate and the active layer being disposed in different layers; A first metal layer, the first metal layer is arranged above the gate and the active layer, and the first metal layer is arranged in different layers from the gate and the active layer respectively; the first metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer; a first insulating layer, the first insulating layer covering the first metal layer, the first insulating layer being provided with a first opening, the first opening exposing the drain electrode; a second metal layer, the second metal layer being disposed on the first insulating layer, the second metal layer comprising a data line, and the data line being connected to the source electrode; a flat layer, the flat layer covering the second metal layer and the first insulating layer, the flat layer being provided with a second opening, the second opening corresponding to and connected to the first opening; A pixel electrode, disposed on the planar layer, the pixel electrode covers the second opening and the first opening, and is connected to the drain electrode; A second insulating layer, covering the pixel electrode and the planar layer, wherein a portion of the second insulating layer covers the first opening and the second opening to form a first groove; as well as A common electrode is disposed on the second insulating layer, and a portion of the common electrode covers the first groove to form a second groove; An organic body is arranged in the second groove, the organic body is used to overlap with the spacer to support the spacer, and the organic body, the common electrode, the pixel electrode and the drain are overlapped with each other.

2. The array substrate according to claim 1, characterized in that: The hole wall of the second opening is arranged at an interval outside the hole wall of the first opening.

3. The array substrate according to claim 1, characterized in that: The hole wall of the second opening is connected to the hole wall of the first opening.

4. The array substrate according to claim 2 or 3, characterized in that: The first opening and the second opening are coaxially arranged.

5. The array substrate according to claim 2 or 3, characterized in that: The common electrode includes a first portion and a second portion that are connected, the first portion is disposed in the second groove, the second portion is disposed outside the second groove, and a thickness of the first portion is greater than a thickness of the second portion.

6. The array substrate according to claim 2 or 3, characterized in that: The second metal layer further includes a connection pad, and the common electrode is connected to the connection pad through a third via hole.

7. A display panel, characterized in that: It comprises a color filter substrate and an array substrate as claimed in claims 1 to 6, wherein the color filter substrate is arranged opposite to the array substrate.

8. The display panel according to claim 7, characterized in that: The color film substrate comprises spacer columns; the spacer columns are arranged overlapping with the organic body.

Images