An electrostatic protection device and an electronic device

Abstract

Embodiments of the present application disclose an electrostatic protection device and an electronic device. Among them, the electrostatic protection device includes: a P-type substrate; an N-well located within the P-type substrate; a PMOS transistor, the PMOS transistor including a gate and first and second P-type heavily doped regions located on both sides of the gate; a pulse monitoring unit, the gate of the PMOS transistor being controlled by the pulse monitoring unit; wherein, the first P-type heavily doped region straddles between the P-type substrate and the N-well, the P-type substrate is connected to a first pad, and the second P-type heavily doped region is connected to a second pad.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuits, and particularly to an electrostatic protection device and an electronic device. Background Art

[0002] In all aspects of integrated circuits, charge accumulation may occur. Under certain conditions, the charge will transfer, and the large current passing through instantaneously may exceed the critical value of the device, resulting in chip burnout. Statistical data shows that Electro Static Discharge (ESD) is the main cause of integrated circuit failure, especially more prominent in power integrated circuits. Therefore, the problem of electrostatic discharge has become the most concerned issue for designers. Summary of the Invention

[0003] In view of this, embodiments of the present application provide an electrostatic protection device and an electronic device.

[0004] According to a first aspect of the embodiments of the present application, an electrostatic protection device is provided, including:

[0005] A P-type substrate;

[0006] An N-well, located within the P-type substrate;

[0007] A PMOS transistor, the PMOS transistor including a gate and a first P-type heavily doped region and a second P-type heavily doped region located on both sides of the gate;

[0008] A pulse monitoring unit, the gate of the PMOS transistor being controlled by the pulse monitoring unit; wherein,

[0009] The first P-type heavily doped region straddles between the P-type substrate and the N-well, the P-type substrate is connected to a first pad, and the second P-type heavily doped region is connected to a second pad.

[0010] In some embodiments, it further includes:

[0011] A first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, and a third P-type heavily doped region;

[0012] The first N-type heavily doped region, the third P-type heavily doped region, and the second N-type heavily doped region are located within the P-type substrate;

[0013] The third N-type heavily doped region and the second P-type heavily doped region are located within the N-well.

[0014] In some embodiments, the third P-type heavily doped region and the second N-type heavily doped region are connected to the first pad.

[0015] In some embodiments, the first N-type heavily doped region is connected to the second pad.

[0016] In some embodiments, it further includes:

[0017] A third pad; the third N-type heavily doped region is connected to the third pad.

[0018] In some embodiments, the second P-type heavily doped region, the N-well, and the P-type substrate form a parasitic PNP transistor;

[0019] The N-well, the P-type substrate, and the second N-type heavily doped region form a parasitic NPN transistor.

[0020] In some embodiments, the first N-type heavily doped region and the third P-type heavily doped region form a first parasitic diode;

[0021] The third P-type heavily doped region and the third N-type heavily doped region form a second parasitic diode;

[0022] The second P-type heavily doped region and the third N-type heavily doped region form a third parasitic diode.

[0023] In some embodiments, the pulse monitoring unit includes a resistor R and a capacitor C;

[0024] The gate of the PMOS transistor is connected to the third pad through the resistor R and to the first pad through the capacitor C.

[0025] In some embodiments, the second P-type heavily doped region, the parasitic PNP transistor, the parasitic NPN transistor, and the second N-type heavily doped region form a first electrostatic current discharge path from the second pad to the first pad.

[0026] In some embodiments, the third P-type heavily doped region, the first parasitic diode, and the first N-type heavily doped region form a second electrostatic current discharge path from the first pad to the second pad.

[0027] In some embodiments, the second P-type heavily doped region, the third parasitic diode, and the third N-type heavily doped region form a third electrostatic current discharge path from the second pad to the third pad.

[0028] In some embodiments, the third P-type heavily doped region, the second parasitic diode, and the third N-type heavily doped region form a fourth electrostatic current discharge path from the first pad to the third pad.

[0029] In some embodiments, the first pad is a ground pad; the second pad is an input / output pad; the third pad is a power supply pad.

[0030] According to a second aspect of the embodiments of the present application, an electronic device is provided, which includes the electrostatic protection device described in any of the above embodiments and an electronic component connected to the electrostatic protection device.

[0031] In the embodiments of the present application, by adding a pulse monitoring unit and a PMOS transistor controlled by the pulse monitoring unit, when electrostatic occurs, the PMOS transistor controlled by the pulse monitoring unit will conduct, thereby triggering an electrostatic current discharge path from the second pad to the first pad to complete the discharge of the electrostatic current. Moreover, the trigger voltage of the electrostatic protection device in the present application is low and the leakage is low, improving the electrostatic protection ability. Description of the Drawings

[0032] Figure 1 is a conventional electrostatic protection circuit in the related art;

[0033] Figure 2 is a conventional SCR electrostatic protection IV characteristic diagram in the related art;

[0034] Figure 3 is an ESD design window diagram in the related art;

[0035] Figure 4 is the layout of the electrostatic protection device provided by the embodiments of the present application;

[0036] Figure 5 is a cross-sectional schematic diagram of the electrostatic protection device provided by the embodiments of the present application;

[0037] Figure 6 is an equivalent circuit schematic diagram of the electrostatic protection device provided by the embodiments of the present application;

[0038] Figure 7 is a cross-sectional schematic diagram of the electrostatic protection device provided by another embodiment of the present application.

[0039] Description of the Reference Numerals:

[0040] 13’, 11 - First P-type heavily doped region; 12 - Second P-type heavily doped region; 11’, 13 - First N-type heavily doped region; 14 - Third P-type heavily doped region; 12’, 15 - Second N-type heavily doped region; 14’, 16 - Third N-type heavily doped region;

[0041] 21’, 21 - P-type substrate; 22’, 22 - N-well;

[0042] 30’, 30 - Gate; 31’, 31 - Oxide layer; 32’, 32 - Polysilicon layer; 33’, 33 - Tungsten layer;

[0043] 40’, 40 - Pulse monitoring unit;

[0044] 51 - The first parasitic diode; 52 - The second parasitic diode; 53 - The third parasitic diode. Detailed implementation manners

[0045] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully communicated to those skilled in the art.

[0046] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some well-known technical features are not described to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0047] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not mean that the present application necessarily has a first element, component, region, layer or part.

[0049] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0051] To fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0052] As the manufacturing process of modern semiconductors becomes more and more advanced, the channel length becomes shorter and shorter, the junction depth becomes shallower and shallower, with the application of silicide and lightly doped drain (LDD), the oxide layer becomes thinner and thinner, and the window of ESD protection design becomes smaller and smaller, and the challenges faced by ESD protection design become greater and greater. To protect integrated circuits from the harm of static electricity, integrated circuits are usually subjected to conventional electrostatic protection. The conventional circuit diagrams are as Figure 1 shown. The electrostatic protection devices commonly used are usually diodes, MOS, and silicon controlled rectifiers (SCR), etc. However, the conventional SCR has a high trigger voltage, a low holding voltage, and is prone to latch-up, and is not suitable for the electrostatic protection of DRAM products. Specifically, as Figure 2 shown. And, as Figure 3As shown, the conventional SCR has deviated from the ESD design window. In order to apply the SCR to the electrostatic protection of DRAM products, new electrostatic protection methods must be found.

[0053] The following uses specific embodiments to elaborate in detail on the method for identifying the latch structure provided by the present invention. It should be noted that Figures 4 to 7 in this text, the P-type heavily doped region is abbreviated as P+, the N-type heavily doped region is abbreviated as N+, the input / output pad is abbreviated as IO, the ground pad is abbreviated as VSS, and the power supply pad is abbreviated as VDD.

[0054] The embodiment of the present application provides an electrostatic protection device. Figure 4 This is the layout of the electrostatic protection device provided by the embodiment of the present application. Figure 5 This is the cross-sectional schematic diagram of the electrostatic protection device provided by the embodiment of the present application. Figure 6 This is the equivalent circuit schematic diagram of the electrostatic protection device provided by the embodiment of the present application.

[0055] Refer to Figures 4 to 6 , the electrostatic protection device includes:

[0056] a P-type substrate 21; an N-well 22 located within the P-type substrate 21; a PMOS transistor, the PMOS transistor including a gate 30 and a first P-type heavily doped region 11 and a second P-type heavily doped region 12 located on both sides of the gate 30; a pulse monitoring unit 40, the gate 30 of the PMOS transistor being controlled by the pulse monitoring unit 40; wherein, the first P-type heavily doped region 11 straddles between the P-type substrate 21 and the N-well 22, the P-type substrate 21 is connected to a first pad, and the second P-type heavily doped region 12 is connected to a second pad.

[0057] In the embodiment of the present application, by adding a pulse monitoring unit and a PMOS transistor controlled by the pulse monitoring unit, when electrostatic occurs, the PMOS transistor controlled by the pulse monitoring unit will conduct, thereby triggering an electrostatic current discharge path from the second pad to the first pad to complete the discharge of the electrostatic current. Moreover, the trigger voltage of the electrostatic protection device in the present application is low and the leakage is low, improving the electrostatic protection ability.

[0058] The electrostatic protection device provided by the embodiment of the present application includes a P-type substrate 21. The substrate can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate in the embodiment of the present application is a P-type substrate doped with P-type doping ions.

[0059] The first P-type heavily doped region 11 serves as the source of the PMOS transistor, and the second P-type heavily doped region 12 serves as the drain of the PMOS transistor.

[0060] The gate 30 of the PMOS transistor includes an oxide layer 31, a polysilicon layer 32, and a tungsten layer 33 stacked in sequence. A titanium nitride layer (not shown in the figure) is further included between the polysilicon layer 32 and the tungsten layer 33.

[0061] In one embodiment, the electrostatic protection device further includes: a first N-type heavily doped region 13, a second N-type heavily doped region 15, a third N-type heavily doped region 16, and a third P-type heavily doped region 14; the first N-type heavily doped region 13, the third P-type heavily doped region 14, and the second N-type heavily doped region 15 are located within the P-type substrate 21; the third N-type heavily doped region 16 and the second P-type heavily doped region 12 are located within the N-well 22.

[0062] It should be noted that the first N-type heavily doped region 13, the third P-type heavily doped region 14, the second N-type heavily doped region 15, the first P-type heavily doped region 11, the second P-type heavily doped region 12, and the third N-type heavily doped region 16 are isolated by a shallow trench isolation structure (not shown in the figure).

[0063] In one embodiment, the third P-type heavily doped region 14 and the second N-type heavily doped region 15 are connected to the first pad.

[0064] The first N-type heavily doped region 13 is connected to the second pad.

[0065] The electrostatic protection device further includes: a third pad; the third N-type heavily doped region 16 is connected to the third pad.

[0066] In one embodiment, as Figure 6 shown, the second P-type heavily doped region 12, the N-well 22, and the P-type substrate 21 form a parasitic PNP transistor Q1; the N-well 22, the P-type substrate 21, and the second N-type heavily doped region 15 form a parasitic NPN transistor Q2.

[0067] As Figure 6 shown, the first N-type heavily doped region 13 and the third P-type heavily doped region 14 form a first parasitic diode 51; the third P-type heavily doped region 14 and the third N-type heavily doped region 16 form a second parasitic diode 52; the second P-type heavily doped region 12 and the third N-type heavily doped region 16 form a third parasitic diode 53.

[0068] In one embodiment, the pulse monitoring unit 40 includes a resistor R and a capacitor C;

[0069] The gate 30 of the PMOS transistor is connected to the third pad through a resistor R and to the first pad through a capacitor C.

[0070] The pulse monitoring unit 40 is an RC coupling circuit, and the PMOS transistor is an RC-triggered PMOS transistor.

[0071] In the embodiment of the present application, the first pad is a ground pad; the second pad is an input / output pad; the third pad is a power supply pad.

[0072] In one embodiment, the second P-type heavily doped region 12, the parasitic PNP transistor Q1, the parasitic NPN transistor Q2, and the second N-type heavily doped region 15 form a first electrostatic current discharge path from the second pad to the first pad.

[0073] When a positive pulse is applied from the input / output pad to the ground pad and electrostatic occurs, the PMOS transistor will conduct first, thereby triggering the SCR electrostatic current discharge path composed of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2, so as to complete the electrostatic current discharge from the input / output pad to the ground pad. Specifically, the first electrostatic current discharge path is Figure 6 the path ① shown in

[0074] When working normally, the gate of the PMOS transistor is connected to the power supply pad through a resistor R and is at a high potential, and the PMOS transistor will turn off, so it does not affect the normal function of the input circuit and ensures the normal operation of the circuit.

[0075] In one embodiment, the third P-type heavily doped region 14, the first parasitic diode 51, and the first N-type heavily doped region 13 form a second electrostatic current discharge path from the first pad to the second pad.

[0076] When a negative pulse is applied from the input / output pad to the ground pad and electrostatic occurs, the electrostatic current will be discharged along the first parasitic diode 51, so as to complete the electrostatic current discharge from the ground pad to the input / output pad. Specifically, the second electrostatic current discharge path is Figure 6 the path ② shown in

[0077] In one embodiment, the second P-type heavily doped region 12, the third parasitic diode 53, and the third N-type heavily doped region 16 form a third electrostatic current discharge path from the second pad to the third pad.

[0078] When a positive pulse is applied from the input / output pad to the power supply pad and electrostatic occurs, the electrostatic current will be discharged along the third parasitic diode 53, so as to complete the electrostatic current discharge from the input / output pad to the power supply pad. Specifically, the third electrostatic current discharge path isFigure 6 Path ③ shown in

[0079] In one embodiment, the third P-type heavily doped region 14, the second parasitic diode 52, and the third N-type heavily doped region 16 form a fourth electrostatic current discharge path from the first pad to the third pad.

[0080] When a pulse is applied from the ground pad to the power supply pad and electrostatic discharge occurs, the electrostatic current will be discharged along the second parasitic diode 52, thereby completing the electrostatic current discharge from the ground pad to the power supply pad. Specifically, the fourth electrostatic current discharge path is Figure 6 Path ④ shown in

[0081] The SCR in the electrostatic protection device has a double-trigger function, a low trigger voltage, and can meet the requirements of DRAM products. Moreover, the layout design has a small area, restoring the original ESD design window.

[0082] In the embodiment of the present application, the electrostatic protection device is a PMOS-triggered thyristor rectifier (PTSCR).

[0083] The electrostatic protection device provided by the embodiment of the present application can be applied to the ESD protection of the input and output circuits of semiconductor integrated circuits and various semiconductor integrated circuits, such as logic circuits, analog circuits, and various memory chips, and can also be applied to the ESD protection of low operating voltages in advanced processes.

[0084] The embodiment of the present application also provides an electrostatic protection device. Refer to Figure 7 The electrostatic protection device includes:

[0085] A P-type substrate 21'; an N-well 22' located within the P-type substrate 21'; an NMOS transistor, the NMOS transistor including a gate 30' and first and second N-type heavily doped regions 11' and 12' located on both sides of the gate 30'; a pulse monitoring unit 40', the gate 30' of the NMOS transistor being controlled by the pulse monitoring unit 40'; wherein the second N-type heavily doped region 12' straddles between the P-type substrate 21' and the N-well 22'; the P-type substrate 21' is connected to the first pad, and the first N-type heavily doped region 11' is connected to the second pad.

[0086] The electrostatic protection device provided by the embodiment of the present application includes a P-type substrate 21'. The substrate can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate in the embodiment of the present application is a P-type substrate doped with P-type doping ions.

[0087] The first N-type heavily doped region 11' serves as the source electrode of the NMOS transistor, and the second N-type heavily doped region 12' serves as the drain electrode of the NMOS transistor.

[0088] The gate 30' of the NMOS transistor includes an oxide layer 31', a polysilicon layer 32', and a tungsten layer 33' stacked in sequence. A titanium nitride layer (not shown in the figure) is further included between the polysilicon layer 32' and the tungsten layer 33'.

[0089] In one embodiment, the electrostatic protection device further includes: a first P-type heavily doped region 13' and a third N-type heavily doped region 14'; the first P-type heavily doped region 13' and the first N-type heavily doped region 11' are located in the P-type substrate 21'; the third N-type heavily doped region 14' is located in the N-well 22'.

[0090] It should be noted that the first P-type heavily doped region 13', the first N-type heavily doped region 11', the second N-type heavily doped region 12', and the third N-type heavily doped region 14' are isolated by a shallow trench isolation structure (not shown in the figure).

[0091] The first P-type heavily doped region 13' is connected to the first pad.

[0092] In one embodiment, the electrostatic protection device further includes: a third pad; the third N-type heavily doped region 14' is connected to the third pad.

[0093] In the embodiment of the present application, the first pad is a ground pad; the second pad is an input / output pad; the third pad is a power supply pad.

[0094] In one embodiment, the pulse monitoring unit 40' includes a resistor R and a capacitor C;

[0095] The gate 30' of the NMOS transistor is connected to the first pad through the resistor R and is connected to the third pad through the capacitor C.

[0096] The pulse monitoring unit 40' is an RC coupling circuit, and the NMOS transistor is an RC-triggered NMOS transistor.

[0097] In one embodiment, the first P-type heavily doped region 13', the first N-type heavily doped region 11', and the P-type substrate 21' form a parasitic PNP transistor; the first N-type heavily doped region 11', the P-type substrate 21', and the second N-type heavily doped region 12' form a parasitic NPN transistor (not shown in the figure).

[0098] An embodiment of the present application further provides an electronic device, which includes the electrostatic protection device described in any of the above embodiments and an electronic component connected to the electrostatic protection device.

[0099] Since the electrostatic protection device described in any of the above embodiments has better electrostatic protection ability, the electronic device also has the above advantages.

[0100] The electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or an intermediate product having the above electrostatic protection device, for example: a mobile phone motherboard having the electrostatic protection device, etc.

[0101] The above is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An electrostatic protection device, characterized in that, Comprising: P-type substrate; N-well, located within the P-type substrate; PMOS transistor, the PMOS transistor comprising a gate and first and second P-type heavily doped regions on both sides of the gate; Pulse monitoring unit, the gate of the PMOS transistor being controlled by the pulse monitoring unit; wherein, The first P-type heavily doped region straddles between the P-type substrate and the N-well, the P-type substrate is connected to a first pad, and the second P-type heavily doped region is connected to a second pad; Further comprising: a first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, and a third P-type heavily doped region; The first N-type heavily doped region, the third P-type heavily doped region, and the second N-type heavily doped region are located within the P-type substrate; The third N-type heavily doped region and the second P-type heavily doped region are located within the N-well; The third P-type heavily doped region and the second N-type heavily doped region are connected to the first pad; The first N-type heavily doped region is connected to the second pad; Third pad; the third N-type heavily doped region is connected to the third pad; The first pad is a ground pad; the second pad is an input / output pad; the third pad is a power supply pad.

2. The electrostatic protection device according to claim 1, wherein The second P-type heavily doped region, the N-well, and the P-type substrate form a parasitic PNP transistor; The N-well, the P-type substrate, and the second N-type heavily doped region form a parasitic NPN transistor.

3. The electrostatic protection device according to claim 1, wherein The first N-type heavily doped region and the third P-type heavily doped region form a first parasitic diode; The third P-type heavily doped region and the third N-type heavily doped region form a second parasitic diode; The second P-type heavily doped region and the third N-type heavily doped region form a third parasitic diode.

4. The electrostatic protection device according to claim 1, wherein The pulse monitoring unit includes a resistor R and a capacitor C; The gate of the PMOS transistor is connected to the third pad through the resistor R and is connected to the first pad through the capacitor C.

5. The electrostatic protection device according to claim 2, wherein The second P-type heavily doped region, the parasitic PNP transistor, the parasitic NPN transistor, and the second N-type heavily doped region form a first electrostatic current discharge path from the second pad to the first pad.

6. The electrostatic protection device according to claim 3, wherein The third P-type heavily doped region, the first parasitic diode, and the first N-type heavily doped region form a second electrostatic current discharge path from the first pad to the second pad.

7. The electrostatic protection device according to claim 3, wherein The second P-type heavily doped region, the third parasitic diode, and the third N-type heavily doped region form a third electrostatic current discharge path from the second pad to the third pad.

8. The electrostatic protection device according to claim 3, wherein The third P-type heavily doped region, the second parasitic diode, and the third N-type heavily doped region form a fourth electrostatic current discharge path from the first pad to the third pad.

9. An electronic device, characterized in that, The electronic device includes the electrostatic protection device according to any one of claims 1 to 8 and an electronic component connected to the electrostatic protection device.

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