Gate driving circuit and display panel including the same

Abstract

A gate driving circuit according to an embodiment and a display panel including the gate driving circuit are disclosed. The gate driving circuit according to the embodiment includes: a controller configured to charge and discharge a first control node and a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; an output unit including a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate high voltage to the output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change the charge voltage of the second control node in response to an output of the sensing unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0127043, filed on September 27, 2021, and Korean Patent Application No. 10-2021-0174587, filed on December 8, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The invention relates to a gate driving circuit and a display panel comprising the gate driving circuit. Background Art

[0004] The display device includes a liquid crystal display (LCD) device, an electroluminescent display device, a field luminescent display (FED) device, a plasma display panel (PDP), and the like.

[0005] According to the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices use self-luminous elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") to reproduce input images, and organic light-emitting display devices have the advantages of fast response speed, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Some display devices, such as a liquid crystal display device or an organic light emitting display device, include: a display panel including a plurality of sub-pixels; a driver outputting a driving signal for driving the display panel; a power supply generating power to be supplied to the display panel or the driver; etc. The driver includes a gate driver supplying a scan signal or a gate signal to the display panel and a data driver supplying a data signal to the display panel.

[0007] In such a display device, when driving signals such as a scan signal, an EM signal, and a data signal are supplied to a plurality of sub-pixels formed in a display panel, selected sub-pixels transmit light or directly emit light, thereby displaying an image.

[0008] In this case, the gate driver outputs a signal once during one frame, and maintains a low voltage through the conduction of the pull-down transistor for most of the remaining time. As described above, the pull-down transistor is driven for a long time and thus has poor reliability due to stress. Therefore, a method is needed that can improve the circuit life by reducing the stress applied to the pull-down transistor. Summary of the invention

[0009] The present invention is intended to meet all of the above needs and / or solve the above problems.

[0010] The present invention aims to provide a gate driving circuit capable of reducing stress applied to a pull-down transistor and a display panel including the gate driving circuit.

[0011] It should be noted that the objects of the present invention are not limited to the above objects, and other objects of the present invention will be apparent to those skilled in the art from the following description.

[0012] The gate drive circuit of the present invention includes: a controller, which is configured to charge and discharge a first control node and a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; an output unit, which includes a pull-up transistor and a pull-down transistor, wherein the pull-up transistor is configured to apply a gate high voltage to the output node in response to a charging voltage of the first control node, and the pull-down transistor is configured to apply a gate low voltage to the output node in response to a charging voltage of the second control node; a sensing unit, which is configured to sense a threshold voltage of the pull-down transistor; and a compensation unit, which is configured to change the charging voltage of the second control node in response to an output of the sensing unit.

[0013] The display panel of the present invention includes: a data driver configured to output a data voltage; a gate driver configured to output a gate signal according to a voltage of a first control node and a voltage of a second control node, wherein the first control node pulls up the output voltage and the second control node pulls down the output voltage; and a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, wherein the gate driver includes: a controller configured to charge and discharge the first control node and the second control node; an output unit including a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate signal of a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate signal of a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change the charge voltage of the second control node in response to an output of the sensing unit.

[0014] In the present invention, the stress of the pull-down transistor can be reduced by sensing the threshold voltage of the pull-down transistor in the output unit of the gate driving circuit and changing the voltage applied to the QB node or the gate node of the pull-down transistor according to the sensed threshold voltage, thereby improving the circuit life.

[0015] In the present invention, since the initial voltage applied to the QB node is low, the gate-source voltage of the pull-down transistor is reduced, so that the increase of the threshold voltage of the pull-down transistor can be delayed.

[0016] The effects of the present invention are not limited to the above effects, and those skilled in the art will clearly understand other effects not mentioned above based on the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art through the exemplary embodiments described in detail with reference to the accompanying drawings. In the accompanying drawings:

[0018] Figure 1 is a view illustrating a gate driving circuit according to a first embodiment of the present invention;

[0019] Figure 2 It is a graphic Figure 1 A view of the configuration of the sensing unit shown;

[0020] Figure 3 It is a graphic Figure 2 The waveform diagram of the input / output signal of the sensing unit and the voltage of the node shown;

[0021] Figure 4 It is a graphic Figure 1 A view of another configuration of the sensing unit is shown;

[0022] Figure 5 It is a graphic Figure 4 The waveform diagram of the input / output signal of the sensing unit and the voltage of the node shown;

[0023] Figure 6 It is a graphic Figure 1 A view of yet another configuration of the sensing unit is shown;

[0024] Figure 7 It is a graphic Figure 6 The waveform diagram of the input / output signal of the sensing unit and the voltage of the node shown;

[0025] Fig. 8A and 8B Is used to describe Figure 1 A diagram showing the variation in threshold voltage of a pull-down transistor;

[0026] Fig. 9 It is a graphic Figure 1 A view of the configuration of the compensation unit shown;

[0027] Fig.10 is a view illustrating a gate driving circuit according to a second embodiment of the present invention;

[0028] Fig.11 is a waveform diagram illustrating input / output signals of a gate drive circuit and voltages of nodes;

[0029] Fig.12 is a view illustrating a gate driving circuit according to a third embodiment of the present invention;

[0030] Fig.13 is a waveform diagram illustrating input / output signals of a gate drive circuit and voltages of nodes;

[0031] Fig.14 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0032] Fig.15 It is a graphic Fig.14 A cross-sectional view of the structure of the display panel shown;

[0033] Fig.16A and 16B is a view for describing the position of a gate driver according to an embodiment;

[0034] Fig.17 is a view illustrating a practical implementation circuit of a gate driver according to an embodiment;

[0035] Fig.18 It is a graphic Fig.17 The waveform diagram of the input / output signal and the voltage of the node of the gate driver shown;

[0036] Fig.19 is a view illustrating a sensing result (simulation result) of a threshold voltage of a pull-down transistor. DETAILED DESCRIPTION

[0037] The advantages and features of the present invention and their implementation methods will be more clearly understood through the following embodiments described with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms. The embodiments of the present invention will make the disclosure of the present invention complete and enable those skilled in the art to fully understand the scope of the present invention. The present invention is only limited within the scope of the attached claims.

[0038] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Similar reference numerals generally represent similar elements throughout the specification. In addition, in describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0039] As used herein, terms such as “including,” “comprising,” and “having” are generally intended to allow for the addition of other components unless these terms are used with the term “only.”

[0040] Even if not explicitly described, the components are construed as including the usual error range.

[0041] When terms such as “on,” “over,” “below,” and “after” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms “immediately” or “directly.”

[0042] Terms such as “first”, “second”, etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by sequence numbers preceding these components or names of the components.

[0043] The same reference numerals may substantially refer to the same elements throughout the specification.

[0044] The following embodiments may be combined or combined with each other in part or in whole and may be technically related and operated in various ways. These embodiments may be implemented independently of each other or in association with each other.

[0045] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a view illustrating a gate driving circuit according to a first embodiment of the present invention.

[0047] Reference Figure 1 According to the first embodiment of the present invention, the gate driving circuit may include: a first control node for pulling up the output voltage (hereinafter referred to as the "Q node"); a second control node for pulling down the output voltage (hereinafter referred to as the "QB" node); a controller 120-1; an output unit 120-2; a sensing unit 120-3 and a compensation unit 120-4.

[0048] The controller 120 - 1 may be used to charge and discharge the first control node and the second control node.

[0049] The output unit 120-2 may output a gate signal in response to the charging voltages of the first control node and the second control node. The output unit 120-2 may include a pull-up transistor and a pull-down transistor. The pull-up transistor may output a gate high voltage to the output node in response to the charging voltage of the first control node, and the pull-down transistor may output a gate low voltage to the output node in response to the charging voltage of the second control node.

[0050] The sensing unit 120 - 3 may sense a threshold voltage of the pull-down transistor.

[0051] The compensation unit 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. In this case, in an embodiment, the high potential voltage line that applies the high potential voltage to the first control node and the second control node may be separated to apply the first high potential voltage to the first control node via the first high potential voltage GVDD_1 line and apply the second high potential voltage to the second control node via the second high potential voltage GVDD_2 line. Therefore, the compensation unit 120-4 may change the charging voltage of the second control node by changing the magnitude of the second high potential voltage applied via the second high potential voltage GVDD_2 line in response to the output of the sensing unit.

[0052] Figure 2 It is a graphic Figure 1 A view of the configuration of the sensing unit shown; Figure 3 It is a graphic Figure 2 1 and 2 are waveform diagrams of the input / output signals of the sensing unit and the voltages of the nodes.

[0053] according to Figure 2 and Figure 3 According to the embodiment, the sensing unit 120-3 may include a first sensing unit 120-3a formed by a first switching element M01 and a second sensing unit 120-3b formed by a second switching element M02. For example, the first sensing unit may apply an initialization voltage to the second control node, and the second sensing unit may sense a threshold voltage of the pull-down transistor.

[0054] When the gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 may be turned on to apply a high potential voltage to the second control node QB. The first switch element M01 includes a gate to which the gate signal Gate1 is applied, a first electrode connected to a high potential voltage line to which the high potential voltage GVDD is applied, and a second electrode connected to the second control node.

[0055] When the gate signal is a high voltage greater than or equal to the gate turn-on voltage, the second switch element M02 can be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The second switch element M02 includes a gate to which the gate signal Gate1 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node GOUT(n).

[0056] like Figure 3 As shown, the first switching element M01 and the second switching element M02 may be turned on during a section in which a high voltage of the first gate signal is maintained to sense a threshold voltage Vth of the pull-down transistor.

[0057] Figure 4 It is a graphic Figure 1A view of another configuration of the sensing unit is shown; Figure 5 It is a graphic Figure 4 1 and 2 are waveform diagrams of the input / output signals of the sensing unit and the voltages of the nodes.

[0058] Reference Figure 4 and Figure 5 , the sensing unit 120 - 3 according to the embodiment may include a first sensing unit 120 - 3 a formed by a first switching element M01 and a capacitor C, and a second sensing unit 120 - 3 b formed by a second switching element M02 .

[0059] When the gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 can be turned on to apply a high potential voltage to the second control node. The first switch element M01 includes a gate to which the gate signal Gate1 is applied, a first electrode connected to the high potential voltage line, and a second electrode connected to the second control node.

[0060] When the gate signal is a high voltage greater than or equal to the gate turn-on voltage, the second switch element M02 can be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The second switch element M02 includes a gate to which the gate signal Gate1 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node GOUT(n).

[0061] The capacitor C is connected between the gate and source nodes of the first switching element M01. The capacitor C can be used to form a bootstrapping voltage at the gate node.

[0062] like Figure 5 As shown, the first switching element M01 and the second switching element M02 may be turned on during a section where the high voltage of the first gate signal is maintained to sense the threshold voltage Vth of the pull-down transistor. In this case, the bootstrap generated by the coupling of the capacitor C may improve the transmission performance.

[0063] Figure 6 It is a graphic Figure 1 A view of yet another configuration of the sensing unit is shown; Figure 7 It is a graphic Figure 6 1 and 2 are waveform diagrams of the input / output signals of the sensing unit and the voltages of the nodes.

[0064] Reference Figure 6 and Figure 7 , the sensing unit 120 - 3 according to the embodiment may include a first sensing unit 120 - 3 a formed by a first switching element M01, a second switching element M02, and a capacitor C, and a second sensing unit 120 - 3 b formed by a third switching element M03.

[0065] When the first gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 may be turned on to apply a high potential voltage to the first node n1. The first switch element M01 includes a gate to which the first gate signal Gate1 is applied, a first electrode connected to a high potential voltage line to which a high potential voltage GVDD is applied, and a second electrode connected to the first node n1.

[0066] When the voltage of the first node n1 is a high voltage greater than or equal to the gate turn-on voltage, the second switch element M02 may be turned on to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to the first node n1, a first electrode connected to a high potential voltage line to which the high potential voltage GVDD is applied, and a second electrode connected to the second control node.

[0067] When the second gate signal is a high voltage greater than or equal to the gate-on voltage, the third switch element M03 may be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal Gate2 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node GOUT(n).

[0068] The capacitor C is connected between the signal line to which the second gate signal Gate2 is applied and the first node n1. The capacitor C may be used to form a bootstrap voltage at the first node.

[0069] like Figure 7 As shown, the section where the threshold voltage is sensed may include: a first section where the high voltage of the first gate signal is maintained and a second section where the high voltage of the second gate signal is maintained. The first switching element M01 and the second switching element M02 may be turned on in the first section, and the second switching element M02 and the third switching element M03 may be turned on in the second section. In this case, the sensing performance, i.e., the transmission performance, may be improved through the bootstrapping generated by the coupling of the capacitor C.

[0070] Fig. 8A and 8B Is used to describe Figure 1 A view showing the variation in threshold voltage of a pull-down transistor is shown.

[0071] Reference Fig. 8A In the comparative example, when the high potential voltage applied to the second control node is a fixed voltage, an increase in the threshold voltage Vth may occur because the initial high potential voltage is applied at a low level and thus the initial gate-source voltage Vgs of the pull-down transistor is formed to be higher.

[0072] In this case, the gate-source voltage Vgs may be defined as Equation 1 below.

[0073] [Equation 1]

[0074] Vgs=Vg-Vs-Vth=GVDD-GVSS–Vth

[0075] Here, Vg is a voltage of a gate node, Vs is a voltage of a source node, Vth is a threshold voltage, GVDD is a high potential voltage, and GVSS is a low potential voltage.

[0076] The amount of change in the threshold voltage (ΔVth) can be expressed as in Equation 2 below.

[0077] [Equation 2]

[0078]

[0079] Here, t represents time, τ represents the time constant, β represents the dispersion expression constant, and E A represents activation energy, V represents frequency, k represents the Boltzmann constant, and T represents temperature.

[0080] Reference Figure 8B In an embodiment, when the high potential voltage applied to the second control node is changed (to a variable voltage), the initial high potential voltage is applied at a low level and increases by sensing the threshold voltage. Since the initial high potential voltage is applied at a low level and thus the initial gate-source voltage Vgs of the pull-down transistor is formed to be low, the increase of the threshold voltage Vth can be delayed.

[0081] Since the high potential voltage gradually increases through the sensing of the threshold voltage, the increase of the threshold voltage Vth is delayed by a corresponding degree, and thus the life of the transistor may also be increased.

[0082] Fig. 9 It is a graphic Figure 1 A view of the configuration of the compensation unit is shown.

[0083] Reference Fig. 9 , the compensation unit according to the embodiment may include an analog-to-digital converter (ADC) 120 - 4 a and a compensation voltage generating circuit 120 - 4 b.

[0084] The analog-to-digital converter 120 - 4 a may convert a voltage sensed through the sensing line, ie, a threshold voltage of the pull-down transistor, into digital data.

[0085] The compensation voltage generating circuit 120-4b may change the magnitude of the high potential voltage provided via the high potential voltage line connected to the compensation unit based on the converted digital data and the lookup table (LUT) 120-4c, and apply the high potential voltage to the QB node. In this case, the compensation voltage generating circuit 120-4b may change the high potential voltage in proportion (directly proportional) to the sensed threshold voltage.

[0086] For example, the compensation voltage generating circuit 120-4b can change the amplitude of the high potential voltage applied to the QB node via the power management integrated circuit (PMIC) by determining the amplitude of the high potential voltage based on the converted digital data and the lookup table, and inputting an indication signal to instruct the change to the high potential voltage of the determined amplitude to the power management integrated circuit (PMIC).

[0087] Fig.10 is a view illustrating a gate driving circuit according to a second embodiment of the present invention; Fig.11 The diagram is a waveform diagram illustrating input / output signals of a gate driving circuit and voltages of nodes.

[0088] Reference Fig.10 and 11 , the gate driving circuit according to the second embodiment of the present invention includes: a controller 120 - 1 ; an output unit 120 - 2 ; a sensing unit 120 - 3 composed of a first sensing unit 120 - 3 a and a second sensing unit 120 - 3 b , and a compensation unit 120 - 4 .

[0089] The controller 120-1 may be used to charge and discharge the first control node and the second control node. The controller 120-1 may include a first transistor T1, a third transistor T3, a 3Nth transistor T3N, a fourth transistor T4, a 4Nth transistor T4N, a fifth transistor T5, and a 5Qth transistor T5Q.

[0090] The first transistor T1 may provide a gate-on voltage VGH to the Q node in response to a start pulse VST received via the VST terminal. The first transistor T1 includes a gate connected to the VST terminal, a high potential voltage line to which a high potential voltage GVDD_1 is applied, and a second electrode connected to the Q node.

[0091] The third transistor T3 may be turned on in response to a carry signal VNEXT of a next signal transmission unit received via the VNEXT terminal to discharge the Q node. The third transistor T3 includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line to which the low potential voltage GVSS0 is applied.

[0092] The 3Nth transistor T3N may discharge the Q node in response to the voltage of the QB node. The 3Nth transistor T3N includes a gate connected to the QB node, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line to which the low potential voltage GVSS0 is applied.

[0093] The fourth transistor T4 may be turned on by the high potential voltage GVDD_2 and may transmit the high potential voltage applied to the high potential voltage line to the QB node. The fourth transistor T4 includes a gate and a first electrode commonly connected to the high potential voltage line, and a second electrode connected to the QB node.

[0094] The 4N transistor T4N may be turned on in response to a carry signal VNEXT of a subsequent signal transmission unit received via a VNEXT terminal to provide a high potential voltage GVDD_2 to a QB node to charge the QB node to a voltage greater than or equal to a gate turn-on voltage VGH. The 4N transistor T4N includes a gate connected to the VNEXT terminal, a first electrode connected to a high potential voltage line, and a second electrode connected to the QB node.

[0095] The fifth transistor T5 connects the QB node to the low potential voltage line in response to the start pulse VST received via the VST terminal to discharge the QB node to the low potential voltage GVSS0. The fifth transistor T5 includes a gate connected to the VST terminal, a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line.

[0096] When the voltage of the Q node Q is a high voltage greater than or equal to the gate-on voltage VGH, the 5Q transistor T5Q is turned on and connects the QB node to the low potential voltage line to discharge the QB node to the low potential voltage. The 5Q transistor T5Q includes a gate connected to the Q node Q, a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line.

[0097] The output unit 120-2 may output a gate signal in response to the charging voltage of the first control node and the second control node. The output unit 120-2 may include buffer transistors T6 and T7 that output gate signals. The buffer transistors T6 and T7 may be divided into a pull-up transistor T6 that is turned on based on the potential of the Q node Q and a pull-down transistor T7 that is turned on based on the potential of the QB node QB. The pull-up transistor T6 includes a gate connected to the Q node Q, a first electrode connected to a clock signal line to which the clock signal GCLK is applied, and a second electrode connected to the output terminal GOUT (n). The pull-down transistor T7 includes a gate connected to the QB node QB, a first electrode connected to the output terminal GOUT (n), and a second electrode connected to the low potential voltage GVSS0 line.

[0098] The sensing unit 120-3 may sense a threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 120-3a formed by a first switching element M01, a second switching element M02, and a capacitor C, and a second sensing unit 120-3b formed by a third switching element M03.

[0099] When the first gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 may be turned on to apply a high potential voltage to the first node n1. The first switch element M01 includes a gate to which the first gate signal Gate1 is applied, a first electrode connected to a high potential voltage line to which a high potential voltage GVDD is applied, and a second electrode connected to the first node n1.

[0100] When the voltage of the first node n1 is a high voltage greater than or equal to the gate turn-on voltage, the second switch element M02 may be turned on to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to the first node n1, a first electrode connected to a high potential voltage line to which the high potential voltage GVDD is applied, and a second electrode connected to the second control node.

[0101] When the second gate signal is a high voltage greater than or equal to the gate-on voltage, the third switch element M03 may be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal Gate2 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node GOUT(n).

[0102] The capacitor C is connected between the signal line to which the second gate signal Gate2 is applied and the first node n1. The capacitor C may be used to form a bootstrap voltage at the first node.

[0103] The compensation unit 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. The compensation unit 120-4 may change the second high potential voltage applied to the second high potential voltage GVDD_2 line connected to the second control node in response to the output of the sensing unit.

[0104] The compensation unit 120 - 4 may change the second high potential voltage applied to the second high potential voltage GVDD_2 line in proportion to the threshold voltage of the pull-down transistor T7 sensed by the sensing unit.

[0105] Fig.12 is a view illustrating a gate driving circuit according to a third embodiment of the present invention; Fig.13 The diagram is a waveform diagram illustrating input / output signals of a gate driving circuit and voltages of nodes.

[0106] Reference Fig.12and 13 The gate driving circuit according to the third embodiment includes: a controller 120 - 1 ; an output unit 120 - 2 ; a sensing unit 120 - 3 composed of a first sensing unit 120 - 3 a and a second sensing unit 120 - 3 b , and a compensation unit 120 - 4 .

[0107] The controller 120 - 1 may be used to charge and discharge the first control node. The controller 120 - 1 may include a first transistor T1 , a third transistor T3 , a fourth transistor T4 , and a fifth transistor T5 .

[0108] The first transistor T1 may provide a gate-on voltage VGH to the Q node in response to a start pulse VST(N-2) received via a VST terminal (start pulse terminal). The first transistor T1 includes a gate and a first electrode commonly connected to the VST terminal, and a second electrode connected to the Q node. Fig.13 The Vout(N-2) shown corresponds to the start pulse VST(N-2).

[0109] The third transistor T3 may be turned on in response to a carry signal VNEXT(N+2) of a subsequent signal transmission unit received via a VNEXT terminal (carry signal terminal) to discharge the Q node. The third transistor T3 includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line to which a low potential voltage GVSS0 is applied. Fig.13 Vout(N+2) shown corresponds to the carry signal VNEXT(N+2).

[0110] The fourth transistor T4 may discharge the Q node in response to a reset signal Vreset received via a VRESET terminal (reset signal terminal). The fourth transistor T4 includes a gate connected to the VRESET terminal, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line.

[0111] The fifth transistor T5 may be turned on in response to the clock signal CLK(N-1) of the previous signal transmission unit to connect the Q node to the output terminal VOUT(N-1) of the previous signal transmission unit. The fifth transistor T5 includes a gate to which the clock signal of the previous signal transmission unit is applied, a first electrode connected to the Q node, and a second electrode connected to the output terminal of the previous signal transmission unit.

[0112] The output unit 120-2 may output a gate signal to the output terminal GOUT(n) in response to the charging voltage of the first control node Q and the second control node QB. The output unit 120-2 may include buffer transistors T6 and T7 that output the gate signal. The buffer transistors T6 and T7 may be divided into a pull-up transistor T6 that is turned on based on the potential of the Q node Q and a pull-down transistor T7 that is turned on based on the potential of the clock signal CLK(N+2) of the subsequent signal transmission unit. The pull-up transistor T6 includes a gate connected to the Q node Q, a first electrode connected to the clock signal line CLK to which the clock signal CLK(N) is applied, and a second electrode connected to the output terminal GOUT(n). The pull-down transistor T7 includes a gate to which the clock signal CLK(n+2) of the subsequent signal transmission unit is applied, a first electrode connected to the output terminal GOUT(n), and a second electrode connected to the low potential voltage GVSS0 line.

[0113] The sensing unit 120-3 may sense a threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 120-3a formed by a first switching element M01, a second switching element M02, and a capacitor C, and a second sensing unit 120-3b formed by a third switching element M03.

[0114] When the first gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 may be turned on to apply a high potential voltage to the first node. The first switch element M01 includes a gate to which the first gate signal Gate1 is applied, a first electrode connected to a high potential voltage line to which a high potential voltage GVDD is applied, and a second electrode connected to the first node.

[0115] When the voltage of the first node is a high voltage greater than or equal to the gate-on voltage, the second switch element M02 may be turned on to apply the high potential voltage to the gate node of the pull-down transistor. The second switch element M02 includes a gate connected to the first node, a first electrode connected to a high potential voltage line to which the high potential voltage GVDD is applied, and a second electrode connected to the gate node of the pull-down transistor.

[0116] When the second gate signal is a high voltage greater than or equal to the gate-on voltage, the third switch element M03 may be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal Gate2 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node GOUT(n).

[0117] The capacitor C is connected between the signal line to which the second gate signal Gate2 is applied and the first node. The capacitor C may be used to form a bootstrap voltage at the first node.

[0118] The compensation unit 120-4 may change the voltage of the gate node of the pull-down transistor in response to the output of the sensing unit. The compensation unit 120-4 may change the voltage or amplitude of the second clock signal Clock2 applied to the second clock signal line connected to the gate node in response to the output of the sensing unit.

[0119] The compensation unit 120 - 4 may change the voltage or amplitude of the second clock signal Clock2 applied to the second clock signal line in proportion to the threshold voltage of the pull-down transistor T7 sensed by the sensing unit.

[0120] Fig.14 is a block diagram illustrating a display device according to an embodiment of the present invention; Fig.15 It is a graphic Fig.14 A view of a cross-sectional structure of a display panel is shown.

[0121] Reference Fig.14 and 15 , the display device according to the embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0122] The display panel 100 may be a display panel of a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines that are commonly connected to the pixels. The power lines may include a power line to which a pixel drive voltage ELVDD is applied, a power line to which an initialization voltage Vinit is applied, a power line to which a reference voltage Vref is applied, and a power line to which a low potential power supply voltage ELVSS is applied. These power lines are commonly connected to the pixels.

[0123] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Pixels arranged in a column direction Y along a data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0124] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device that displays an image on a screen and an actual background can be seen.

[0125] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be disposed on a rear panel of the plastic OLED panel, and a pixel array AA and a light emitting element may be formed on the organic film.

[0126] In order to realize color, each pixel 101 can be divided into a red sub-pixel (hereinafter referred to as an R sub-pixel), a green sub-pixel (hereinafter referred to as a G sub-pixel) and a blue sub-pixel (hereinafter referred to as a B sub-pixel). Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit. The pixel circuit is connected to a data line, a gate line and a power line.

[0127] Pixels may be arranged as actual color pixels and Pentile pixels. Pentile pixels may achieve a higher resolution than actual color pixels by driving two sub-pixels with different colors into one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may use the color of light emitted from adjacent pixels to compensate for the insufficient color representation in each pixel.

[0128] The touch sensor may be provided on the display panel 100. The touch input may be sensed using a separate touch sensor or may be sensed via a pixel. The touch sensor may be provided as an on-cell type or an add-on type on the screen of the display panel, or may be implemented as an in-cell type touch sensor built into the pixel array AA.

[0129] like Fig.15 As shown, when viewed from a cross-sectional structure, the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0130] The circuit layer 12 may include: a pixel circuit connected to wirings such as data lines, gate lines, and power lines; a gate driver (GIP) connected to the gate lines; etc. The wirings and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer including a semiconductor material.

[0131] The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. The light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting element EL of the light emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0132] The light emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto.

[0133] An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. The organic light emitting diode having the tandem structure may improve the brightness and lifespan of a pixel.

[0134] The encapsulation layer 16 covers the light emitting element layer 14 to seal the circuit layer 12 and the light emitting element layer 14. The encapsulation layer 16 may have a multilayer insulation structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked into multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light emitting element layer 14.

[0135] The touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include an insulating layer and a metal wiring pattern that form a capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase delay film are bonded, or a circular polarizing plate. A cover glass may be bonded to the polarizing plate.

[0136] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green and blue color filters and a black matrix pattern. The color filter layer may replace the polarizing plate and improve the color purity by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 having a higher light transmittance than the polarizing plate to the display panel, the light transmittance of the display panel 100 may be improved, and the thickness and flexibility of the display panel 100 may be improved. The glass cover may be adhered to the color filter layer.

[0137] The power supply 140 generates a DC power required for driving the pixel array AA of the display panel 100 and the display panel driver by using a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc. The power supply 140 may adjust a DC input voltage from a host system (not shown) to thereby generate DC voltages such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, a pixel driving voltage ELVDD, a pixel low potential power supply voltage ELVSS, a reference voltage Vref, an initialization voltage Vinit, an anode voltage Vano, etc. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel driving voltage ELVDD, the pixel low potential power supply voltage ELVSS, the reference voltage Vref, the initialization voltage Vinit, the anode voltage Vano, etc. are provided to the pixel in common.

[0138] The display panel driver writes pixel data (digital data) of an input image to pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0139] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0140] The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0141] The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is configured to: Figure 1 The touch sensor driver may be integrated into one driver integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, the touch sensor driver, etc. may be integrated into one driver integrated circuit (IC).

[0142] The display panel driver may operate in a low-speed drive mode under the control of a timing controller (TCON) 130. The low-speed drive mode may be set to reduce the power consumption of the display device when an input image is analyzed and the input image does not change within a preset number of frames. In the low-speed drive mode, the power consumption of the display panel driver and the display panel 100 may be reduced by reducing the refresh rate of the pixels when a still image is input for a predetermined time or longer. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in a standby mode or a user command or an input image is not input to the display panel driver for a predetermined time or longer, the display panel driver may operate in a low-speed drive mode.

[0143] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage at each frame period using a digital-to-analog converter (DAC). For each grayscale, the gamma reference voltage VGMA is divided via a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output via an output buffer AMP in each channel of the data driver 110.

[0144] The gate driver 120 may be implemented as a GIP (gate in panel) circuit directly formed on the circuit layer 12 of the display panel 100 together with the TFT array of the pixel array AA. The gate in panel (GIP) circuit may be provided on the border area BZ which is the non-display area of ​​the display panel 100, or may be dispersed in the pixel array on which the input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include a scan pulse, a light emitting control pulse (hereinafter referred to as an "EM pulse"), an initialization pulse, and a sensing pulse. Therefore, the gate driver 120 may include a scan driver 121, a light emitting control driver 122, an initialization driver 123, and the like.

[0145] The shift register of the gate driver 120 outputs a pulse of a gate signal in response to a start pulse and a shift clock from the timing controller 130 , and shifts the pulse according to the shift clock timing.

[0146] In this case, the gate driver 120 may be implemented as Figure 1 , 3, 6, and 8 are gate drivers capable of reducing leakage current while reducing the number of transistors. In the present invention, all transistors in a display panel including a data driver, a gate driver, and a plurality of sub-pixels can be implemented using oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

[0147] The timing controller 130 receives the digital video data DATA of the input image and the timing signal synchronized therewith from the host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a cycle of one horizontal period (1H).

[0148] The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a vehicle system. The host system may scale the image signal from the video source according to the resolution of the display panel 100 and transmit the image signal to the timing controller 130 together with the timing signal.

[0149] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driver at a frame frequency of input frame frequency×i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase Alternation Line) system. The timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz, so as to reduce the refresh rate of the pixel in the low-speed driving mode.

[0150] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver, thereby synchronizing the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0151] The voltage level of the gate timing control signal output from the timing controller 130 may be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL via a level shifter (not shown), and then provided to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing control signal includes a start pulse and a shift clock.

[0152] Fig.16A and 16B is a view for describing the position of a gate driver according to an embodiment; Fig.17 is a view illustrating a practical implementation circuit of a gate driver according to an embodiment; Fig.18 It is a graphic Fig.17 The waveform diagram of the input / output signal and the voltage of the node of the gate driver shown; Fig.19 is a view illustrating a sensing result (simulation result) of a threshold voltage of a pull-down transistor. Here, an example in which a gate driver is implemented as a scan driver will be described.

[0153] Reference Fig.16A and 16B The scan driver according to the embodiment may be implemented as a structure in which a shift register is disposed in the left and right non-display areas of the display panel. The shift register may include a plurality of signal transmission units ST and a plurality of dummy signal transmission units D_ST, respectively.

[0154] In this case, a plurality of signal transmission units ST are connected to the gate lines, respectively. Each of the plurality of dummy signal transmission units D_ST may be disposed at the uppermost end portions A and B and the lowermost end portions C and D located at both sides of the display panel PNL. Here, a case where four dummy signal transmission units D_ST are formed is shown.

[0155] Each of the plurality of dummy signal transmission units disposed at the uppermost end and the lowermost end of the display panel may be implemented to include Figure 1 The reason why the sensing unit and the compensation unit are included only in the dummy signal transmission unit (only disposed at the uppermost and lowermost ends of the display panel) is to minimize the increase of the frame of the display panel outside the active area.

[0156] Reference Fig.17 and Fig.18, the virtual signal transmission unit according to the embodiment of the present invention may be implemented to include: a controller 120-1; an output unit 120-2; a sensing unit 120-3 consisting of a first sensing unit 120-3a and a second sensing unit 120-3b, and a compensation unit 120-4.

[0157] The controller 120-1 may be used to charge and discharge the first control node and the second control node. The controller 120-1 may include a first transistor T1, a 1A transistor T1A, a transistor T3, a 3A transistor T3A, a 3q transistor T3q, a 3n transistor T3n, a 3nA transistor T3nA, a 3nB transistor T3nB, a 3nC transistor T3nC, a fourth transistor T4, a 41 transistor T41, a 4q transistor T4q, a fifth transistor T5, and a 5q transistor T5q.

[0158] The first transistor T1 is turned on by the N-2 carry signal applied through the N-2 carry signal line C(n-2), and charges the Q node Q based on the N-2 carry signal. The first transistor T1 includes a gate and a first electrode connected to the N-2 carry signal line C(n-2), and a second electrode connected to the Q node Q.

[0159] The 1A-th transistor T1A is turned on by the N-2-th carry signal applied through the N-2-th carry signal line C(n-2), and charges the Q node Q based on the N-2-th carry signal. In the 1A-th transistor T1A, the gate is connected to the N-2-th carry signal line C(n-2), the first electrode is connected to the second electrode of the first transistor T1, and the second electrode is connected to the Q node Q.

[0160] The third transistor T3 is turned on through the QB node QB, and discharges the Q node Q to the third low potential voltage of the third low potential voltage GVSS2 line together with the 3A transistor T3A. In the third transistor T3, the gate is connected to the QB node QB, the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the 3A transistor T3A.

[0161] The 3A transistor T3A is turned on through the QB node QB, and discharges the Q node Q to the third low potential voltage of the third low potential voltage GVSS2 line together with the third transistor T3. In the 3A transistor T3A, the gate is connected to the QB node QB, the first electrode is connected to the second electrode of the third transistor T3, and the second electrode is connected to the third low potential voltage GVSS2 line.

[0162] The 3nth transistor T3n is turned on by the N+2th carry signal applied via the N+2th carry signal line C(n+2), and discharges the Q node Q to the third low potential voltage of the third low potential voltage GVSS2 line together with the 3nth transistor T3nA. In the 3nth transistor T3n, the gate is connected to the N+2th carry signal line C(n+2), the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the 3nth transistor T3nA.

[0163] The 3nA transistor T3nA is turned on by the N+2 carry signal applied via the N+2 carry signal line C(n+2), and discharges the Q node Q to the third low potential voltage of the third low potential voltage GVSS2 line together with the 3n transistor T3n. In the 3nA transistor T3nA, the gate is connected to the N+2 carry signal line C(n+2), the first electrode is connected to the second electrode of the 3n transistor T3n, and the second electrode is connected to the third low potential voltage GVSS2 line.

[0164] The 3q-th transistor T3q is turned on through the Q node Q and transmits the high potential voltage of the first high potential voltage GVDD_1 line to the Qh node. In the 3q-th transistor T3q, the gate is connected to the Q node Q, the first electrode is connected to the first high potential voltage GVDD_1 line, and the second electrode is connected to the Qh node Qh.

[0165] The 3nB transistor T3nB is turned on by the start pulse received via the VST terminal, and discharges the Q node Q and the Qh node Qh to the third low potential voltage of the third low potential voltage GVSS2 line together with the 3nC transistor T3nC. In the 3nB transistor T3nB, the gate is connected to the VST terminal, the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the 3nC transistor T3nC.

[0166] The 3nC transistor T3nC is turned on by the start pulse received via the VST terminal, and discharges the Q node Q and the Qh node Qh to the third low potential voltage of the third low potential voltage GVSS2 line together with the 3nB transistor T3nB. In the 3nC transistor T3nC, the gate is connected to the VST terminal, the first electrode is connected to the second electrode of the 3nB transistor T3nB, and the second electrode is connected to the third low potential voltage GVSS2 line.

[0167] The fourth transistor T4 is turned on by the second high potential voltage transmitted through the 41st transistor T41, and the QB node QB is charged to the second high potential voltage applied to the second high potential voltage GVDD_2 line. The first capacitor Ca is used to form a bootstrap voltage at the gate node of the fourth transistor T4. In the fourth transistor T4, the gate is connected to one end of the first capacitor Ca and the second electrode of the 41st transistor T41, the first electrode is connected to the second high potential voltage GVDD_2 line, and the second electrode is connected to the other end of the first capacitor Ca and the QB node QB.

[0168] The 41st transistor T41 is turned on by the second high potential voltage, and transmits the second high potential voltage applied to the second high potential voltage GVDD_2 line to the gate node of the fourth transistor T4. In the 41st transistor T41, the gate and the first electrode are connected to the second high potential voltage GVDD_2 line, and the second electrode is connected to the gate of the fourth transistor T4 and the first electrode of the 4qth transistor T4q.

[0169] When the voltage of the QB node is a high voltage greater than or equal to the gate-on voltage VGH, the 4q-th transistor T4q is turned on to connect the gate node of the fourth transistor T4 to the low potential voltage GVSS1 line, thereby discharging the gate node of the fourth transistor T4 to the low potential voltage. In the 4q-th transistor T4q, the gate is connected to the QB node, the first electrode is connected to the gate of the fourth transistor T4 and the second electrode of the 41st transistor T41, and the second electrode is connected to the low potential voltage GVSS1 line.

[0170] The fifth transistor T5 is turned on by the N-2 carry signal applied via the N-2 carry signal line C(n-2), and connects the QB node to the low potential voltage GVSS2 line, thereby discharging the QB node to the low potential voltage. The fifth transistor T5 includes a gate connected to the N-2 carry signal line C(n-2), a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line.

[0171] When the voltage of the Q node is a high voltage greater than or equal to the gate-on voltage VGH, the 5q-th transistor T5q is turned on to connect the QB node to the low potential voltage GVSS2 line, thereby discharging the QB node to the low potential voltage. The 5q-th transistor T5q includes a gate connected to the Q node Q, a second electrode connected to the QB node, and a second electrode connected to the low potential voltage GVSS2 line.

[0172] The output unit 120-2 may output a gate signal in response to the charge voltages of the first and second control nodes. The output unit 120-2 includes first buffer transistors T6cr and T7cr outputting a carry signal, second buffer transistors T6sc and T7sc outputting a scan signal, and third buffer transistors T6se and T7se.

[0173] The first buffer transistors T6cr and T7cr can be divided into a first pull-up transistor T6cr that is turned on based on the potential of the Q node Q and a first pull-down transistor T7cr that is turned on based on the potential of the QB node QB. In the first pull-up transistor T6cr, the gate is connected to the Q node Q, the first electrode is connected to the clock signal line SC_CRCLK(n), and the second electrode is connected to the output terminal Carry(n). In the first pull-down transistor T7cr, the gate is connected to the QB node QB, the first electrode is connected to the output terminal Carry(n), and the second electrode is connected to the low potential voltage GVSS2 line.

[0174] The second buffer transistors T6sc and T7sc can be divided into a second pull-up transistor T6sc that is turned on based on the potential of the Q node Q and a second pull-down transistor T7sc that is turned on based on the potential of the QB node QB. In the second pull-up transistor T6sc, the gate is connected to the Q node Q and one end of the second capacitor Cb, the first electrode is connected to the clock signal line SCCLK(n) to which the clock signal is applied, and the second electrode is connected to the other end of the second capacitor Cb and the output terminal SCOUT(n). In the second pull-down transistor T7sc, the gate is connected to the QB node QB, the first electrode is connected to the output terminal SCOUT(n), and the second electrode is connected to the low potential voltage GVSS0 line.

[0175] The third buffer transistors T6se and T7se can be divided into a third pull-up transistor T6se that is turned on based on the potential of the Q node Q and a third pull-down transistor T7se that is turned on based on the potential of the QB node QB. In the third pull-up transistor T6se, the gate is connected to the Q node Q, the first electrode is connected to the clock signal line SECLK (n), and the second electrode is connected to the output terminal SEOUT (n). In the third pull-down transistor T7se, the gate is connected to the QB node QB, the first electrode is connected to the output terminal SEOUT (n), and the second electrode is connected to the low potential voltage GVSS0 line.

[0176] The sensing unit 120-3 may sense a threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 120-3a formed by a first switching element M01, a second switching element M02, and a capacitor C, and a second sensing unit 120-3b formed by a third switching element M03.

[0177] When the first gate signal is a high voltage greater than or equal to the gate-on voltage, the first switch element M01 may be turned on to apply a high potential voltage to the first node n1. The first switch element M01 includes a gate to which the first gate signal Gate1 is applied, a first electrode connected to a high potential voltage line to which a high potential voltage GVDD is applied, and a second electrode connected to the first node n1.

[0178] When the voltage of the first node n1 is a high voltage greater than or equal to the gate turn-on voltage, the second switch element M02 may be turned on to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to the first node n1, a first electrode connected to a high potential voltage line to which the high potential voltage GVDD is applied, and a second electrode connected to the second control node.

[0179] When the second gate signal is a high voltage greater than or equal to the gate-on voltage, the third switch element M03 may be turned on to sense the threshold voltage of the pull-down transistor and transmit the threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal Gate2 is applied, a first electrode connected to the sensing line Sensing, and a second electrode connected to the output node SEOUT(n).

[0180] The capacitor C is connected between the signal line to which the second gate signal Gate2 is applied and the first node n1. The capacitor C may be used to form a bootstrap voltage at the first node.

[0181] The compensation unit 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. The compensation unit 120-4 may change the second high potential voltage applied to the second high potential voltage GVDD_2 line connected to the second control node in response to the output of the sensing unit.

[0182] The compensation unit 120 - 4 may change the second high potential voltage applied to the second high potential voltage GVDD_2 line in proportion to the threshold voltage of the pull-down transistors T7cr, T7sc, T7se sensed by the sensing unit.

[0183] Reference Fig.19 It can be seen that, in the dummy signal transmission unit according to the embodiment, the threshold voltage of the pull-down transistor is normally sensed via the sensing unit during the sensing section. It can be seen that even if the threshold voltage of the pull-down transistor changes, sensing is performed normally.

[0184] Although the embodiments of the present invention are described in more detail with reference to the accompanying drawings, the present invention is not limited thereto, and the present invention can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided only for illustrative purposes, and these embodiments are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the attached claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present invention.

Claims

1. A gate drive circuit, comprising: a controller configured to charge and discharge a first control node and a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; as well as a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit includes a first sensing unit and a second sensing unit. The first sensing unit includes a first switch element, the first switch element having a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode directly connected to the second control node, The second sensing unit includes a second switching element, wherein the second switching element has a gate to which the first gate signal is applied, a first electrode connected to the sensing node, and a second electrode directly connected to the output node.

2. The gate driving circuit according to claim 1, wherein the sensing unit comprises: the first sensing unit, the first sensing unit being configured to apply an initialization voltage to the second control node; as well as The second sensing unit is configured to sense a threshold voltage of the pull-down transistor.

3. A gate drive circuit, comprising: a controller configured to charge and discharge a first control node and a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; as well as a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit includes a first sensing unit and a second sensing unit. The first sensing unit comprises: a first switch element having a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode directly connected to the second control node; as well as a capacitor connected between the gate and the second electrode of the first switching element, The second sensing unit includes a second switching element, wherein the second switching element has a gate to which the first gate signal is applied, a first electrode connected to the sensing node, and a second electrode directly connected to the output node.

4. A gate drive circuit comprising: a controller configured to charge and discharge a first control node and a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; as well as a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit comprises: a first sensing unit configured to apply an initialization voltage to the second control node; and a second sensing unit configured to sense a threshold voltage of the pull-down transistor, The first sensing unit comprises: a first switching element having a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a first node; a second switching element having a gate connected to the first node, a first electrode connected to the high potential voltage line, and a second electrode directly connected to the second control node; and a capacitor connected between the first node and a signal line to which a second gate signal is applied, The second sensing unit includes a third switching element, wherein the third switching element has a gate to which the second gate signal is applied, a first electrode connected to a sensing node, and a second electrode directly connected to the output node.

5. The gate drive circuit according to claim 4, wherein: The section where the threshold voltage is sensed includes: a first section where the high voltage of the first gate signal is maintained and a second section where the high voltage of the second gate signal is maintained, The first switching element and the second switching element are turned on in the first section, The second switching element and the third switching element are conductive in the second section.

6. The gate driving circuit according to claim 1, comprising: a first high potential voltage line, the first high potential voltage line being configured to apply a first high potential voltage to the first control node; as well as A second high potential voltage line is configured to apply a second high potential voltage to the second control node. 7 . The gate driving circuit according to claim 6 , wherein the compensation unit changes the second high potential voltage according to a threshold voltage sensed from the sensing unit. 8 . The gate driving circuit according to claim 7 , wherein the compensation unit changes the second high potential voltage in proportion to the sensed threshold voltage.

9. The gate driving circuit according to claim 1, wherein: The second control node is a gate node of the pull-down transistor, The gate drive circuit further includes: a first clock signal line configured to apply a first clock signal to the first control node; and A second clock signal line is configured to apply a second clock signal to the second control node. 10 . The gate driving circuit of claim 9 , wherein the compensation unit changes an amplitude of the second clock signal according to a threshold voltage sensed from the sensing unit. 11 . The gate driving circuit of claim 9 , wherein the compensation unit changes the amplitude of the second clock signal in proportion to the sensed threshold voltage.

12. The gate driving circuit according to claim 1, wherein the compensation unit comprises: an analog-to-digital converter that converts the sensed threshold voltage into digital data; as well as A compensation voltage generating circuit changes the magnitude of a high potential voltage provided via a high potential voltage line connected to the compensation unit based on the converted digital data and a lookup table, and applies the high potential voltage to the second control node.

13. The gate driving circuit according to claim 1, wherein: The pull-up transistors include a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor that are turned on based on the potential of the first control node, The pull-down transistors include a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor that are turned on based on the potential of the second control node, The output unit also includes a capacitor, and the second pull-up transistor includes a gate connected to the first control node and one end of the capacitor, a first electrode connected to a clock signal line to which a clock signal is applied, and a second electrode connected to the other end of the capacitor and the output node.

14. The gate driving circuit according to claim 1, wherein the controller comprises: a first transistor including a gate and a first electrode commonly connected to a start pulse terminal, and a second electrode connected to the first control node; a third transistor including a gate connected to a carry signal terminal, a first electrode connected to the first control node, and a second electrode connected to a low potential voltage line to which a low potential voltage is applied; a fourth transistor including a gate connected to a reset signal terminal, a first electrode connected to the first control node, and a second electrode connected to the low potential voltage line; as well as A fifth transistor includes a gate to which a clock signal is applied, a first electrode connected to the first control node, and a second electrode connected to an output terminal.

15. A display panel, comprising: a data driver configured to output a data voltage; a gate driver configured to output a gate signal according to a voltage of a first control node and a voltage of a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; as well as a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, The gate driver comprises: a controller configured to charge and discharge the first control node and the second control node; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate signal of a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate signal of a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit includes a first sensing unit and a second sensing unit. The first sensing unit includes a first switch element, the first switch element having a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode directly connected to the second control node, The second sensing unit includes a second switching element, wherein the second switching element has a gate to which the first gate signal is applied, a first electrode connected to the sensing node, and a second electrode directly connected to the output node.

16. A display panel, comprising: a data driver configured to output a data voltage; a gate driver configured to output a gate signal according to a voltage of a first control node and a voltage of a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; as well as a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, The gate driver comprises: a controller configured to charge and discharge the first control node and the second control node; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate signal of a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate signal of a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit includes a first sensing unit and a second sensing unit. The first sensing unit comprises: a first switching element having a gate to which a gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode directly connected to the second control node; and a capacitor connected between the gate and the second electrode of the first switching element, The second sensing unit includes a second switching element, wherein the second switching element has a gate to which the gate signal is applied, a first electrode connected to the sensing node, and a second electrode directly connected to the output node.

17. A display panel, comprising: a data driver configured to output a data voltage; a gate driver configured to output a gate signal according to a voltage of a first control node and a voltage of a second control node, wherein the first control node pulls up an output voltage and the second control node pulls down the output voltage; as well as a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, The gate driver comprises: a controller configured to charge and discharge the first control node and the second control node; an output unit, the output unit comprising a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to apply a gate signal of a gate high voltage to an output node in response to a charge voltage of the first control node, and the pull-down transistor being configured to apply a gate signal of a gate low voltage to the output node in response to a charge voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit, The sensing unit comprises: a first sensing unit configured to apply an initialization voltage to the second control node; and a second sensing unit configured to sense a threshold voltage of the pull-down transistor, The first sensing unit comprises: a first switching element having a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a first node; a second switching element having a gate connected to the first node, a first electrode connected to the high potential voltage line, and a second electrode directly connected to the second control node; and a capacitor connected between the first node and a signal line to which a second gate signal is applied, The second sensing unit includes a third switching element, wherein the third switching element has a gate to which the second gate signal is applied, a first electrode connected to a sensing node, and a second electrode directly connected to the output node.

18. The display panel according to claim 15, wherein all transistors in the display panel including the data driver, the gate driver, and a plurality of sub-pixels are implemented using oxide thin film transistors including an n-channel type oxide semiconductor. 19 . The display panel of claim 15 , wherein the sensing unit and the compensation unit are disposed only at an uppermost end portion and a lowermost end portion of the display panel.

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