Test system and test method

Abstract

A test system includes a plurality of first latches, an X-to-Y compressor coupled to the plurality of first latches for compressing X-bit signals outputted from the plurality of first latches into Y-bit signals, X and Y being positive integers and X being greater than Y, at least one second latch coupled to the X-to-Y compressor for receiving the Y-bit signals to generate a scan output, wherein each of the first latches and the second latch forms a D-type flip-flop, and wherein the test system outputs the X-bit signals in a normal mode and outputs the scan output in a test mode.

Description

Technical Field

[0001] This invention relates to test systems and test methods, and in particular, to test systems and test methods that can reduce circuit area and signal delay. Background Technology

[0002] In existing technologies, test systems for SRAM (Static Random Access Memory) include a scan chain to test the signals input to the SRAM. However, this scan chain contains a large number of latches and multiplexers, which not only increases the circuit area but also increases the signal delay during scanning.

[0003] Therefore, a new testing system is needed to solve the above problems. Summary of the Invention

[0004] Therefore, one objective of this invention is to provide a test system that can reduce circuit area and signal delay time.

[0005] Another objective of this invention is to provide a testing method that can reduce circuit area and signal delay time.

[0006] An embodiment of the present invention discloses a test system comprising: a plurality of first latches; an X-to-Y compressor coupled to the plurality of first latches for compressing an X-bit signal output by the plurality of first latches into a Y-bit signal, wherein X and Y are positive integers and X is greater than Y; and at least one second latch coupled to the X-to-Y compressor for receiving the Y-bit signal to generate a scan output, wherein each of the first latches and the second latch forms a D-type flip-flop; wherein the test system outputs the X-bit signal in normal mode and outputs the scan output in test mode.

[0007] Another embodiment of the present invention discloses a testing method, comprising: compressing an X-bit signal output by a plurality of first latches into a Y-bit signal, wherein X and Y are positive integers and X is greater than Y; receiving the Y-bit signal with at least one second latch to generate a scan output, wherein each of the first latches and the second latches forms a D-type flip-flop; outputting the X-bit signal to a target electronic device in normal mode and outputting the scan output to the target electronic device in test mode.

[0008] Compared to existing technologies, the aforementioned embodiments can save a considerable number of components. For example, if the test system uses a built-in scan chain, each first latch must be paired with a second latch, and each first latch must be paired with a multiplexer for mode switching. The aforementioned architecture can significantly reduce the number of latches and multiplexers, which not only greatly reduces the circuit area but also reduces the signal delay caused by these components. Attached Figure Description

[0009] Figures 1 to 3 Circuit diagrams of test systems according to different embodiments of the present invention are shown.

[0010] Figure 4 and Figure 5 Circuit diagrams of test systems according to different embodiments of the present invention are shown, each having multiple sets of first latches.

[0011] Figure 6 A flowchart illustrating a test method according to an embodiment of the present invention is shown. Detailed Implementation

[0012] The present invention will be described below with reference to several embodiments. It should be noted that the components in each embodiment can be implemented by hardware (e.g., a device or circuit) or firmware (e.g., at least some programs written into a microprocessor). Furthermore, the terms "first," "second," and similar descriptions in the following description are only used to define different components, parameters, data, signals, or steps, and are not intended to limit their order. Moreover, the following embodiments are illustrated using SRAM as an example. However, the test system provided by the present invention is not limited to SRAM and can be used with other memories or other electronic devices.

[0013] like Figure 1As shown, the test system 100 includes: a plurality of first latches La11, La12…La1x, an X-to-Y compressor 101, and at least one second latch La2. The X-to-Y compressor 101 is coupled to the first latches La11, La12…La1x and is used to compress the X-bit signal XS output by the first latches La11, La12…La1x into a Y-bit signal YS, where X and Y are positive integers and X is greater than Y. In the following embodiment, Y is 1 and the number of second latches La2 is 1, but the number of second latches La2 may vary depending on Y. The second latch La2 is coupled to the X-to-Y compressor 101 and is used to receive the Y-bit signal YS to generate a scan output SO, wherein each of the first latches La11, La12…La1x and the second latch La2 form a D-type flip-flop. For example, the first latch La11 and the second latch La2 form a D-type flip-flop, while the first latch La12 and the second latch La2 form a D-type flip-flop. The test system 100 outputs an X-bit signal XS to the SRAM 103 in normal mode (or function mode) and outputs a scan output SO to the SRAM 103 in test mode (or scan mode). The scan output SO is then connected in series with a scan chain outside the SRAM 103.

[0014] In normal mode, the test system 100 outputs an X-bit signal XS to the SRAM 103 to enable normal operation of the SRAM 103, and in test mode, generates a scan output SO to the SRAM 103. In one embodiment, the scan output SO is received by a predetermined pin of the SRAM 103, while the X-bit signal XS may be received by different pins of the SRAM 103 depending on different requirements. The X-bit signal XS may contain different signals depending on different requirements. In one embodiment, the X-bit signal XS may contain at least one of the following signals: a data signal, an address signal, a write enable signal, or a memory enable signal of the SRAM 103. For example, the X-bit signal XS may contain a data signal and an address signal, or it may contain a write enable signal and a memory enable signal. The write enable signal is used to enable the write function of the SRAM 103, while the memory enable signal is used to enable the SRAM 103. In one embodiment, the test system 100 may further include a third latch La3, which is coupled to the data output terminal Q of the SRAM 103.

[0015] Apart from Figure 1 In addition to the testing mechanisms and paths shown, the testing system provided by this invention may also include other testing mechanisms and paths. Figure 2 A circuit diagram of a test system according to yet another embodiment of the present invention is shown. Besides Figure 1The test system 100 includes a first latch La11…La1x, an X-to-Y compressor 101, and a latch La2. Figure 2 The test system 200 also includes a fourth latch La4 and a first multiplexer MU1. The first multiplexer MU1 includes an output coupled to a second latch La2, a first input for receiving a Y-bit signal YS, and a second input for receiving the output of the fourth latch La4.

[0016] The fourth latch La4 and the second latch La2 can form a D-type flip-flop. Therefore, the fourth latch La4 and the second latch La2 can be regarded as a reserved additional scan path, which can be used to receive test signals from external inputs of the self-test system 200.

[0017] Therefore, in Figure 2 In the embodiment, the test system 200 outputs an X-bit signal XS to the SRAM 103 in normal mode and outputs a scan output SO to the SRAM 103 in test mode, and can receive test signals input from outside the test system 200 through the fourth buffer La4 in external test mode.

[0018] Apart from Figure 2 In addition to the paths shown, the testing system provided by this invention may also include other paths. Figure 3 A circuit diagram of a test system according to yet another embodiment of the present invention is shown. Besides Figure 1 The test system 100 includes a first latch La11…La1x, an X-to-Y compressor 101, and a latch La2. Figure 3 The test system 300 also includes a fourth latch La4, a first multiplexer MU1, and a second multiplexer MU2. The first multiplexer MU1 includes an output coupled to the second latch La2, a first input for receiving the Y-bit signal YS, and a second input for receiving the output of the fourth latch La4. The fourth latch La4 and the second latch La2 can form a D-type flip-flop. Therefore, the fourth latch La4 and the second latch La2 can be considered as reserved additional scan paths, which can be used to receive test signals input from outside the test system 300. The second multiplexer MU2 includes a first input for receiving the X-bit signal XS and a second input for receiving the output of the SRAM 103.

[0019] Therefore, in Figure 3 In this embodiment, the test system 300 outputs an X-bit signal XS to the SRAM 103 in normal mode and a scan output SO to the SRAM 103 in test mode, and can receive test signals input from outside the test system 300 in external test mode. Furthermore, the test system 300 outputs an X-bit signal XS to the second multiplexer MU2 in bypass mode. Figure 3In the embodiments, the path from the first latch La11…La1x to the X-to-Y compressor 101 to the first multiplexer MU1 to the second latch La2 can be regarded as a scan capture path in SRAM testing, and the path from the fourth latch La4 to the first multiplexer MU1 to the second latch La2 can be regarded as a scan shift path in SRAM testing. The path from the first latch La11…La1x to the second multiplexer MU2 can be regarded as a scan bypass path in SRAM testing.

[0020] The first latches La1, La2...Lax in the foregoing embodiments can be configured differently to meet different needs. Figure 4 A circuit diagram of a test system according to another embodiment of the present invention is shown, which has multiple sets of first latches. For example... Figure 4 As shown, the test system 400 includes two sets of first latches. One set of first latches contains N latches La11-La1N, used to generate an N-bit signal NS. The other set of first latches contains M latches La11'-La1M', used to generate an M-bit signal MS. N+M is greater than Y, and in one embodiment, Y is 1. Figure 4 In this embodiment, the M-bit signal MS includes the address signal, write enable signal, and memory enable signal of SRAM 103, and the N-bit signal NS is a data signal. In this case, the N-bit signal NS is received by the data terminal D of SRAM 103, while the M-bit signal MS is received by the address terminal ADDR, write enable terminal WE, and memory enable terminal ME of SRAM 103, respectively.

[0021] Therefore, in Figure 4 In the embodiment, in normal mode, the test system 400 outputs an N-bit signal NS to the data terminal D of the SRAM 103, and an M-bit signal MS to the address terminal ADDR, write enable terminal WE, and memory enable terminal ME of the SRAM 103. In test mode, the test system 400 generates a scan output SO to the SRAM 103.

[0022] The foregoing Figure 2 and Figure 3 The architecture can also be applied to Figure 4 Examples of implementations. Figure 5 A circuit diagram of a test system according to yet another embodiment of the present invention is shown. Figure 5 In addition to the 500 test system in the middle Figure 4 In addition to the components shown, it also includes a fourth latch La4, a first multiplexer MU1, and a second multiplexer MU2.

[0023] The fourth latch La4 and the second latch La2 can form a D-type flip-flop. Therefore, the fourth latch La4 and the second latch La2 can be regarded as a reserved additional scan path, which can be used to receive test signals from external inputs of the self-test system 500. The second multiplexer MU2 includes a first input terminal for receiving an N-bit signal NS and a second input terminal for receiving the output of SRAM 103. However, please note that in Figure 5 In one embodiment, the second multiplexer MU2 receives only the N-bit signal NS and not the M-bit signal MS.

[0024] Therefore, in Figure 5 In this embodiment, the test system 500 outputs an N-bit signal NS and an M-bit signal MS to the SRAM 103 in normal mode and outputs a scan output SO to the SRAM 103 in test mode. It can also receive test signals input from outside the test system 500 in external test mode. Furthermore, the test system 500 outputs an N-bit signal NS to the second multiplexer MU2 in bypass mode. Figure 5 In this embodiment, the path from the first latch La11…La1N, La11'…La1M' to the X-to-Y compressor 101 to the first multiplexer MU1 to the second latch La2 can be considered as a scan capture path in SRAM testing, and the path from the fourth latch La4 to the first multiplexer MU1 to the second latch La2 can be considered as a scan shift path in SRAM testing. The path from the first latch La11…La1N to the second multiplexer MU2 can be considered as a scan bypass path in SRAM testing.

[0025] exist Figure 5 In this embodiment, the M-bit signal MS includes the address signal, write enable signal, and memory enable signal of SRAM 103, and the N-bit signal NS is a data signal. In this case, the N-bit signal NS is received by the data terminal D of SRAM 103, while the M-bit signal MS is received by the address terminal ADDR, the write enable terminal WE, and the memory enable terminal ME of SRAM 103, respectively.

[0026] In one embodiment, the test system 500 may correspond to Figure 2 In this embodiment, the second multiplexer MU2 is not included. In this embodiment, the test system 500 outputs an N-bit signal NS and an M-bit signal MS to the SRAM 103 in normal mode, and outputs a scan output SO to the SRAM 103 in test mode. It can also receive test signals input from outside the test system 500 in external test mode. In this embodiment, the output of the SRAM 103 can be used as test signals for its subsequent components.

[0027] Compared to existing technologies, the aforementioned embodiments can save a considerable number of components. For example, if the test system uses a built-in scan chain mechanism, each first latch must be paired with a second latch, and each first latch must be paired with a multiplexer for mode switching. The architecture in the aforementioned embodiments can significantly reduce the number of latches and multiplexers, which not only greatly reduces the circuit area but also reduces the signal delay caused by these components.

[0028] Based on the foregoing embodiments, a testing method can be obtained. Figure 6 A flowchart illustrating a testing method according to an embodiment of the present invention is shown, which includes the following steps:

[0029] Step 601

[0030] The X-bit signals output by multiple first latches are compressed into Y-bit signals, where X and Y are positive integers and X is greater than Y.

[0031] Step 603

[0032] The Y-bit signal is received by at least one second latch to generate a scan output, wherein each of the first latch and the second latch forms a D-type flip-flop.

[0033] Step 605

[0034] The X-bit signal is output to the target electronic device in normal mode and the scan output is output to the target electronic device in test mode. The target electronic device can be a memory such as SRAM, but it can also be other types of electronic devices.

[0035] In one embodiment, as in the present invention Figure 4 As shown, the X-bit signal includes an M-bit signal and an N-bit signal. The M-bit signal includes an address signal, a write enable signal, and a memory enable signal, and the N-bit signal is a data signal, where M+N is greater than Y. Other detailed steps can be derived from the foregoing embodiments, and therefore will not be repeated here.

[0036] According to the foregoing embodiments, the circuit area and signal delay required for testing can be significantly reduced, thus improving the problems of existing testing systems.

[0037] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A test system, comprising: a plurality of first latches; an X-to-Y compressor coupled to the plurality of first latches for compressing X-bit signals outputted by the plurality of first latches into Y-bit signals, X and Y being positive integers and X being greater than Y; and at least one second latch coupled to the X-to-Y compressor for receiving the Y-bit signal to generate a scan output, wherein each of the first latches and the second latches forming a D-type flip-flop; wherein the test system outputs the X-bit signals in a normal mode and outputs the scan output in a test mode.

2. The test system of claim 1, wherein, Y is 1 and the number of the second latches is 1.

3. The test system of claim 1, wherein, The test system is used in a memory, and the X-bit signals include data signals, address signals, write enable signals or memory enable signals of the memory.

4. The test system of claim 1, wherein, The test system is used in a memory, wherein the X-bit signals include M-bit signals and N-bit signals, the M-bit signals include address signals, write enable signals and memory enable signals, and the N-bit signals are data signals, M+N being greater than Y.

5. The test system of claim 3 or 4, wherein, The memory is an SRAM.

6. The test system of claim 5, further comprising: a third latch coupled to a data output of the SRAM.

7. The test system of claim 1, further comprising: a fourth latch; and a first multiplexer including an output coupled to the second latch, a first input receiving the Y-bit signals and a second input receiving an output of the fourth latch.

8. The test system of claim 1, wherein, The test system is used in a memory, and further comprising: a second multiplexer including a first input receiving the X-bit signals and a second input receiving an output of the memory.

9. A test method, comprising: compressing X-bit signals outputted by a plurality of first latches into Y-bit signals, X and Y being positive integers and X being greater than Y; The Y-bit signal is received by at least one second latch to generate a scan output, wherein, each of the first latches and the second latches forming a D-type flip-flop; and outputting the X-bit signals to a target electronic device in a normal mode and outputting the scan output to the target electronic device in a test mode.

10. The test method of claim 9, wherein, The target electronic device is a memory, wherein the X-bit signals include M-bit signals and N-bit signals, the M-bit signals include address signals, write enable signals and memory enable signals, and the N-bit signals are data signals, M+N being greater than Y.

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