Code block transmission method, device and storage medium

Abstract

The present application discloses a code block transmission method, device and storage medium. The code block transmission method includes: determining the counting threshold of the counter for counting the clock pulse according to the period of the clock pulse, the bandwidth of the client and the code block interval of the code block transmitted by the clients with different bandwidths, and the counters corresponding to the clients with different bandwidths are different; when the count value of the nth counter reaches the counting threshold of the nth counter, the counting flag position corresponding to the nth counter in the register is set to a preset value, the value of n is less than or equal to N, and N is the number of clients; scanning the register; when the counting flag position corresponding to the mth counter in the register is scanned to be the preset value, receiving the code block sent by the client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter, the value of m is less than or equal to N. The present application can take into account both chip resource saving and feasibility, and meet the time interval requirements required by the code block transmission standard.

Description

Technical Field

[0001] The present application relates to the field of network communication technology, and in particular to a code block transmission method, device and storage medium. Background Art

[0002] Flexible Ethernet (FlexE) technology is developed based on Ethernet technology to meet the needs of high-speed transmission and flexible bandwidth configuration.

[0003] In flexible Ethernet, according to the relevant standards of OAM (Operation, Administration and Maintenance), the block intervals for different types of OAM blocks are different. For example, the block interval requirement for transmitting BAS blocks is to send and receive at intervals of 16K frames, or 32K, 64K, 128K, 256K, or 512K frames (K is 1024) under the bandwidth of the FlexE Client (Flexible Ethernet Client) to which it belongs. Other types of OAM frames are also based on this interval unit, or are sent and received in 1 second time units.

[0004] Due to the flexibility of the 5G granularity of supported bandwidth, the bandwidth of each FlexE Client may be different. Even if the code blocks are transmitted at the same code block interval, the time intervals for FlexE Clients with different bandwidths to transmit code blocks are different. If multiple timers are used to achieve the time interval required by the code block transmission standard for clients with different bandwidths, it will lead to a waste of chip resources. If one timer is used to achieve the time interval required by the code block transmission standard for clients with different bandwidths, it may be difficult to achieve. Summary of the invention

[0005] Embodiments of the present application provide a code block transmission method, device, and storage medium.

[0006] The technical solution of this application is implemented as follows:

[0007] In a first aspect, a code block transmission method is provided, the method comprising:

[0008] Determine a counting threshold for a counter to count the clock pulses according to a period of the clock pulse, a bandwidth of the client, and a code block interval of code blocks transmitted by the client with different bandwidths; wherein the counters corresponding to the clients with different bandwidths are different;

[0009] When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value; wherein the value of n is less than or equal to N, and N is the number of the clients;

[0010] scanning the register;

[0011] When the count flag bit corresponding to the mth counter in the register is scanned to be the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, where the value of m is less than or equal to N.

[0012] In the above technical solution, scanning the register includes:

[0013] The register is scanned within a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.

[0014] In the above technical solution, the counting threshold for the counter to count the clock pulses is determined according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting code blocks with different bandwidths, including:

[0015] Determine a time interval for transmitting the code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame within the code block interval;

[0016] determining a quotient between the time interval and the period of the clock pulse;

[0017] The integer part of the quotient is determined as the counting threshold of the nth counter.

[0018] In the above technical solution, the method further comprises:

[0019] When the quotient has a decimal part, record the decimal part of the quotient;

[0020] When the product of the decimal part and s is greater than or equal to 1, the maximum value of the current count of the nth counter is determined to be the counting threshold plus 1, where s is the counting round of the current count in which the nth counter continuously counts from 0 to the counting threshold.

[0021] In the above technical solution, the code blocks include: a first type of code blocks and a second type of code blocks, wherein the code block interval of the second type of code blocks is P times the code block interval of the first type of code blocks, and P is a positive integer greater than or equal to 2;

[0022] The counting threshold of the nth counter is determined according to the code block interval of the first type of code blocks;

[0023] When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value, including:

[0024] Whenever the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the first class code block of the nth counter in the register is set to the preset value; and / or,

[0025] When the count value of the nth counter reaches the count threshold of the nth counter for P consecutive times, the count flag position corresponding to the second type code block of the nth counter in the register is set to the preset value.

[0026] In the above technical solution, the code block also includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2;

[0027] When the count value of the nth counter reaches the count threshold of the nth counter, setting the count flag position corresponding to the nth counter in the register to a preset value also includes:

[0028] When the count value of the nth counter reaches the count threshold of the nth counter for q consecutive times, the count flag position corresponding to the third type code block of the nth counter in the register is set to the preset value.

[0029] In the above technical solution, the method further comprises:

[0030] If the code block sent by the client corresponding to the mth counter is not received for a preset number of consecutive times, a timeout alarm is generated; wherein the preset number of consecutive times is: the number of times the count value of the mth counter reaches the count threshold of the mth counter continuously.

[0031] In a second aspect, a code block transmission device is provided, the device comprising:

[0032] A determination module, configured to determine a counting threshold for a counter to count the clock pulses according to a period of the clock pulses, a bandwidth of the client, and a code block interval of code blocks transmitted by the client with different bandwidths; wherein the counters corresponding to the clients with different bandwidths are different;

[0033] A setting module, used for setting the counting flag position corresponding to the nth counter in the register to a preset value when the counting value of the nth counter reaches the counting threshold of the nth counter; wherein the value of n is less than or equal to N, and N is the number of the clients;

[0034] A scanning module, used for scanning the register;

[0035] A transmission module is used to receive a code block sent by a client corresponding to the mth counter or send the code block to the client corresponding to the mth counter when the count flag bit corresponding to the mth counter in the register is scanned to be the preset value, wherein the value of m is less than or equal to N.

[0036] According to a third aspect, an electronic device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the code block transmission method according to any one of the first aspects.

[0037] According to a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, wherein the computer program is configured to execute the code block transmission method described in any one of the first aspects when running.

[0038] In the technical solution provided by the present application, since the counting threshold of the counter for counting clock pulses is determined according to the period of the clock pulse, the bandwidth of the client and the code block interval of the code blocks transmitted by the clients with different bandwidths, the counters corresponding to the clients with different bandwidths are different. In this way, compared with using multiple timers to respectively realize the time interval required for the clients with different bandwidths to meet the code block transmission standard, the counters corresponding to the clients with different bandwidths in the present application share the same clock pulse for counting, which is equivalent to using only one timer to realize pulse counting for the clients with different bandwidths, which can greatly save chip resources. In addition, since there is no need to use the same main frequency / frequency division pulse signal as the lowest common divisor of different time intervals, there is no need to be limited by the pulse signal. The size of the number only needs to determine the counting threshold of the counter corresponding to the client with different bandwidths for counting the clock pulse, which is more feasible; in addition, when the count value of the nth counter reaches the counting threshold of the nth counter, the counting flag position corresponding to the nth counter in the register is set to a preset value, and the register is scanned. When the counting flag corresponding to the mth counter in the register is scanned to be the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, wherein the value of m is less than or equal to N. Therefore, while fully considering the chip resource saving and feasibility, the time accuracy of the code block transmission can be guaranteed to meet the time interval requirement required by the code block transmission standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1a A flowchart of a design using multiple timers;

[0040] Figure 1b A flow chart of a design using a timer;

[0041] Figure 2 A schematic diagram of a flow chart of a code block transmission method provided in an embodiment of the present application;

[0042] Figure 3 Another schematic diagram of a flow chart of a code block transmission method provided in an embodiment of the present application;

[0043] Figure 4 Another flowchart of the code block transmission method provided in the embodiment of the present application;

[0044] Figure 5a A schematic diagram of a framework of a two-stage timer in a code block transmission method provided in an embodiment of the present application;

[0045] Figure 5b Pseudo-code logic of the method for using the timing counter register provided in the embodiment of the present application;

[0046] Figure 5c A flowchart of a code block transmission method based on a two-stage timer provided in an embodiment of the present application;

[0047] Figure 5d A flowchart of a BAS timeout processing mechanism triggered by a timer provided in an embodiment of the present application;

[0048] Figure 5e A flowchart of a timeout count update processing mechanism in the receiving direction provided by an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the structure of a code block transmission device provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. In addition, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0052] It should be noted that, unless the context clearly requires otherwise, words such as “include”, “including” and similar words throughout the specification and claims should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is “including but not limited to”.

[0053] In addition, in the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "plurality" is two or more.

[0054] According to the relevant standards of Flexible Ethernet OAM, the time intervals for different types of OAM blocks are different. For the BAS block (Basic block), the function of this block is to periodically monitor the basic block of the FlexE Client (Flexible Ethernet Client). The block interval requirement for transmitting this block is 16K / 32K / 64K / 128K / 256K / 512Kblock (data frame), and the data frame uses 66bit / 64bit encoding, that is, the actual valid data of each frame is 8Byte. For the APS block (block used for protection switching), when a link failure is detected, three APS blocks need to be sent continuously with the same block interval as the BAS block. For other blocks, such as CV block (connectivity verification block), 1DM block (one-way delay block), 2DMM block (two-way delay measurement block), 2DMR (two-way delay response block), and CS block (client signal indication block), the time unit is 1 second, 10 seconds or 1 minute.

[0055] Due to the flexibility of the FlexE Client bandwidth of Flexible Ethernet, Flexible Ethernet defines the bandwidth of its FlexE Client as 5G as the minimum unit, which can be combined and the maximum can be supported by the chip, such as 400G or 800G. For example, it can support 25G, 50G, 105G, 195G, and other bandwidth combinations in 5G units. Therefore, when the code block intervals of FlexE Clients with different bandwidths are the same, the time intervals of their code blocks are different. For example, if 16k frames are used as the code block interval for transmitting BAS code blocks, the time intervals for transmitting BAS code blocks of FlexE Clients with 25G bandwidth and FlexE Clients with 50G bandwidth are different.

[0056] The general implementation method of the timer is: configure the frequency division according to the main frequency of the chip, take the main frequency as the smallest unit, update the counter, and trigger a certain operation process by configuring the threshold value reached by the counter, so as to realize the timing function. For example, assuming that the main frequency of the chip is 500M, if you want to configure a 1ms timer, you need to design a counter. Each time the main frequency is refreshed, the counter is incremented by 1. When the counter reaches 500M / 1000 / 1, that is, 500000, it means that the time has reached 1ms, and a certain operation will be performed at this time.

[0057] In view of the flexibility of 5G granularity of supported bandwidth and the requirements of OAM-related standards, there are generally two solutions from a design perspective to achieve code block transmission of FlexEClient with different bandwidths.

[0058] Option 1: If Figure 1a As shown, Figure 1a This is a flow chart of a design using multiple timers. Since the bandwidth of each FlexE Client may be different, there is no definite calculation relationship for the threshold configuration of the counter. It is necessary to design a timer for each FlexE Client, and the timer time can be set according to different bandwidths. Although this solves the timer problem, it requires the use of a large number of timers, which is a great waste of chip resources.

[0059] Option 2: If Figure 1b As shown, Figure 1bThe flowchart of the design scheme using a timer is shown in Figure 1. Using a timer, all time units of different bandwidths are generated from this timer. On a timer, different time intervals are achieved by configuring different timer counter accumulator registers and different thresholds. However, due to the diversity of FlexEClient bandwidth, if a FlexE Client needs to support 55G bandwidth, the time interval of 16K frames is calculated as: 64bit*16K / 55G=19065.018ns, and another FlexE Client needs to support 105G, then the time interval of 16K frames is calculated as 64bit*16K / 105G=9986.438ns. Using the same main frequency / frequency division pulse signal, that is, it is necessary to find the lowest common divisor of the time intervals of the two, so that different timer counters can be configured to achieve the purpose of using a timer. Moreover, with the bandwidth granularity of 5G, the minimum common divisor of the time interval of 16K frames of all bandwidths is likely to reach 1ns or less. Even if the chip main frequency can meet the pulse granularity of 1ns, the chip cannot complete the operations that need to be done after the timer reaches the threshold within 1ns, such as sending FlexE OAM code blocks. Therefore, this solution is not feasible.

[0060] In view of this, an embodiment of the present application provides a code block transmission method, which can ensure the time accuracy of code block transmission while fully considering chip resource conservation and feasibility, and meet the time interval requirements required by the code block transmission standard. The method can be executed by a code block transmission device, which can be implemented in software and / or hardware, and can be deployed in a switching chip supporting FlexE OAM, which can be an Application Specific Integrated Circuit (ASIC) chip, or a Field Programmable Gate Array (FPGA) chip, or NP, etc., which can be adjusted accordingly according to actual conditions.

[0061] See also Figure 2 As shown, an embodiment of the present application provides a code block transmission method, which may include:

[0062] S11. Determine a counting threshold for a counter to count clock pulses according to a period of a clock pulse, a bandwidth of a client, and a code block interval of code blocks transmitted by clients with different bandwidths; wherein different counters correspond to clients with different bandwidths.

[0063] The clock pulse may be a time pulse signal generated by dividing the main frequency generated by the switching chip. Each time a clock pulse is generated, the count of the started counter will increase by one. Here, the period of the clock pulse may be set according to actual needs. Preferably, the period of the clock pulse is set to 32ns. Here, the started counter may be a counter corresponding to a client that needs to perform code block transmission between the current device.

[0064] The client may be a flexible Ethernet client FlexE Client, and sends or receives OAM code blocks at the code block interval required by the OAM standard under its bandwidth. Here, there are multiple clients, and the bandwidths of the multiple clients may be partially the same or completely different.

[0065] The code block interval may be a specified number of data frames required by the code block transmission standard. For example, when the code block interval of the transmission code block is 16k data frames, it means that one code block is transmitted every 16k data frames, wherein the data frame adopts 66bit / 64bit encoding, and the actual valid data of each frame is 8Byte.

[0066] The counter used to count the clock pulses is a counting register, and the counter used to record the counting threshold of the clock pulses is a configuration register. More specifically, the first counting field of the counting register is used to record the current count value of the clock pulse, and the first configuration field of the configuration register is used to record the counting threshold of the clock pulse.

[0067] It can be understood that, under the same code block interval, the counting thresholds for counting clock pulses by the counters corresponding to different bandwidth clients are different.

[0068] S12. When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value; wherein the value of n is less than or equal to N, and N is the number of clients.

[0069] When the count value of the nth counter corresponding to the nth client reaches the count threshold of the nth counter, the count value of the nth counter is reset to zero, and the count flag position corresponding to the nth counter in the register is triggered to be a preset value. The count flag corresponding to the counter in the register uses different values ​​to indicate whether the count value of the counter reaches the count threshold.

[0070] In a specific implementation, the register may use a binary bit in a bitmap data structure as a count flag bit corresponding to the counter. Here, the bitmap data structure refers to a data structure using a field of a bitmap type, where each bit in the field represents a counter (or a client corresponding to the counter), and each bit uses 0 to indicate that the count value of the counter has not reached the count threshold, and uses 1 to indicate that the count value of the counter has reached the count threshold; or, uses 0 to indicate that the count value of the counter has reached the count threshold, and uses 1 to indicate that the count value of the counter has not reached the count threshold.

[0071] When the count value of a certain counter reaches the count threshold of the counter, the bit representing the counter in the register is set to a preset value indicating that the count threshold has been reached.

[0072] S13. Scan register.

[0073] In one embodiment, the registers may be scanned in a repetitive loop;

[0074] In another embodiment, specifically, the count flag bits corresponding to different counters in the register may be scanned according to the timing cycle of the timer, and each time a count flag bit is scanned, it is determined whether the value of the count flag bit is a preset value.

[0075] S14. When the count flag bit corresponding to the mth counter in the register is scanned to be a preset value, a code block sent by the client corresponding to the mth counter is received or a code block is sent to the client corresponding to the mth counter, where the value of m is less than or equal to N.

[0076] In one example, the code block transmission device is located in a switching chip as a receiving end. When the count flag bit corresponding to the mth counter in the register is scanned to be a preset value, it indicates that the time interval for receiving the code block sent by the client corresponding to the mth counter has arrived. At this time, the code block transmission device receives the code block sent by the client corresponding to the mth counter.

[0077] In another example, the code block transmission device is located in a switching chip serving as a transmitting end. When the count flag corresponding to the mth counter in the register is scanned to be a preset value, it indicates that the time interval for sending the code block to the client corresponding to the mth counter has arrived. At this time, the code block transmission device sends the code block to the client corresponding to the mth counter.

[0078] In the embodiment of the present application, when the code block is transmitted, since the counting threshold of the counter for counting the clock pulse is determined according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the code block transmitted by the clients with different bandwidths, the counters corresponding to the clients with different bandwidths are different. In this way, compared with using multiple timers to respectively realize the time interval required for the clients with different bandwidths to meet the code block transmission standard, the counters corresponding to the clients with different bandwidths in the present application share the same clock pulse for counting, which is equivalent to using only one timer to realize pulse counting for the clients with different bandwidths, which can greatly save chip resources. In addition, since there is no need to use the same main frequency / frequency division pulse signal as the lowest common divisor of different time intervals, there is no need to be limited by the pulse signal. The size of the number only needs to determine the counting threshold of the counter corresponding to the client with different bandwidths for counting the clock pulse, which is more feasible; in addition, when the count value of the nth counter reaches the counting threshold of the nth counter, the counting flag position corresponding to the nth counter in the register is set to a preset value, and the register is scanned. When the counting flag corresponding to the mth counter in the register is scanned to be the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, wherein the value of m is less than or equal to N. Therefore, while fully considering the chip resource saving and feasibility, the time accuracy of the code block transmission can be guaranteed to meet the time interval requirement required by the code block transmission standard.

[0079] In one embodiment, Figure 3 As shown, in the above step S11, determining the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the code blocks transmitted by the client with different bandwidths may include:

[0080] S111 . Determine a time interval for transmitting code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame within the code block interval.

[0081] The bandwidth of the client is negatively correlated with the time interval for the client to transmit code blocks.

[0082] Specifically, the product of the code block interval and the number of bits included in the code block is determined, and the quotient of the product and the bandwidth of the nth client is used as the time interval for the nth client to transmit the code block.

[0083] For example, taking the BAS code block as an example, assuming that the bandwidth of the nth client is 55G, the code block interval for transmitting the BAS code block is 16K frames, and the number of bits contained in each frame is 64 bits, then the time interval for the nth client to transmit the code block is calculated as: 64bit*16K / 55G=19065.018ns.

[0084] S112. Determine the quotient between the time interval and the period of the clock pulse.

[0085] Here, the quotient between the time interval and the period of the clock pulse can be understood as the number of pulses of the clock pulse within the time interval, and the number of pulses can be a non-integer value.

[0086] S113. Determine the integer part of the quotient as the counting threshold of the nth counter.

[0087] Specifically, the configuration register of the nth counter stores a first configuration field and a second configuration field. The first configuration field is used to configure the counting threshold of the nth counter, that is, the integer part of the quotient between the time interval of the nth client transmission code block and the period of the clock pulse; the second configuration field is used to configure the configuration value of the fractional counting part of the nth counter.

[0088] In one embodiment, Figure 4 As shown, based on Figure 3 , the method may further include:

[0089] S114. When the quotient has a decimal part, record the decimal part of the quotient.

[0090] Specifically, for the time interval of the nth client transmitting a code block, the fractional part of the quotient between the time interval and the period of the clock pulse can be used as the configuration value of the fractional count part of the nth counter and configured in the second configuration field in the configuration register.

[0091] For example, assuming that the bandwidth of the nth client is 55G, the code block is transmitted with a code block interval of 16K data frame, and the transmission time interval is 19065.018ns. For a time pulse with a pulse period of 32ns, the required number of pulses is: 19065.018 / 32=595.782. In order to achieve a more precise time interval, in addition to using the integer part 595 of the pulse number as the configuration value of the counting threshold of the nth counter in the first configuration field in the configuration register, the decimal part 0.782 of the pulse number can also be used as the configuration value of the decimal counting part of the nth counter in the second configuration field in the configuration register.

[0092] S115. When the product of the decimal part and s is greater than or equal to 1, determine that the maximum value of the current count of the nth counter is the counting threshold plus 1, where s is the counting round of the current count in which the nth counter continuously counts from 0 to the counting threshold.

[0093] Specifically, when the product of the decimal part and s is greater than or equal to 1, the value of the product is recorded in the second count field of the count register in the nth counter, and the first count field of the count register in the nth counter is used to record the current count value of the clock pulse of the nth counter.

[0094] In this embodiment, a product operation is performed on the counting round of the current count in which the nth counter continuously counts from 0 to the counting threshold, and the decimal part of the number of pulses of the clock pulse within the time interval of the nth client transmitting the code block is multiplied, and when the product operation result is greater than or equal to 1, the maximum value of the current count of the nth counter is determined to be the counting threshold plus 1. This not only enables the counting processing of the decimal part to be approximately averaged in multiple pulse cycles, but also helps to further improve the time accuracy of code block transmission.

[0095] In one embodiment, the code blocks include: a first type of code blocks and a second type of code blocks, wherein the code block interval of the second type of code blocks is P times the code block interval of the first type of code blocks, and P is a positive integer greater than or equal to 2; the counting threshold of the nth counter is: determined according to the code block interval of the first type of code blocks.

[0096] Here, for the convenience of description, the code block interval of the first type of code block can be recorded as the first code block interval, and the code block interval of the second type of code block can be recorded as the second code block interval. Here, the first code block interval can be a 16k data frame, and the second code block interval can be a 32k data frame, a 64K data frame, a 128K data frame, a 256K data frame, or a 512K data frame, but the embodiments of the present application are not limited thereto.

[0097] The first code block interval may be a minimum code block interval supported by the corresponding client, and the second code block interval may be P times the minimum code block interval.

[0098] The counting threshold of the nth counter is determined according to the code block interval of the first type of code blocks, including:

[0099] A counting threshold for the nth counter to count the clock pulses is determined according to the period of the clock pulse, the bandwidth of the nth client, and the code block interval of the first type of code blocks.

[0100] Specifically, the implementation process of this step can refer to steps S111 to S113 in the above embodiment, which will not be repeated here.

[0101] In the above step S12, when the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value, which may include at least one of step S121 and step S122:

[0102] S121. Whenever the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the first type of code block of the nth counter in the register is set to a preset value.

[0103] In this embodiment, since the counting threshold of the nth counter is determined according to the code block interval of the first type of code block, when the count value of the nth counter reaches the counting threshold of the nth counter, it indicates that the nth client corresponding to the nth counter has reached the code block interval for transmitting the first type of code block. By setting the counting mark position corresponding to the first type of code block of the nth counter in the register to a preset value, in this way, during the process of scanning the register, the counting mark position corresponding to the first type of code block of the nth counter in the register will be scanned as the preset value, so as to receive the first type of code block sent by the nth client or send the first type of code block to the nth client, thereby enabling clients with different bandwidths to transmit the first type of code block according to the code block transmission standard and ensuring the time accuracy of code block transmission.

[0104] S122. When the count value of the nth counter reaches the count threshold of the nth counter for P consecutive times, the count flag position corresponding to the second type code block of the nth counter in the register is set to a preset value.

[0105] In this embodiment, since the code block interval of the second type of code block is P times the code block interval of the first type of code block, and since the counting threshold of the nth counter is determined according to the code block interval of the first type of code block, when the count value of the nth counter reaches the counting threshold of the nth counter for P consecutive times, it indicates that the nth client corresponding to the nth counter has reached the code block interval for transmitting the second type of code block, and by setting the counting mark position corresponding to the second type of code block of the nth counter in the register to a preset value, in the process of scanning the register, the counting mark position corresponding to the second type of code block of the nth counter in the register will be scanned as the preset value, so as to receive the second type of code block sent by the nth client or send the second type of code block to the nth client, so that clients with different bandwidths can transmit the second type of code block according to the code block transmission standard and can ensure the time accuracy of code block transmission. In one embodiment, the code block also includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2.

[0106] Here, the time interval may be in seconds, and the code block interval may be in the number of data frames. As an example, the third type of code block may be a CV code block transmitted in seconds or minutes, and the first type of code block may be a BAS code block, APS code block, etc. transmitted in 16k data frames as code block intervals, but the embodiments of the present application are not limited thereto.

[0107] The time interval for the nth client to transmit the first type of code block can be determined in the following manner:

[0108] The time interval for the nth client to transmit the first type of code block is determined according to the bandwidth of the nth client, the code block interval for the nth client to transmit the first type of code block, and the number of bits contained in each frame code block in the code block interval.

[0109] In the above step S12, when the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value, and may also include:

[0110] S123. When the count value of the nth counter reaches the count threshold of the nth counter for q consecutive times, the count flag position corresponding to the third type code block of the nth counter in the register is set to a preset value.

[0111] In this embodiment, since the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, when the count value of the nth counter reaches the count threshold of the nth counter for q consecutive times, it indicates that the nth client has reached the time interval for transmitting the third type of code block. By setting the count mark position corresponding to the third type of code block of the nth counter in the register to a preset value, in this way, during the process of scanning the register, the count mark position corresponding to the third type of code block of the nth counter in the register will be scanned as the preset value, so as to receive the third type of code block sent by the nth client or send the third type of code block to the nth client, thereby enabling clients with different bandwidths to transmit the third type of code block according to the code block transmission standard and ensuring the time accuracy of the code block transmission.

[0112] In one embodiment, in the above step S13, scanning the register may include:

[0113] The register is scanned within a timing period of the timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.

[0114] The timer may be a timer to which the register belongs, that is, a second-level timer.

[0115] Among them, the timing period of the timer is an adjustable value, which can be adjusted within the range allowed by the chip design, and the register can be scanned with a smaller timing period as much as possible. It can be understood that the smaller the timing period of the timer, the higher the accuracy of the code block transmission time. Preferably, the timing period of the timer is set to 8ns.

[0116] In one embodiment, the method may further include:

[0117] If the code block sent by the client corresponding to the mth counter is not received for a preset number of consecutive times, a timeout alarm is generated; wherein the preset number of consecutive times is: the number of times the count value of the mth counter reaches the count threshold of the mth counter consecutively.

[0118] The preset number of consecutive times may be set according to actual applications, for example, set to 3, that is, if the code block sent by the client corresponding to the mth counter is not received for three consecutive times, a timeout alarm is generated.

[0119] It should be noted that, when the number of consecutive times that the code block sent by the client corresponding to the mth counter is not received is lower than the preset number of consecutive times, no timeout alarm is generated.

[0120] Next, combine Figure 5a to Figure 5e The code block transmission method provided in an embodiment of the present application is described.

[0121] Taking a FlexE Client that supports a total of 800G as an example, when 5G bandwidth is the minimum bandwidth granularity, there are a maximum of 800 / 5(G) = 160 FlexE Clients. The period of the clock pulse signal divided by the chip main frequency is set to 32ns, and 16K data frames are used as the code block interval for each FlexE Client transmission code block.

[0122] like Figure 5a In the first-level timer, a counter is set for each FlexE Client. Each counter includes a counting register and a configuration register. The counting register is DsFlexEOamTxScanCounter. The counting register stores two fields: counter and counterFrac. Counter is used to store the integer part of the current timer count, and counterFrac is used to store the decimal part of the current timer count. The configuration register is DsFlexEOamTxScanCfg. The configuration register stores two fields: counterThrd and counterFracCfg. CounterThrd is used to configure the counting threshold for the 16K data frame of the FlexE Client to which it belongs, and counterFracCfg is used to configure the configuration value of the decimal part of each pulse update.

[0123] In the second-level timer, the trigger register is set to FlexEOamTxScanBitmap, which stores a field called updateEnBitmap. This field can be a bitmap type, that is, each bit in it represents a FlexE Client. When it is 1, it means that the 16K frame time interval of the current FlexE Client has been reached.

[0124] Figure 5b The following is the pseudo code logic for the usage of the timing counter register. Considering that the 32ns time pulse is a fixed pulse, it is generally not divisible for different bandwidths. Taking 55G bandwidth as an example, according to the calculation in the previous embodiment, the time interval for transmitting the code block with 16K data frame as the code block interval is 19065.018ns. For a 32ns time pulse, 19065.018 / 32=595.782 is required. To achieve the precise time interval, DsFlexEOamTxScanCfg.countertThrd can be configured to 595, and DsFlexEOamTxScanCfg.counterFracCfg is approximately 0.C8H. According to Figure 5b The pseudo-code logic can achieve the required time interval. In particular, considering that dedicated switching chips generally do not support fractional operations, the pseudo-code logic here is used to increase the fractional count part each time counterThrd is reached. When the fractional part carries, the threshold that meets the condition next time needs to be increased by 1, that is, DsFlexEOamTxScanCounter.counterFrac[8] is 1, thereby approximately averaging the fractional count processing in multiple cycles.

[0125] When the count value of the nth counter reaches the count threshold of the nth counter, the bit of the FlexE Client corresponding to the nth counter in FlexEOamTxScanBitmap.updateEnBitmap is set to 1, indicating that the FlexE Client corresponding to the nth counter has reached the time trigger condition of the 16K frame, and the second-level timer timing processing can be performed to trigger subsequent operations.

[0126] It should be noted that the DsFlexEOamTxScanCounter and DsFlexEOamTxScanCfg registers need to save the relevant counter and configuration for each FlexE Client so that FlexE Clients with different bandwidth rates can have different time interval configurations.

[0127] The second-level timer can use an 8ns fixed polling timer to process the subsequent processing of the FlexE Client corresponding to a bit in FlexEOamTxScanBitmap.updateEnBitmap being 1 every 8ns. Here, 8ns is an adjustable value that can be adjusted within the range allowed by the chip design, and the subsequent processing can be performed with a smaller polling time as much as possible.

[0128] like Figure 5c , based on the timing processing of the first-level timer and the second-level timer, when the processing logic reaches the functional processing module, it means that the time interval of the 16K data frame corresponding to the bandwidth of the current FlexE Client has been reached. Other code block intervals can be obtained by multiplying the code block interval of the 16K data frame. For example, the transmission of BAS code blocks needs to support code block intervals of 16K / 32K / 64K / 128K / 256K / 512K.

[0129] Furthermore, a counter register called BasPeriodCounter can be added to the BAS Period Counter module of the functional processing module to configure multiples of 16K. For example, if the current FlexE Client needs to be configured with a code block interval of 64K frames, the count value is configured to 4. When BasPeriodCounter is not 0, no processing is performed, and the next round of 16K frame code block interval trigger is waited; when BasPeriodCounter is reduced to 0, the sending of the BAS frame is triggered, and BasPeriodCounter is set to the initial value 4, waiting for the next round of 16K frame code block interval trigger.

[0130] Furthermore, for other frames that need to be sent at a rate of seconds, the 16K frame time interval corresponding to the current FlexEClient bandwidth calculated previously is calculated to a multiple of 1 second. For example, taking 55G bandwidth as an example, the time interval corresponding to 16K frames is 19065.018ns, and the multiple of 1 second can be configured as 52452. Under the premise of allowing a certain error, decimal processing can be omitted. Here, OneSecPeriodCounter can be configured as 52452. The processing flow is similar to BasPeriodCounter. When OneSecPeriodCounter is reduced to 0, it means that the 1-second time interval is triggered.

[0131] Furthermore, similar processing is performed for different OAM frames that require time intervals in seconds. Here, CV code blocks are used as an example. If the CV code block generation rate needs to be set to 1 second, then the initial value of CVPeriodCounter is configured to 1. Similarly, if it needs to be set to 10 seconds, then the initial value of CVPeriodCounter is configured to 10. If it needs to be set to 1 minute, then it is set to 60. Similar logic is used later. When CVPeriodCounter is 0, the sending of CV frames is triggered, and CVPeriodCounter is restored to the initial value. Other second-level OAM frames are processed using similar logic.

[0132] Figure 5d A schematic diagram of a BAS timeout processing mechanism triggered by a timer provided in an embodiment of the present application, Figure 5e This is a flowchart of the timeout count update processing mechanism in the receiving direction. Figure 5d As shown, at a 16K frame time interval, the BasExpiredCount minus 1 operation is triggered. BasExpiredCount is used to configure the preset number of consecutive times for timeout alarms. When BasExpiredCount is reduced to 0, it is considered that a timeout has occurred and an alarm is triggered. Figure 5e As shown, in the receiving direction, when a BAS is received, BasExpiredCount will be updated to the pre-configured preset consecutive number of times. For example, if it is necessary to consider that a BAS is not received for three consecutive 16K frame intervals as a timeout, then the pre-configured preset consecutive number of times is configured to 3. The timeout alarm mechanism can be implemented by the timer regular decrement and the receiving direction refresh processing.

[0133] In summary, this application uses a two-level timer, and only two timers are required. Through the two-level timer cascade, while ensuring the accuracy of the transmission time of the FlexE OAM frame, the resource saving and feasibility of the chip design are fully considered to meet the time interval requirements required by the standard. At the same time, based on the two-level timer, the time interval processing of different FlexE OAM frame types can be carried out, and a set of processing procedures can be used to support various time intervals required by the standard, which has strong scalability.

[0134] It should be noted that although this application is for the two-stage timer-based code block transmission method brought about by the flexible bandwidth of FlexE OAM, this idea can be used to process similar two-stage timer-based code block transmission requirements at the chip level, and is not limited to the single scenario of FlexE OAM.

[0135] like Figure 6 As shown, an embodiment of the present application provides a code block transmission device, which may include:

[0136] The determination module 601 is used to determine a counting threshold for a counter to count clock pulses according to a period of the clock pulse, a bandwidth of the client, and a code block interval of code blocks transmitted by clients with different bandwidths; wherein different counters correspond to clients with different bandwidths;

[0137] A setting module 602 is used to set the count flag position corresponding to the nth counter in the register to a preset value when the count value of the nth counter reaches the count threshold of the nth counter; wherein the value of n is less than or equal to N, and N is the number of clients;

[0138] Scanning module 603, used for scanning registers;

[0139] The transmission module 604 is used to receive the code block sent by the client corresponding to the mth counter or send the code block to the client corresponding to the mth counter when the count flag corresponding to the mth counter in the register is scanned to be a preset value, where the value of m is less than or equal to N.

[0140] In one embodiment, the scanning module is specifically used for:

[0141] The register is scanned within a timing period of the timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.

[0142] In one embodiment, the determination module is specifically used to:

[0143] Determine the time interval for transmitting code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame within the code block interval;

[0144] determining a quotient between the time interval and the period of the clock pulse;

[0145] The integer part of the quotient is determined as the counting threshold of the nth counter.

[0146] In one embodiment, the determination module is further configured to:

[0147] When the quotient has a decimal part, record the decimal part of the quotient;

[0148] When the product of the decimal part and s is greater than or equal to 1, the maximum value of the current count of the nth counter is determined to be the counting threshold plus 1, where s is the counting round of the current count in which the nth counter continuously counts from 0 to the counting threshold.

[0149] In one embodiment, the code blocks include: a first type of code blocks and a second type of code blocks, wherein the code block interval of the second type of code blocks is P times the code block interval of the first type of code blocks, and P is a positive integer greater than or equal to 2; the counting threshold of the nth counter is: determined according to the code block interval of the first type of code blocks;

[0150] The setup module includes:

[0151] A first setting unit, configured to set a count flag position corresponding to the first type of code block of the nth counter in the register to a preset value whenever the count value of the nth counter reaches a count threshold of the nth counter;

[0152] The second setting unit is used to set the counting flag position corresponding to the second type code block of the nth counter in the register to a preset value when the counting value of the nth counter reaches the counting threshold of the nth counter for P consecutive times.

[0153] In one embodiment, the code block further includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2;

[0154] The setup module also includes:

[0155] The third setting unit is used to set the counting flag position corresponding to the third type code block of the nth counter in the register to a preset value when the counting value of the nth counter reaches the counting threshold of the nth counter for q consecutive times.

[0156] In one embodiment, the apparatus further comprises:

[0157] The alarm module is used to generate a timeout alarm if the code block sent by the client corresponding to the mth counter is not received for a preset number of consecutive times; wherein the preset number of consecutive times is: the number of times the count value of the mth counter continuously reaches the count threshold of the mth counter.

[0158] It should be noted that: when the code block transmission device provided in the above embodiment executes the code block transmission method, only the division of the above program modules is used as an example. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the code block transmission device provided in the above embodiment and the code block transmission method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0159] An embodiment of the present application also provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: when the processor executes the computer program, the steps of the code block transmission method described in any one of the embodiments of the present application are implemented.

[0160] Figure 7 A hardware structure diagram of an electronic device according to an embodiment of the present application is given. Figure 7 The electronic device 700 shown includes: at least one processor 701, a memory 702, and at least one network interface 703. The various components in the electronic device 700 are coupled together via a bus system 704. It is understood that the bus system 704 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 704 is not described in detail. Figure 7 Various buses are labeled as bus system 704 .

[0161] It can be understood that the memory 702 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories.

[0162] The memory 702 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device 700. Examples of such data include: any computer program for operating on the electronic device 700, such as an executable program, and the program implementing the method of the embodiment of the present application may be included in the executable program.

[0163] An embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the code block transmission method described in any one of the embodiments of the present application are implemented.

[0164] It should be noted that the storage medium of the embodiment of the present application can be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAM bus random access memory (DRRAM, Direct Rambus Random Access Memory).The storage media described in the embodiments of the present application are intended to include, but are not limited to, these and any other suitable types of memory.

[0165] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0166] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0167] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0168] A person skilled in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, etc. Various media that can store program codes.

[0169] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for an electronic device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, disks, or optical disks.

[0170] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0171] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0172] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A code block transmission method, characterized in that: The method comprises: Determine a counting threshold for a counter to count the clock pulses according to a period of the clock pulse, a bandwidth of the client, and a code block interval of code blocks transmitted by the client with different bandwidths; wherein the counters corresponding to the clients with different bandwidths are different; When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value; wherein the value of n is less than or equal to N, and N is the number of the clients; scanning the register; When the count flag bit corresponding to the mth counter in the register is scanned to be the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, where the value of m is less than or equal to N.

2. The method according to claim 1, characterized in that The scanning of the register comprises: The register is scanned within a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.

3. The method according to claim 1, characterized in that The determining, according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting code blocks with different bandwidths, a counting threshold for the counter to count the clock pulse comprises: Determine a time interval for transmitting the code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame within the code block interval; determining a quotient between the time interval and the period of the clock pulse; The integer part of the quotient is determined as the counting threshold of the nth counter.

4. The method according to claim 3, characterized in that The method further comprises: When the quotient has a decimal part, record the decimal part of the quotient; When the product of the decimal part and s is greater than or equal to 1, the maximum value of the current count of the nth counter is determined to be the counting threshold plus 1, where s is the counting round of the current count in which the nth counter continuously counts from 0 to the counting threshold.

5. The method according to any one of claims 1 to 4, characterized in that: The code blocks include: a first type of code blocks and a second type of code blocks, wherein the code block interval of the second type of code blocks is P times the code block interval of the first type of code blocks, and P is a positive integer greater than or equal to 2; The counting threshold of the nth counter is determined according to the code block interval of the first type of code blocks; When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value, including: Whenever the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the first class code block of the nth counter in the register is set to the preset value; and / or, When the count value of the nth counter reaches the count threshold of the nth counter for P consecutive times, the count flag position corresponding to the second type code block of the nth counter in the register is set to the preset value.

6. The method according to claim 5, characterized in that The code block also includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2; When the count value of the nth counter reaches the count threshold of the nth counter, the count flag position corresponding to the nth counter in the register is set to a preset value, and further includes: When the count value of the nth counter reaches the count threshold of the nth counter for q consecutive times, the count flag position corresponding to the third type code block of the nth counter in the register is set to the preset value.

7. The method according to claim 1, characterized in that The method further comprises: If the code block sent by the client corresponding to the mth counter is not received for a preset number of consecutive times, a timeout alarm is generated; wherein the preset number of consecutive times is: the number of times the count value of the mth counter reaches the count threshold of the mth counter continuously.

8. A code block transmission device, characterized in that: The device comprises: A determination module, configured to determine a counting threshold for a counter to count the clock pulses according to a period of the clock pulses, a bandwidth of the client, and a code block interval of code blocks transmitted by the client with different bandwidths; wherein the counters corresponding to the clients with different bandwidths are different; A setting module, used for setting the counting flag position corresponding to the nth counter in the register to a preset value when the counting value of the nth counter reaches the counting threshold of the nth counter; wherein the value of n is less than or equal to N, and N is the number of the clients; A scanning module, used for scanning the register; A transmission module is used to receive a code block sent by a client corresponding to the mth counter or send the code block to the client corresponding to the mth counter when the count flag bit corresponding to the mth counter in the register is scanned to be the preset value, wherein the value of m is less than or equal to N.

9. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to execute the code block transmission method described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the code block transmission method described in any one of claims 1 to 7 when running.

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