Power module controller and electronic equipment

Abstract

The present invention provides a power module controller and electronic equipment, wherein the power module controller includes a microcontroller module, a logic processing module, a driver module and a peripheral power management module. In the present invention, two simple control chips, the microcontroller module and the peripheral power management module, and pure integrated circuit products of the logic processing module and the driver module are combined to form a simple and efficient power module safety drive control technical solution, which can realize pulse width modulation control in normal conditions, and make the driver module and the corresponding power module enter a safe state in case of failure, thereby improving the safety and reliability of the power control product; at the same time, the two-stage control chip does not involve complex calculation processing, only a simple control chip is needed, and the design of the logic processing module only requires logic components and a few peripheral electronic components to be realized, and its corresponding structure is simple and low in cost, and its switching control speed is fast based on the processing switching of electronic components, and its stability and reliability are strong.

Description

Technical Field

[0001] The present invention relates to the field of electronic control technology, and in particular to a power module controller and electronic equipment. Background Art

[0002] With the development of new energy vehicles, the demand for core components is not only limited to the realization of functions, but also focuses on the safety of functions.

[0003] The functional safety system of the motor controller can be simply summarized as four modules: peripheral power management module, microcontroller module, logic processing module and driver module. The logic processing module is located between the microcontroller module and the driver module, and is mainly responsible for filtering and transmitting safety signals. However, the logic processing module is not just a simple signal transmission module, but should also have signal stability protection and support functional safety strategy execution. Therefore, based on the functional safety development of the motor controller, it is necessary to design a logic circuit that meets functional safety.

[0004] In view of this technical problem, the solutions of the prior art are as follows: In the prior art one (107910852B), a logic gate circuit connected to a driving circuit is configured, but the high side and the low side in the logic gate circuit are completely independent of each other, and there will be a conflict in driving the high side and the low side at the same time, and the logic gate circuit involves a relay, which enters a safe state slowly and has low reliability; In the prior art two (CN 212114770 U), an ASC signal transmission circuit is designed, and a digital isolator is connected only to the first ASC signal transmission path, and a multi-stage amplifier circuit controlled by a current source is connected to the other two ASC signal transmission paths, and the current source control end of the multi-stage amplifier circuit is connected to the output end of the digital isolator, which requires the use of more digital isolators and transistors, and has a high corresponding cost and a complex structure.

[0005] Therefore, there is an urgent need for a simple and efficient logic circuit technology solution for driving power modules. Summary of the invention

[0006] In view of the shortcomings of the prior art mentioned above, the present invention provides a logic control driving technology solution for a power module, which combines the structural design of a simple control chip and a logic circuit. On the basis of the control of the control chip, the pulse width modulation control and safety shutdown of the power module and other functional switching are realized through the logic processing of the logic circuit, thereby improving the safety and reliability of the power control product.

[0007] To achieve the above-mentioned purpose and other related purposes, the technical solution provided by the present invention is as follows.

[0008] A power module controller, comprising:

[0009] Microcontroller module;

[0010] A logic processing module, electrically connected to the microcontroller module;

[0011] A driving module, electrically connected to the logic processing module, and used to drive the power module;

[0012] A peripheral power management module is electrically connected to the logic processing module, is in communication connection with the microcontrol module, and provides operating voltage for the microcontrol module, the logic processing module and the driving module;

[0013] Among them, the microcontrol module outputs a first pulse width modulation signal, a first enable signal, a first high-side safety signal and a first low-side safety signal, the peripheral power management module outputs a power management signal, the logic processing module receives the first pulse width modulation signal, the first enable signal, the first high-side safety signal, the first low-side safety signal and the power management signal and performs logic processing to obtain and output a second pulse width modulation signal, a second enable signal, a second high-side safety signal and a second low-side safety signal to the driving module, so that the driving module enters a pulse width modulation control state or a safe state.

[0014] Optionally, the microcontrol module receives a drive control instruction from a host computer and a detection feedback signal from a detection module, and regulates the states of the first pulse width modulation signal, the first enable signal, the first high-side safety signal, and the first low-side safety signal according to the drive control instruction or the detection feedback signal; the peripheral power management module receives the detection feedback signal from the detection module and the feedback signal from the microcontrol module, and regulates the state of the power management signal according to the detection feedback signal and the feedback signal; combined with the logic processing of the logic processing module, the drive module enters a pulse width modulation control state or a safe state.

[0015] Optionally, the logic processing module includes a first logic processing unit, and the first logic processing unit performs an AND operation on the first pulse width modulation signal and the first enable signal to obtain and output the second pulse width modulation signal to the driving module.

[0016] Optionally, the first logic processing unit includes a two-input logic AND gate, a first input terminal of the logic AND gate is connected to the first pulse width modulation signal, a second input terminal of the logic AND gate is connected to the first enable signal, and an output terminal of the logic AND gate outputs the second pulse width modulation signal.

[0017] Optionally, the logic processing module includes a second logic processing unit, and the second logic processing unit includes a first logic processing sub-unit, a second logic processing sub-unit and a third logic processing sub-unit; the first logic processing sub-unit performs an AND operation on the first high-side safety signal, the first low-side safety signal and the power management signal to obtain and output a second high-side safety signal to the driving module; the second logic processing sub-unit performs an AND operation on the first enable signal and the power management signal to obtain and output a second enable signal to the driving module; the third logic processing sub-unit performs an AND-NOT operation on the first low-side safety signal and the power management signal to obtain and output a second low-side safety signal to the driving module.

[0018] Optionally, the first logic processing subunit includes two two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the first high-side safety signal, the second input terminal of the first logic AND gate is connected to the power management signal, the output terminal of the first logic AND gate is connected to the first input terminal of the second logic AND gate, the second input terminal of the second logic AND gate is connected to the first low-side safety signal, and the output terminal of the second logic AND gate outputs the second high-side safety signal.

[0019] Optionally, the first logic processing subunit includes a three-input logic AND gate, a first input terminal of the logic AND gate is connected to the first high-side safety signal, a second input terminal of the logic AND gate is connected to the first low-side safety signal, a third input terminal of the logic AND gate is connected to the power management signal, and an output terminal of the logic AND gate outputs the second high-side safety signal.

[0020] Optionally, the first logic processing subunit includes four two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the first enable signal, the second input terminal of the first logic AND gate is connected to the first high-side safety signal, the output terminal of the first logic AND gate is connected to the second input terminal of the second logic AND gate, the first input terminal of the second logic AND gate is connected to the first low-side safety signal, the output terminal of the second logic AND gate outputs the second high-side safety signal, the first input terminal of the third logic AND gate is connected to the first high-side safety signal, the second input terminal of the third logic AND gate is connected to the first enable signal, the output terminal of the third logic AND gate is connected to the first input terminal of the fourth logic AND gate, the second input terminal of the fourth logic AND gate is connected to the first low-side safety signal, and the output terminal of the fourth logic AND gate outputs the second high-side safety signal.

[0021] Optionally, the second logic processing subunit includes a two-input logic AND gate, a first input terminal of the logic AND gate is connected to the first enable signal, a second input terminal of the logic AND gate is connected to the power management signal, and an output terminal of the logic AND gate outputs the second enable signal.

[0022] Optionally, the second logic processing subunit includes two two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the power management signal, the second input terminal of the first logic AND gate is connected to the first enable signal, the output terminal of the first logic AND gate outputs the second enable signal, the first input terminal of the second logic AND gate is connected to the first enable signal, the second input terminal of the second logic AND gate is connected to the power management signal, and the output terminal of the second logic AND gate outputs the second enable signal.

[0023] Optionally, the third logic processing subunit includes a two-input logic NAND gate, a first input terminal of the logic NAND gate is connected to the first low-side safety signal, a second input terminal of the logic NAND gate is connected to the power management signal, and an output terminal of the logic NAND gate outputs the second low-side safety signal.

[0024] Optionally, the third logic processing sub-unit includes two two-input logic NAND gates, the first input terminal of the first logic NAND gate is connected to the power management signal, the second input terminal of the first logic NAND gate is connected to the first low-side safety signal, the output terminal of the first logic NAND gate outputs the second low-side safety signal, the first input terminal of the second logic NAND gate is connected to the first low-side safety signal, the second input terminal of the second logic NAND gate is connected to the power management signal, and the output terminal of the second logic NAND gate outputs the second low-side safety signal.

[0025] An electronic device comprises a power module and any one of the power module controllers described above, wherein the power module is electrically connected to the power module controller, and the power module is safely driven and controlled by the power module controller.

[0026] The beneficial effects of the present invention are as follows: a power module controller is designed based on a microcontroller module, a logic processing module, a drive module and a peripheral power management module, and a power module drive control technical solution with multiple safety shutdown paths is formed by combining two simple control chips, the microcontroller module and the peripheral power management module, and pure integrated circuit products of the logic processing module and the drive module. The pulse width modulation control can be realized under normal conditions, and the drive module and the corresponding power module can be put into a safe state in case of a fault, thereby improving the safety and reliability of the power control product; at the same time, only a simple control chip and a few logic electronic components are needed, and the corresponding cost is low, the switching control speed is fast, and the stability and reliability are strong.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0029] Figure 1 is a schematic structural diagram of a power module controller shown in an exemplary embodiment of the present invention;

[0030] Figure 2 An exemplary embodiment of the present invention is shown Figure 1 A circuit structure diagram of the first logic processing unit 21;

[0031] Figure 3 An exemplary embodiment of the present invention is shown Figure 1 A circuit structure diagram of the second logic processing unit 22;

[0032] Figure 4 An exemplary embodiment of the present invention is shown Figure 1 A circuit structure diagram of the second logic processing unit 22;

[0033] Figure 5 An exemplary embodiment of the present invention is shown Figure 1 A circuit structure diagram of the second logic processing unit 22;

[0034] Figure 6 An exemplary embodiment of the present invention is shown Figure 5 A complete circuit diagram of the second logic processing word unit 222. DETAILED DESCRIPTION

[0035] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0038] As described in the background technology, the inventors have found that the safety shutdown control of power modules in the prior art requires the use of independent complex control chips or electrical control devices such as relays, which have relatively high corresponding costs. The switching control speed of the electrical control devices is slow, which may cause the power module to fail to enter the safe state in time and cause uncontrollable hazards. In addition, the stability and reliability of the electrical control devices are insufficient, which may cause the power module to be unable to enter the safe state. Therefore, the cost of the safety shutdown control technical solution for power modules in the prior art is relatively high, and there are still many deficiencies in safety and reliability.

[0039] Based on this, the present invention proposes a simple and efficient power module safe drive control technical solution: combining the structural design of a simple control chip and a logic circuit, on the basis of the control of the control chip, through the logic processing of the logic circuit, the pulse width modulation control and safety shutdown of the power module and other functional switching are realized, thereby improving the safety and reliability of the power control product.

[0040] Specifically, the embodiments of the present invention respectively provide a power module controller and an electronic device, and these embodiments will be described in detail below.

[0041] like Figure 1 As shown, in an exemplary embodiment of the present invention, a power module controller is proposed, which includes:

[0042] Micro control module 1;

[0043] The logic processing module 2 is electrically connected to the microcontroller module 1;

[0044] A driving module 3, electrically connected to the logic processing module 2, and used to drive the power module;

[0045] The peripheral power management module 4 is electrically connected to the logic processing module 2, is in communication connection with the microcontrol module 1, and provides operating voltage for the microcontrol module 1, the logic processing module 2 and the driving module 3;

[0046] Among them, the microcontroller module 1 outputs a first pulse width modulation signal, a first enable signal, a first high-side safety signal and a first low-side safety signal, the peripheral power management module 4 outputs a power management signal, the logic processing module 2 receives the first pulse width modulation signal, the first enable signal, the first high-side safety signal, the first low-side safety signal and the power management signal and performs logic processing to obtain and output a second pulse width modulation signal, a second enable signal, a second high-side safety signal and a second low-side safety signal to the driving module 3, so that the driving module 3 enters a pulse width modulation control state or a safety state.

[0047] In detail, Figure 1 As shown, the peripheral power management module 4 includes:

[0048] The power management unit 41 receives a power supply voltage (not shown in the figure) and converts the power supply voltage to obtain a variety of operating voltages, provides operating voltages for the microcontroller module 1, the logic processing module 2 and the driver module 3, is electrically connected to the logic processing module 2, and is communicatively connected to the microcontroller module 1;

[0049] The watchdog unit 42 is in communication with the power management unit 41 and the microcontroller module 1, and is used to monitor the program flow of the microcontroller module 1 and restart the microcontroller module 1 that fails and enters an infinite loop.

[0050] The peripheral power management module 4 can be a system basis chip (System Basis Chip, SBC) or a power management chip (Power Management IC, PMIC), and can also be configured with an independent peripheral power management and control unit 41 and an independent watchdog unit (Watch Dog) 42. The following embodiments are described with an integrated peripheral power management module 4, and the control principle of a separate module is similar and is not described in the embodiments.

[0051] In an optional embodiment of the present invention, the power management and control unit 41 can step down the voltage of a 14V automobile battery to obtain operating voltages of various specifications such as 1.25V, 1.3V, 3.3V, 5V, etc., to power various electronic components in the microcontroller module 1, the logic processing module 2 and the drive module 3 and monitor the operating voltage.

[0052] In an optional embodiment of the present invention, the peripheral power management module 4 and the microcontrol module 1 are configured with a communication interface for signal interaction between the modules, including transmitting status information of the microcontrol module 1, transmitting fault information, and recording fault information; the peripheral power management module 4 is configured with a Reset interface, and the microcontrol module 1 is monitored at all times through the watchdog unit 42. When the data in the registers and memory of the microcontrol module 1 are confused, causing the program pointer error to fall into an infinite loop, the microcontrol module 1 is reset through the watchdog unit 42 to erase the cold state fault.

[0053] In detail, in addition to the communication connection, there is also an electrical connection between the peripheral power management module 4 and the microcontroller module 1 to transmit electrical signals and analog signals, and is equipped with an output port and an input port. The peripheral power management module 4 outputs analog signals and operating voltage to the microcontroller module 1.

[0054] In detail, the microcontroller module 1 is an integrated control chip including multiple functions such as logic self-test function, flash storage function and clock (OSC) function, and can be a microcontroller unit (MCU) or a single chip microcomputer (SCM).

[0055] In detail, the microcontrol module 1 is also communicated with the host computer (not shown in the figure), the host computer sends a drive control instruction to the microcontrol module 1, the microcontrol module 1 is also communicated with the detection module (not shown in the figure), the detection module sends a detection feedback signal to the microcontrol module 1, and after the microcontrol module 1 receives the drive control instruction and the detection feedback signal, it regulates the state (high level or low level) of the first pulse width modulation signal, the first enable signal, the first high-side safety signal and the first low-side safety signal according to the drive control instruction or the detection feedback signal.

[0056] In detail, the microcontroller module 1 is also in communication with the driver module 3 (not shown in the figure). The driver module 3 has a fault self-detection function. The driver module 3 detects its own faults during power-on and operation and feeds back to the microcontroller module 1.

[0057] In detail, the peripheral power management module 4 is also communicated with the detection module (not shown in the figure), the detection module sends a detection feedback signal to the peripheral power management module 4, and the peripheral power management module 4 is also communicated with the microcontrol module 1. The peripheral power management module 4 receives the feedback signal of the microcontrol module 1, and the peripheral power management module 4 adjusts the state (high level or low level) of the power management signal according to the detection feedback signal and the feedback signal, and combines the logic processing module 2 to perform logical processing on the first pulse width modulation signal, the first enable signal, the first high-side safety signal, the first low-side safety signal and the power management signal to obtain the second pulse width modulation signal, the second enable signal, the second high-side safety signal and the second low-side safety signal. Through the comprehensive control of the second pulse width modulation signal, the second enable signal, the second high-side safety signal and the second low-side safety signal, the driving module 3 enters the pulse width modulation control state or the safety state.

[0058] In more detail, Figure 1 As shown, the output end of the logic processing module 2 transmits the second pulse width modulation signal to the driving module 3, so that the driving module 3 enters the pulse width modulation control state; the output end of the logic processing module 2 transmits the second low-side safety signal to the driving module 3, so that the driving module 3 enters the preset safety state; the output end of the logic processing module 2 transmits the second high-side safety signal to the driving module 3, so that the driving module 3 enters the preset safety state; the output end of the logic processing module 2 transmits the second enable signal to the driving module 3, so that the driving module 3 enters the safety state or enters the pulse width modulation control state.

[0059] In detail, Figure 1 As shown, the logic processing module 2 includes a first logic processing unit 21 , and the first logic processing unit 21 performs an AND operation on the first pulse width modulation signal and the first enable signal to obtain and output a second pulse width modulation signal to the driving module 3 .

[0060] In more detail, in an optional embodiment of the present invention, if Figure 2 As shown, the first logic processing unit 21 includes a two-input logic AND gate U1, the first input terminal of the logic AND gate U1 is connected to the first pulse width modulation signal, the second input terminal of the logic AND gate U1 is connected to the first enable signal, and the output terminal of the logic AND gate U1 outputs the second pulse width modulation signal.

[0061] In detail, Figure 1As shown, the logic processing module 2 includes a second logic processing unit 22, and the second logic processing unit 22 is arranged in parallel with the first logic processing unit 21. The second logic processing unit 22 includes a first logic processing sub-unit 221, a second logic processing sub-unit 222 and a third logic processing sub-unit 223; the first logic processing sub-unit 221 performs an AND operation on the first high-side safety signal, the first low-side safety signal and the power management signal to obtain and output the second high-side safety signal to the driving module 3; the second logic processing sub-unit 222 performs an AND operation on the first enable signal and the power management signal to obtain and output the second enable signal to the driving module 3; the third logic processing sub-unit 223 performs an AND-NOT operation on the first low-side safety signal and the power management signal to obtain and output the second low-side safety signal to the driving module 3.

[0062] In more detail, in an optional embodiment of the present invention, if Figure 3 As shown, the first logic processing subunit 221 includes two two-input logic AND gates U2~U3, the first input terminal of the first logic AND gate U2 is connected to the first high-side safety signal, the second input terminal of the first logic AND gate U2 is connected to the power management signal, the output terminal of the first logic AND gate U2 is connected to the first input terminal of the second logic AND gate U3, the second input terminal of the second logic AND gate U3 is connected to the first low-side safety signal, and the output terminal of the second logic AND gate U3 outputs the second high-side safety signal; the second logic processing subunit 222 includes a two-input logic AND gate U4, the first input terminal of the logic AND gate U4 is connected to the first enable signal, the second input terminal of the logic AND gate U4 is connected to the power management signal, and the output terminal of the logic AND gate U4 outputs the second enable signal; the third logic processing subunit 223 includes a two-input logic NAND gate U5, the first input terminal of the logic NAND gate U5 is connected to the first low-side safety signal, the second input terminal of the logic NAND gate U5 is connected to the power management signal, and the output terminal of the logic NAND gate U5 outputs the second low-side safety signal.

[0063] In more detail, Figure 3 As shown, the first high-side safety signal and the power management signal are subjected to an AND logic judgment, so that the preset safety state can be entered only when the power management signal is pulled high; wherein the first low-side safety signal and the power management signal are subjected to an AND-NOT logic judgment, so that the preset safety state can be entered only when the power management is pulled high; wherein the first enable signal and the power management signal are subjected to an AND logic judgment, so that when the power management signal is pulled high, the required second enable signal can be output.

[0064] In more detail, Figure 3As shown, the logic AND gates U2~U3 judge the first high-side safety signal, the first low-side safety signal, and the power management signal, and output the second high-side signal. When the power management signal is pulled high, if the first high-side safety signal is at a high level and the first low-side safety signal is at a high level, then the output second high-side safety signal is at a high level; the NAND gate U5 judges the first low-side safety signal and the power management signal. According to the above assumptions, when the power management signal is pulled high, the first high-side safety signal output by the micro-control module 1 is at a high level, the first low-side safety signal is at a high level, and the second low-side safety signal output from the output end of the NAND gate U5 is at a low level, and is simultaneously input to the drive module 3 together with the second high-side safety signal output at a high level, so that the drive module 3 enters an upper bridge arm short-circuit safety state.

[0065] In more detail, in an optional embodiment of the present invention, Figure 3 Optimization is performed based on the Figure 4 As shown, the first logic processing subunit 221 includes a three-input logic AND gate U6, the first input terminal of the logic AND gate U6 is connected to the first high-side safety signal, the second input terminal of the logic AND gate U6 is connected to the first low-side safety signal, the third input terminal of the logic AND gate U6 is connected to the power management signal, and the output terminal of the logic AND gate U6 outputs the second high-side safety signal; the second logic processing subunit 222 includes a two-input logic AND gate U4, the first input terminal of the logic AND gate U4 is connected to the first enable signal, the second input terminal of the logic AND gate U4 is connected to the power management signal, and the output terminal of the logic AND gate U4 outputs the second enable signal; the third logic processing subunit 223 includes a two-input logic NAND gate U5, the first input terminal of the logic NAND gate U5 is connected to the first low-side safety signal, the second input terminal of the logic NAND gate U5 is connected to the power management signal, and the output terminal of the logic NAND gate U5 outputs the second low-side safety signal.

[0066] In more detail, Figure 4 As shown, in this embodiment, a three-input logic AND gate U6 is used to replace Figure 3 The two two-input logic AND gates U2-U3 shown use three-input logic gates to optimize the number of components and circuits in the logic protection circuit and reduce system product cost.

[0067] In more detail, in an optional embodiment of the present invention, Figure 3 Optimization is performed based on the Figure 5As shown, the first logic processing subunit 221 includes four two-input logic AND gates U2, U3, U7, and U8, the first input terminal of the first logic AND gate U7 is connected to the first enable signal, the second input terminal of the first logic AND gate U7 is connected to the first high-side safety signal, the output terminal of the first logic AND gate U7 is connected to the second input terminal of the second logic AND gate U8, the first input terminal of the second logic AND gate U8 is connected to the first low-side safety signal, the output terminal of the second logic AND gate U8 outputs the second high-side safety signal, the first input terminal of the third logic AND gate U2 is connected to the first high-side safety signal, the second input terminal of the third logic AND gate U2 is connected to the first enable signal, the output terminal of the third logic AND gate U2 is connected to the first input terminal of the fourth logic AND gate U3, the second input terminal of the fourth logic AND gate U3 is connected to the first low-side safety signal, and the output terminal of the fourth logic AND gate U3 outputs the second high-side safety signal; the second logic processing subunit 222 includes two two-input logic AND gates U4 and U9. , the first input terminal of the first logic AND gate U9 is connected to the power management signal, the second input terminal of the first logic AND gate U9 is connected to the first enable signal, and the output terminal of the first logic AND gate U9 outputs the second enable signal, the first input terminal of the second logic AND gate U4 is connected to the first enable signal, the second input terminal of the second logic AND gate U4 is connected to the power management signal, and the output terminal of the second logic AND gate U4 outputs the second enable signal; the third logic processing sub-unit 223 includes two two-input logic NAND gates U5 and U10, the first input terminal of the first logic NAND gate U10 is connected to the power management signal, the second input terminal of the first logic NAND gate U10 is connected to the first low-side safety signal, and the output terminal of the first logic NAND gate U10 outputs the second low-side safety signal, the first input terminal of the second logic NAND gate U5 is connected to the first low-side safety signal, the second input terminal of the second logic NAND gate U5 is connected to the power management signal, and the output terminal of the second logic NAND gate U5 outputs the second low-side safety signal.

[0068] In more detail, Figure 5 As shown, in this embodiment, the input terminal signals of the logic AND gate U7 and the logic AND gate U2 are opposite to each other; the input terminal signals of the logic AND gate U9 and the logic AND gate U4 are opposite to each other; the input terminal signals of the logic NAND gate U10 and the logic NAND gate U5 are opposite to each other. For example, the first input terminal of the logic AND gate U2 receives the first high-side safety signal, the second input terminal of the logic AND gate U2 receives the first enable signal, and the input terminal signals of the logic AND gate U7 and the logic AND gate U2 are opposite to each other, that is, the first input terminal of the logic AND gate U7 receives the first enable signal, and the second input terminal of the logic AND gate U7 receives the first high-side safety signal. By configuring the logic gates with opposite signals, the stability and safety of the system signal transmission can be effectively improved.

[0069] In more detail, Figure 6 Shown Figure 52 is a schematic diagram of a partial hardware logic protection peripheral circuit and implementation, which describes a partial circuit involved in the second logic processing subunit 222. The remaining logic circuits are basically similar to this embodiment, and the remaining circuits can be known through the hardware logic protection circuit of the part.

[0070] In more detail, Figure 6 As shown, the first enable signal is transmitted to the input port A of the logic AND gate U4 and the input port B of the logic AND gate U9 through the resistor R1, and the power management signal is transmitted to the input port B of the logic AND gate U4 and the input port A of the logic AND gate U9 through the resistor R2. Figure 5 The opposite logic gate configuration described in the above. The power input port VCC of the logic AND gate U4 and the logic AND gate U9 is connected to a 5V power supply. The power supply can be a system power management module or a micro control unit or a configuration LDO circuit distribution. The 5V power supply needs to be configured with a capacitor to improve the stability of the power supply, such as the capacitors C1 and C2 shown in the figure. The ground port GND of the logic AND gate U4 and the logic AND gate U9 is connected to the ground line and capacitor in the circuit board, and the common ground reduces the interference of the power supply. The signal output by the logic AND gate U4 is connected to the ground by a large resistor R3, and the signal is further filtered. The output signal of the logic AND gate U4 is connected to the output signal of the logic AND gate U9 and the resistor R4, wherein the resistor R4 is much smaller than R3, to avoid the wrong flow of the signal at the output end of the logic AND gate U9. The output signal of the logic AND gate U4 and the logic AND gate U9 is connected to the capacitor C3 and the resistor R5 to GND. The capacitor C3 and the resistor R5 are connected in parallel to form an RC filter structure, which further filters the signal and outputs the second enable signal.

[0071] In this example, multiple filtering and signal reverse processing can improve the stability and reliability of the signal and greatly enhance the safety of the system.

[0072] In detail, in an optional embodiment of the present invention, the logic relationship matrix corresponding to the power management signal, the first enable signal, the first high-side safety signal, the first low-side safety signal, the second enable signal, the second high-side safety signal and the second low-side safety signal can be shown in the following table:

[0073] Power management signal The first enable signal First high side safety signal First low side safety signal The second enable signal Second high side safety signal Second low side safety signal 0 X X X 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0

[0074] Among them, when the power management signal is 0 (ie, low level), no matter whether the first high-side safety signal is high or low, the second low-side safety signal will be 1 (ie, high level), and the lower bridge arm safety state will be entered first.

[0075] In detail, the driving module 3 includes at least one driving chip (not shown in the figure), which is electrically connected to the logic processing module 2 and the power module (not shown in the figure), respectively, and the driving chip drives and controls the power module under the control of the output signal of the logic processing module 2. The number of driving chips in the driving module 3 is configured according to actual needs, and can be 1 or n, where n is an integer greater than or equal to 2.

[0076] In the above-mentioned power module controller, the power module controller is designed based on the microcontroller module, the logic processing module, the drive module and the peripheral power management module. The two simple control chips of the microcontroller module and the peripheral power management module, and the pure integrated circuit products of the logic processing module and the drive module are combined to form a simple and efficient power module safety drive control technical solution, which can realize pulse width modulation control under normal conditions and make the drive module and the corresponding power module enter a safe state in case of failure, thereby improving the safety and reliability of the power control product; at the same time, the two-stage control chip does not involve complex calculation processing, only a simple control chip is needed, and the circuit design of the logic processing module only needs logic components and a few peripheral electronic components to be realized, and the number of electronic components involved is not large, and the corresponding structure is simple and low in cost, and it completely relies on the processing switching of electronic components, and its switching control speed is fast, and the stability and reliability are strong.

[0077] Based on the design concept of the above-mentioned power module controller, in another exemplary embodiment of the present invention, an electronic device is proposed, which includes a power module and the above-mentioned power module controller, the power module is electrically connected to the power module controller, and the power module is safely driven and controlled by the power module controller.

[0078] In the above-mentioned electronic equipment, based on the structural design of the power module controller, combined with two simple control chips, the microcontroller module and the peripheral power management module, and the pure integrated circuit products of the logic processing module and the driver module, a simple and efficient power module safety drive control technical solution is formed, which can realize pulse width modulation control under normal conditions, and make the driver module and the corresponding power module enter a safe state in case of failure, thereby improving the safety and reliability of the power control product; at the same time, the two-stage control chip does not involve complex calculation processing, only a simple control chip is needed, and the circuit design of the logic processing module only requires logic components and a few peripheral electronic components to be realized, and the number of electronic components involved is not large, and the corresponding structure is simple and low in cost, and it completely relies on the processing switching of electronic components, and its switching control speed is fast, and the stability and reliability are strong.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power module controller, characterized in that: include: Microcontroller module; A logic processing module, electrically connected to the microcontroller module; A driving module, electrically connected to the logic processing module, and used to drive the power module; A peripheral power management module is electrically connected to the logic processing module, is in communication connection with the microcontrol module, and provides operating voltage for the microcontrol module, the logic processing module and the driving module; Wherein, the microcontroller module outputs a first pulse width modulation signal, a first enable signal, a first high-side safety signal and a first low-side safety signal, the peripheral power management module outputs a power management signal, the logic processing module receives the first pulse width modulation signal, the first enable signal, the first high-side safety signal, the first low-side safety signal and the power management signal and performs logic processing to obtain and output a second pulse width modulation signal, a second enable signal, a second high-side safety signal and a second low-side safety signal to the driver module, so that the driver module enters a pulse width modulation control state or a safety state; The logic processing module includes a second logic processing unit, and the second logic processing unit includes a first logic processing sub-unit, a second logic processing sub-unit and a third logic processing sub-unit; the first logic processing sub-unit performs an AND operation on the first high-side safety signal, the first low-side safety signal and the power management signal to obtain and output a second high-side safety signal to the driving module; the second logic processing sub-unit performs an AND operation on the first enable signal and the power management signal to obtain and output a second enable signal to the driving module; the third logic processing sub-unit performs an AND-NOT operation on the first low-side safety signal and the power management signal to obtain and output a second low-side safety signal to the driving module.

2. The power module controller according to claim 1, characterized in that: The microcontrol module receives the drive control instruction of the host computer and the detection feedback signal of the detection module, and adjusts the states of the first pulse width modulation signal, the first enable signal, the first high-side safety signal and the first low-side safety signal according to the drive control instruction or the detection feedback signal. The peripheral power management module receives the detection feedback signal of the detection module and the feedback signal of the microcontrol module, and adjusts the state of the power management signal according to the detection feedback signal and the feedback signal. Combined with the logic processing of the logic processing module, the drive module enters a pulse width modulation control state or a safe state.

3. The power module controller according to claim 2, characterized in that: The logic processing module includes a first logic processing unit, which performs an AND operation on the first pulse width modulation signal and the first enable signal to obtain and output the second pulse width modulation signal to the driving module.

4. The power module controller according to claim 3, characterized in that: The first logic processing unit includes a two-input logic AND gate, a first input terminal of the logic AND gate is connected to the first pulse width modulation signal, a second input terminal of the logic AND gate is connected to the first enable signal, and an output terminal of the logic AND gate outputs the second pulse width modulation signal.

5. The power module controller according to claim 1, characterized in that: The first logic processing subunit includes two two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the first high-side safety signal, the second input terminal of the first logic AND gate is connected to the power management signal, the output terminal of the first logic AND gate is connected to the first input terminal of the second logic AND gate, the second input terminal of the second logic AND gate is connected to the first low-side safety signal, and the output terminal of the second logic AND gate outputs the second high-side safety signal.

6. The power module controller according to claim 1, characterized in that: The first logic processing subunit includes a three-input logic AND gate, a first input terminal of the logic AND gate is connected to the first high-side safety signal, a second input terminal of the logic AND gate is connected to the first low-side safety signal, a third input terminal of the logic AND gate is connected to the power management signal, and an output terminal of the logic AND gate outputs the second high-side safety signal.

7. The power module controller according to claim 1, characterized in that: The first logic processing subunit includes four two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the first enable signal, the second input terminal of the first logic AND gate is connected to the first high-side safety signal, the output terminal of the first logic AND gate is connected to the second input terminal of the second logic AND gate, the first input terminal of the second logic AND gate is connected to the first low-side safety signal, the output terminal of the second logic AND gate outputs the second high-side safety signal, the first input terminal of the third logic AND gate is connected to the first high-side safety signal, the second input terminal of the third logic AND gate is connected to the first enable signal, the output terminal of the third logic AND gate is connected to the first input terminal of the fourth logic AND gate, the second input terminal of the fourth logic AND gate is connected to the first low-side safety signal, and the output terminal of the fourth logic AND gate outputs the second high-side safety signal.

8. The power module controller according to claim 1, characterized in that: The second logic processing subunit includes a two-input logic AND gate, a first input terminal of the logic AND gate is connected to the first enable signal, a second input terminal of the logic AND gate is connected to the power management signal, and an output terminal of the logic AND gate outputs the second enable signal.

9. The power module controller according to claim 1, characterized in that: The second logic processing subunit includes two two-input logic AND gates, the first input terminal of the first logic AND gate is connected to the power management signal, the second input terminal of the first logic AND gate is connected to the first enable signal, the output terminal of the first logic AND gate outputs the second enable signal, the first input terminal of the second logic AND gate is connected to the first enable signal, the second input terminal of the second logic AND gate is connected to the power management signal, and the output terminal of the second logic AND gate outputs the second enable signal.

10. The power module controller according to claim 1, characterized in that: The third logic processing subunit includes a two-input logic NAND gate, a first input terminal of the logic NAND gate is connected to the first low-side safety signal, a second input terminal of the logic NAND gate is connected to the power management signal, and an output terminal of the logic NAND gate outputs the second low-side safety signal.

11. The power module controller according to claim 1, characterized in that: The third logic processing sub-unit includes two two-input logic NAND gates, the first input end of the first logic NAND gate is connected to the power management signal, the second input end of the first logic NAND gate is connected to the first low-side safety signal, the output end of the first logic NAND gate outputs the second low-side safety signal, the first input end of the second logic NAND gate is connected to the first low-side safety signal, the second input end of the second logic NAND gate is connected to the power management signal, and the output end of the second logic NAND gate outputs the second low-side safety signal.

12. An electronic device, characterized in that: It comprises a power module and a power module controller as described in any one of claims 1 to 11, wherein the power module is electrically connected to the power module controller, and the power module is safely driven and controlled by the power module controller.

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