A light emitting element and a method for preparing the same

Abstract

The present invention provides a light-emitting element, which relates to the field of semiconductor technology. The conventional symmetrical electrode structure design is changed, and an asymmetrical electrode structure and a large number of N holes are adopted to increase the current channel between the P electrode and the N electrode and reduce the voltage between the P electrode and the N electrode. The pad of the light-emitting element includes two N-type pads and one P-type pad, and the P-type pad is located between the two N-type pads. The area ratio of the N-type pad is greater than the area ratio of the P-type pad, and a plurality of N holes are evenly arranged on the end face of each N-type pad. The larger the area ratio of the N-type pad, the wider the distribution of the N holes, so there will be more current channels between the P electrode and the N electrode, and the current expansion between the P electrode and the N electrode will be more sufficient, thereby reducing the voltage between the P electrode and the N electrode. In addition, the present invention also provides a method for preparing a light-emitting element.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light-emitting element and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor light-emitting device with photoelectric performance characteristics such as low energy consumption, long life, good stability, fast response, and stable luminous wavelength. Therefore, it is widely used in lighting, home appliances, display screens, indicator lights and other fields.

[0003] Compared with the traditional upright structure, flip-chip LED chips have more advantages in heat dissipation and luminous efficiency, so flip-chip LED chips are increasingly widely used. Conventional flip-chip P and N contact materials can form good ohmic contact with GaN. However, in practical applications, automotive-grade high-power chips have increasingly higher requirements for low voltage. By adjusting the contact material, the voltage can only be slightly adjusted, and the voltage cannot be significantly reduced. At the same time, the adjustment of the structure during the voltage reduction process will also cause a loss in brightness, which cannot meet market demand. Summary of the invention

[0004] The main purpose of the present invention is to provide a light-emitting element and a method for preparing the same, aiming to solve the technical problem in the prior art that the voltage cannot be significantly reduced and the adjustment of the structure during the voltage reduction process will cause a loss in brightness.

[0005] To achieve the above object, the present invention provides a light-emitting element, comprising a substrate and a light-emitting structure, a current spreading layer, a passivation layer, a reflective layer, a barrier layer, an insulating layer, and a pad sequentially grown on the substrate;

[0006] Among them, the pad includes two N-type pads and one P-type pad, the P-type pad is located between the two N-type pads, the area ratio of the N-type pad is greater than the area ratio of the P-type pad, and a plurality of N holes are evenly arranged on the end surface of each N-type pad to increase the current channel between the P electrode and the N electrode, so that the current between the P electrode and the N electrode is fully expanded, thereby reducing the voltage between the P electrode and the N electrode.

[0007] Optionally, the plurality of N holes are arranged in a plurality of columns on the end surface of the N-type pad, and the N holes in two adjacent columns are staggered so that the N holes are evenly distributed on the end surface of the N-type pad.

[0008] Optionally, the area of ​​the N-type pad is more than 10 times that of the P-type pad, so that a plurality of N holes can be excavated on the end surface of the N-type pad to increase the current channel between the P electrode and the N electrode.

[0009] Optionally, the openings of the current spreading layer and the openings of the passivation layer are arranged in a staggered manner to improve brightness.

[0010] Optionally, the reflective metal used to make the reflective layer includes Ag alloy and 2%-5% Pt component to improve brightness.

[0011] In addition, to achieve the above object, the present invention also provides a method for preparing a light-emitting element, comprising the following steps:

[0012] An N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially grown on the substrate to form an epitaxial layer;

[0013] Etching isolation trenches between adjacent core particles so that each core particle is completely isolated on the epitaxial layer to form an independent unit;

[0014] Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by inductively coupled plasma etching to form an N-type conductive region;

[0015] Fabricating a current spreading layer on the P-type semiconductor layer;

[0016] forming a passivation layer on the current spreading layer;

[0017] forming a reflective layer on the passivation layer;

[0018] forming a blocking layer on the reflective layer;

[0019] forming an insulating layer on the barrier layer;

[0020] Deposit N-type pads and P-type pads.

[0021] Optionally, the step of forming a passivation layer on the current spreading layer includes:

[0022] First, evaporate a layer of SiO 2 film layer, and then on the SiO 2 A layer of TiO is deposited on the film 2 Membrane layer;

[0023] Repeat the above evaporation process until a thickness of SiO 2 / TiO 2 Lamination;

[0024] The SiO 2 / TiO 2 stack until the bottom layer of SiO is etched 2 Film

[0025] The SiO 2 / TiO 2 The bottom layer of the stack is SiO 2 Membrane layer.

[0026] Optionally, the step of making a reflective layer on the passivation layer includes:

[0027] A layer of reflective metal is plated on the passivation layer by a magnetron sputtering method or a vacuum evaporation coating process;

[0028] While the reflective metal is being coated, a Ti / Pt or TiW film layer is continuously deposited on the upper layer to cover the reflective metal.

[0029] Optionally, the step of forming an insulating layer on the barrier layer includes:

[0030] The passivation film is deposited at 250°C-300°C using plasma enhanced vapor deposition;

[0031] Then, a layer with a thickness of Al metal reflective layer;

[0032] Then depositing a passivation film layer on the Al metal reflective layer;

[0033] Then, the passivation film layer is opened by yellow light photoresist exposure, development and etching.

[0034] Optionally, depositing the N-type pad and the P-type pad comprises the following steps:

[0035] The pads are patterned by yellow light process, exposure and development;

[0036] Use Asher process to remove negative resist film;

[0037] After the source was washed with water, Cr / Pt / Ni / Pt / Ni / AuSn was deposited using an E-Beam device;

[0038] Use alkaline stripping solution to remove photoresist.

[0039] In the technical solution provided by the present invention, the light-emitting element includes a substrate and a light-emitting structure, a current expansion layer, a passivation layer, a reflective layer, a barrier layer, an insulating layer, and a pad sequentially grown on the substrate; wherein the pad includes two N-type pads and one P-type pad, the P-type pad is located between the two N-type pads, the area ratio of the N-type pad is greater than the area ratio of the P-type pad, and a plurality of N holes are evenly arranged on the end face of each N-type pad to increase the current channel between the P electrode and the N electrode, so that the current between the P electrode and the N electrode is fully expanded, thereby reducing the voltage between the P electrode and the N electrode. In the present application, by arranging the P-type pad between the two N-type pads, the conventional symmetrical electrode structure design is changed, so that the current can be expanded more fully, thereby reducing the voltage between the PN electrodes. In addition, the area of ​​the N-type pad is much larger than the area of ​​the P-type pad, which increases the area ratio of the N-type pad. The area of ​​the N-type pad occupies a larger proportion, the distribution of the N holes is wider, and the contact area of ​​the N electrode is larger, so there will be more current channels between the P electrode and the N electrode, and the current expansion between the P electrode and the N electrode will be more sufficient, thereby reducing the voltage between the P electrode and the N electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0041] Figure 1 A schematic structural diagram of an embodiment of a light emitting element provided by the present invention;

[0042] Figure 2 for Figure 1 A top view of the light emitting element;

[0043] Figure 3 for Figure 1 A schematic diagram of the structure of the N-type conductive region of the light-emitting element;

[0044] Figure 4 for Figure 1 A schematic diagram of the structure of the current spreading layer of the light-emitting element;

[0045] Figure 5 for Figure 1 A schematic diagram of the structure of the passivation layer of the light emitting element;

[0046] Figure 6 for Figure 1 A schematic diagram of the structure of the reflective layer of the light emitting element;

[0047] Figure 7 for Figure 1 A schematic diagram of the structure of the light emitting element blocking layer;

[0048] Figure 8 for Figure 1 A schematic diagram of the structure of the insulating layer of the light emitting element;

[0049] Fig. 9 for Figure 1 A schematic diagram of the structure of the light emitting element pad;

[0050] Fig.10 A schematic diagram of a process for preparing a light-emitting element according to an embodiment of the present invention

[0051] Description of Figure Numbers:

[0052] Label name Label name 100 Light-emitting components 105 Barrier layer 101 Substrate 106 Insulation layer 102 Current spreading layer 107 Pads 103 Passivation layer 1071 N-type pad 104 Reflective layer 1072 P-type pad 1073 N hole

[0053] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. The technical solution in the present invention is clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0056] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0057] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0058] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0059] It should be noted that if a directional indication is involved in the embodiment of the present invention, the directional indication is only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0060] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0061] In the description of the present invention, it should be noted that the terms "upper", "lower", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0062] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] Furthermore, in the description of the present invention, unless otherwise specified, “plurality”, “multiple roots”, and “multiple groups” mean two or more.

[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] In practical applications, automotive-grade high-power chips have increasingly higher requirements for low voltage. By adjusting the contact material, the voltage can only be slightly adjusted, and it is impossible to significantly reduce the voltage. At the same time, the adjustment of the structural strips during the voltage reduction process will cause a loss in brightness. In view of this, the present invention provides a light-emitting element and a preparation method thereof, aiming to solve the above problems.

[0066] See also Figure 1 , Figure 1 The schematic diagram of the structure of an embodiment of the light-emitting element 100 provided by the present invention. The light-emitting element 100 includes a substrate 101, a light-emitting structure, a current spreading layer 102, a passivation layer 103, a reflective layer 104, a barrier layer 105, an insulating layer 106, and a pad 107. The light-emitting structure, the current spreading layer 102, the passivation layer 103, the reflective layer 104, the barrier layer 105, the insulating layer 106, and the pad are sequentially grown on the substrate 101.

[0067] The substrate material of the semiconductor device is also called the substrate material, and the epitaxial layer is grown on the substrate material. There are many kinds of LED substrate materials. In this embodiment, a sapphire substrate is used, which has the advantages of good chemical stability, no absorption of visible light, and good light transmittance.

[0068] The light-emitting structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially formed on a sapphire substrate. A buffer layer and a light-emitting structure are grown on a sapphire substrate by metal organic chemical vapor deposition technology (Metal Organic Chemical Vapor Deposition). The light-emitting structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer formed sequentially, which constitute the epitaxial layer of the chip. The current spreading layer 102 is formed by depositing an ITO layer on the surface of the P-type semiconductor layer by a magnetron sputtering process, and is used to form a P-type ohmic contact after annealing. The passivation layer 103 is SiO evaporated on the current spreading layer using a DBR evaporation device. 2 / TiO 2 The reflective layer 104 is formed by depositing a reflective metal on the passivation layer by magnetron sputtering or vacuum evaporation coating process. The barrier layer 105 is a film layer plated on the reflective layer 104 by vacuum evaporation coating method. The barrier layer 105 is mainly composed of Au, and the remaining components include one or more of Cr / Pt / Ti / Ni / Sn elements. The insulating layer 106 is a film layer deposited on the barrier layer by plasma enhanced vapor deposition.

[0069] It should be noted that in this embodiment, the conventional symmetrical electrode structure design is changed and replaced by a new asymmetrical electrode structure design. Figure 2 In this embodiment, the pad 107 includes two N-type pads 1071 and one P-type pad 1072. The two N-type pads 1071 are arranged on both sides, and the P-type pad 1072 is arranged in the middle. Compared with the existing structure, the contact area of ​​the N pad 1071 is increased, and the distribution of the N holes is wider, so there will be more current channels between the P electrode and the N electrode, and the current expansion between the P electrode and the N electrode will be more sufficient, thereby reducing the voltage between the P electrode and the N electrode.

[0070] In addition, in this embodiment, the area ratio of the N-type pad 1071 is set to be more than 10 times that of the P-type pad 1072. The area of ​​the N-type pad 1071 is much larger than that of the P-type pad 1072, which increases the area ratio of the N-type pad 1071 and slightly reduces the area ratio of the P-side light-emitting area. The larger the area ratio of the N-type pad 1071, the wider the distribution of the N holes 1073, and the larger the contact area of ​​the N electrode, which further reduces the voltage between the P electrode and the N electrode and meets more application scenarios.

[0071] Further, in this embodiment, the plurality of N holes 1073 are arranged in a plurality of columns on the end surface of the N-type pad 1071, and the N holes 1073 in two adjacent columns are staggered so that the N holes 1073 are evenly distributed on the end surface of the N-type pad 1071. A plurality of N holes 1073 are provided on the end surface of the N-type pad 1071, and three adjacent N holes 1073 are arranged in an equilateral triangle. The N holes 1073 are evenly distributed, which can better optimize current conduction and reduce voltage compared with conventional non-uniform arrangement.

[0072] Further, see Figure 1 In this embodiment, the openings of the current spreading layer 102 and the openings of the passivation layer 103 are arranged in a staggered manner. 2 / TiO 2 The direct contact between the stack and the P semiconductor layer can achieve the best ODR reflection effect, so the design of ITO patterned openings can not only ensure high-quality current expansion, but also increase the contact area between the passivation layer 103 and the P semiconductor layer.

[0073] Further, see Figure 5 In this embodiment, the SiO 2 / TiO 2 The thickness of the laminate is The passivation layer 103 is SiO2 deposited on the current spreading layer using a DBR evaporation device. 2 / TiO 2 Layer, SiO 2 / TiO 2 The specific evaporation process of the stack is: first evaporate a layer of SiO on the current spreading layer 2 film layer, and then on the SiO 2 A layer of TiO is deposited on the film 2 The above evaporation process is repeated until a film with a thickness of SiO 2 / TiO 2 SiO 2 / TiO 2 The stacked growth forms a DBR structure, and at the same time forms an ODR structure with GaN and Ag, which further improves the reflectivity compared to the traditional ODR structure.

[0074] Furthermore, participate Figure 6In this embodiment, the reflective metal used to make the reflective layer 104 includes an Ag alloy and 2%-5% Pt. In other embodiments, the reflective metal of the reflective layer can also select Al / Rh as the reflective layer metal, but in this embodiment, it is preferred to select an Ag alloy component doped with 2%-5% Pt. The advantage of this design is that it can reduce the migration of Ag; at the same time, it shortens the distance between the reflective layer and the edge of the Mesa, increases the area of ​​the reflective layer, and improves the brightness. In addition, by filling the Ag reflective metal through the N hole 1073, the height difference of the film layer caused by the N hole 1073 is reduced, the eutectic void rate of the chip package is reduced, and the product reliability is improved.

[0075] In addition, in order to achieve the above-mentioned object of the invention, the present invention also provides a method for preparing a light-emitting element. Fig.10 , is a flow chart of an embodiment of a method for preparing a light-emitting element according to the present invention, wherein the method for preparing a light-emitting element comprises the following steps:

[0076] Step S10: growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer in sequence on the substrate 101 to form an epitaxial layer.

[0077] Step S20: etching isolation trenches between adjacent core particles so that each core particle is completely isolated on the epitaxial layer to form an independent unit.

[0078] Step S30: Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by inductively coupled plasma etching to form an N-type conductive region.

[0079] Step S40: forming a current spreading layer 102 on the P-type semiconductor layer.

[0080] Step S50 : forming a passivation layer 103 on the current spreading layer 102 .

[0081] Step S60 : forming a reflective layer 104 on the passivation layer 103 .

[0082] Step S70 : forming a blocking layer 105 on the reflective layer 104 .

[0083] Step S80 : forming an insulating layer 106 on the barrier layer 105 .

[0084] Step S90 : depositing N-type pad 1071 and P-type pad 1072 .

[0085] In the present embodiment, a growth substrate 101 is provided, on which a buffer layer (not shown), an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially grown. The N-type semiconductor layer, the active layer, and the P-type semiconductor layer together constitute an epitaxial layer, i.e., a (light-emitting structure). Among them, the growth substrate 101 can be a sapphire substrate, a GaN substrate, a silicon substrate, or a silicon carbide substrate. In the present embodiment, the growth substrate 101 is a sapphire substrate, and the materials of the buffer layer, the N-type semiconductor layer, and the P-type semiconductor layer are all GaN materials. The buffer layer, the N-type semiconductor layer 21, the active layer 22, and the P-type semiconductor layer 23 can all be formed by growth methods such as MOCVD (Metal Organic Chemical Vapor Deposition) and / or MBE (Molecular Beam Epitaxy).

[0086] In step S20, the epitaxial layer structure 2 is deeply etched by an inductively coupled plasma etching process to form isolation channels between adjacent light-emitting elements, so that each light-emitting element is completely isolated on the growth substrate 101 to form an independent light-emitting element unit. The specific etching depth is determined according to the thickness of the epitaxial layer, and is generally between 6-7μm. It should be noted that in this embodiment, a structure including a plurality of light-emitting elements is produced by step S10, and then deep etching is performed to completely isolate each light-emitting element on the growth substrate 101 to form an independent light-emitting element unit. In other embodiments of the present invention, a single light-emitting element structure can also be formed directly on the growth substrate 101 by step S10.

[0087] Combination Figure 3 As shown, in step S30, an inductively coupled plasma etching process is used to form a groove structure, and the etching depth is determined by the growth thickness of each semiconductor layer, generally 1-1.5 μm deep. In this embodiment, N-type conductive openings are arranged around the light-emitting element in step S30 to form an N-type conductive area.

[0088] Combination Figure 4 As shown, in step S40, an ITO layer is deposited on the surface of the P-type semiconductor layer 23 by a magnetron sputtering process, and the deposited thickness is The current spreading layer 4 is deposited on the surface of the P-type semiconductor layer 23, and forms a P-type ohmic contact after annealing. ITO is mainly composed of indium tin oxide, which is a semiconductor transparent conductive film. It can have the characteristics of low resistivity and high light transmittance at the same time, meeting the requirements of good conductivity and light transmittance; the function of ITO is to make the electrode and the epitaxial layer form a good ohmic contact, so that the current diffuses on the electrode surface and better passes into the electrode to reduce the voltage. At the same time, the Mg-H bond in the P-type gallium nitride layer is opened by annealing in an oxygen atmosphere, which plays a role in activating Mg and better forming an ohmic contact.

[0089] Combination Figure 5 As shown, in step S50, a passivation layer 103 is evaporated on the current spreading layer 102 using a DBR evaporation device. The material of the passivation layer 103 is SiO 2 、TiO 2 , specifically SiO 2 / TiO 2 The stacked deposition coating is deposited at a temperature of

[0090] Combination Figure 6 and Figure 7 As shown, in step S60, the reflective layer 104 is formed by depositing a reflective metal on the passivation layer by a magnetron sputtering method or a vacuum evaporation coating process. In step S70, the barrier layer is a film layer plated on the reflective layer using a vacuum evaporation coating method, and the barrier layer 105 is mainly composed of Au, and the remaining components include one or more of the Cr / Pt / Ti / Ni / Sn elements. In step S80, the insulating layer 106 is a film layer deposited on the barrier layer 105 using a plasma enhanced vapor deposition method. In step S90, an N-type pad 1071 and a P-type pad 1072 are deposited.

[0091] Further, in this embodiment, step S50 specifically includes the following steps:

[0092] Step S501: First evaporate a layer of SiO 2 film layer, and then on the SiO 2 A layer of TiO is deposited on the film 2 Membrane layer;

[0093] Step S502: Repeat the above evaporation process until a layer with a thickness of SiO 2 / TiO 2 Lamination;

[0094] Step S503: Using ICP dry etching to etch the SiO 2 / TiO 2 The stacking process is continued until the TiO layer at the bottom is etched. 2Film

[0095] Step S504: using BOE wet etching to etch the SiO 2 / TiO 2 The bottom layer of the stack is SiO 2 Membrane layer.

[0096] In this embodiment, the yellow light uniform coating exposure and development process is used to open the pattern to be etched. For the two types of film layers, ICP dry etching and BOE wet etching are used to complete the pattern transfer of the passivation layer. The reason why two methods are selected for etching pattern is that if only dry etching is used, the bottom of the passivation layer 103 is etched, and SiO 2 After etching is complete, the plasma will damage the P GaN surface, causing poor ohmic contact on the chip surface and increased voltage. If only wet etching is used, then SiO 2 and TiO 2 The different corrosion rates of wet BOE will cause different corrosion rates of the two materials in DBR, which will cause different film cross-sections and lead to faults in the thickness of the metal coating, thus affecting the current conduction of the chip and the reliability of quality performance detection, resulting in leakage anomalies. In addition, the reflectivity is improved by increasing the direct contact area between the passivation layer 103 and P GaN in the ODR structure.

[0097] Further, in this embodiment, step S60 specifically includes the following steps:

[0098] Step S601: a layer of reflective metal is plated on the passivation layer by using a magnetron sputtering method or a vacuum evaporation coating process.

[0099] Step S602: while coating the reflective metal, a Ti / Pt or TiW film layer is continuously deposited on the upper layer to cover the reflective metal.

[0100] In this embodiment, an adhesion layer is first deposited, and Ti or Ni is usually used, but since metals absorb light, TCO materials are preferred. In addition, Ag / Al / Rh can be selected as the reflective layer metal, and the coating can be deposited by magnetron sputtering or vacuum evaporation coating process, with a deposition thickness of The reflective metal is plated and a Ti / Pt or TiW film is deposited on the upper layer to cover the reflective metal and inhibit the migration of the reflective metal. Preferably, an Ag alloy composition is selected and 2%-5% Pt composition is doped to reduce the migration of Ag; at the same time, the distance between the reflective layer and the edge of the Mesa is shortened, the area of ​​the reflective layer is increased, and the brightness is improved.

[0101] Further, in this embodiment, step S80 specifically includes the following steps:

[0102] Step S801: depositing a layer with a thickness of Al metal reflective layer.

[0103] Step S802: depositing a passivation film layer on the Al metal reflective layer.

[0104] Step S803: opening holes in the passivation film layer by yellow light photoresist exposure, development and etching.

[0105] Combination Figure 8 As shown, in step S80, a plasma enhanced vapor deposition process is used to deposit a passivation film layer on the entire wafer surface. In this step, the material of the passivation film layer is selected from any one or more stacks of silicon dioxide, silicon nitride, and aluminum oxide, silicon dioxide / silicon nitride, silicon dioxide / silicon nitride / aluminum oxide deposition coating, the deposition temperature is 250°C to 300°C, and the deposition thickness is For example, in this embodiment, the passivation film layer is silicon dioxide, and an independent light-emitting unit structure is formed by deep etching first, and then a silicon dioxide layer is made on the entire surface of the wafer. The insulating property of silicon dioxide is used to prevent leakage caused by direct exposure of the epitaxial layer material after the product is cut. In addition, the passivation film layer is opened by yellow light uniform coating exposure, development and etching, and the Al emission layer is fully covered except for the open area of ​​the passivation film layer, further improving the brightness.

[0106] Further, see Fig. 9 In this embodiment, step S90 specifically includes the following steps:

[0107] Step S901: Patterning the pad by photolithography, exposure, and development;

[0108] Step S902: using the Asher process to remove the negative resist base film;

[0109] Step S903: After the source is washed with water, Cr / Pt / Ni / Pt / Ni / AuSn is deposited using an E-Beam device;

[0110] Step S904: using an alkaline stripping solution to remove the photoresist.

[0111] Here, it should be noted that the thickness of AuSn is 3um-4um.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A light emitting element, characterized in that: It comprises a substrate (101), and a light-emitting structure, a current spreading layer (102), a passivation layer (103), a reflective layer (104), a barrier layer (105), an insulating layer (106), and a pad (107) which are sequentially grown on the substrate (101); The pad (107) comprises two N-type pads (1071) and one P-type pad (1072), the P-type pad (1072) is located between the two N-type pads (1071), the area ratio of the N-type pad (1071) is greater than the area ratio of the P-type pad (1072), and a plurality of N holes (1073) are evenly arranged on the end surface of each N-type pad (1071) to increase the current channel between the P electrode and the N electrode, so that the current between the P electrode and the N electrode is fully expanded, thereby reducing the voltage between the P electrode and the N electrode.

2. The light emitting element according to claim 1, wherein The plurality of N holes (1073) are arranged in a plurality of rows on the end surface of the N-type solder pad (1071), and the N holes (1073) in two adjacent rows are arranged in a staggered manner, so that the N holes (1073) are evenly distributed on the end surface of the N-type solder pad (1071).

3. The light-emitting element according to claim 1 or 2, characterized in that: The area of ​​the N-type pad (1071) is more than 10 times that of the P-type pad (1072), so that a plurality of N holes (1073) can be excavated on the end surface of the N-type pad (1071) to increase the current channel between the P electrode and the N electrode.

4. The light-emitting element according to claim 3, wherein: The openings of the current spreading layer (102) and the openings of the passivation layer (103) are arranged in a staggered manner, so as to improve brightness.

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