Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: forming a substrate comprising a power rail region, the power rail region comprising a first region and a second region, the power rail region having a first fin and a second fin spanning the second region; after forming the first fin and the second fin, forming sidewalls on the sidewall surfaces of the first fin and the second fin; forming a first patterned layer on the substrate, the first patterned layer having a first opening exposing the power rail region; etching the substrate using the first patterned layer as a mask to form the power rail opening within the substrate; forming an isolation film on the inner wall surface of the power rail opening; and after forming the isolation film, forming buried power rails within the power rail openings, the width of the buried power rail in the first region being greater than the width of the buried power rail in the second region. This improves the performance of the formed semiconductor structure and increases the process window of the formation process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory, and analog circuits, with memory devices accounting for a considerable proportion of integrated circuit products.

[0003] With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Erasable Programmable Read-Only Memory (EPROM), Flash memory, and so on.

[0004] Among them, SRAM memory and its formation methods have received increasing attention due to their advantages such as low power consumption and fast operating speed.

[0005] However, in the existing technology, the process window for forming SRAM memory is small, and the performance of SRAM memory needs to be improved. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure and increase the process window.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a power rail region, the power rail region including a first region, a second region, and a third region arranged along a first direction; a first fin located on the first and second regions, and a second fin located on the second and third regions, the first and second fins being arranged along a second direction perpendicular to the first direction; a buried power rail located within the power rail region, the buried power rail of the second region being located within the substrate between the first and second fins, and, in the second direction, the width of the buried power rails of the first and third regions being greater than the width of the buried power rail of the second region; and an isolation film located between the buried power rails and the substrate. Optionally, the structure further includes: a first dielectric layer located on the surface of the substrate, the surface of the first dielectric layer being lower than the top surface of the first and second fins, the buried power rails further extending upward into the first dielectric layer, and the isolation film being located between the sidewalls of the buried power rails and the first dielectric layer, the surface of the buried power rails being lower than the top surface of the first dielectric layer.

[0008] Optionally, it may also include a second dielectric layer located on the top surface of the buried power rail, the second dielectric layer being located within the first dielectric layer.

[0009] Optionally, it also includes: a first source / drain opening located within a first fin on the first region; a first source / drain structure located within the first source / drain opening; and a first conductive structure located on the first region, wherein the first conductive structure contacts the top surface of the first source / drain structure and the top surface of the buried power rail of the first region.

[0010] Optionally, it also includes: a second source / drain opening within the second fin on the third region; a second source / drain structure within the second source / drain opening; and a second conductive structure on the third region, wherein the second conductive structure contacts the top surface of the second source / drain structure and the top surface of the buried power rail on the third region.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: forming a substrate, the substrate including a power rail region, the power rail region including a first region and a second region arranged along a first direction, the power rail region having a first fin and a second fin arranged along a second direction, the first fin and the second fin spanning the second region, the second direction being perpendicular to the first direction; after forming the first fin and the second fin, forming sidewalls on the sidewall surfaces of the first fin and the second fin; after forming the sidewalls on the sidewall surfaces of the first fin and the second fin, forming a first patterned layer on the substrate, the top surface of the first patterned layer being higher than the top surface of the first fin and the second fin, the first patterned layer having a first opening exposing the power rail region; etching the substrate using the first patterned layer as a mask to form a power rail opening in the substrate; forming an isolation film on the inner wall surface of the power rail opening; after forming the isolation film, forming a buried power rail in the power rail opening, wherein, in the second direction, the width of the buried power rail in the first region is greater than the width of the buried power rail in the second region.

[0012] Optionally, it further includes: forming a first dielectric layer on the substrate surface before forming the sidewall, the surface of the first dielectric layer being lower than the top surface of the first fin and the second fin; and etching the first dielectric layer using the first patterned layer as a mask before etching the substrate using the first patterned layer as a mask, until the substrate surface is exposed, and forming a first extended opening in the first dielectric layer.

[0013] Optionally, the first extended opening communicates with the power rail opening, the isolation membrane is also formed on the inner wall surface of the first extended opening, the embedded power rail is also formed inside the first extended opening, and the surface of the embedded power rail is lower than the top surface of the first dielectric layer.

[0014] Optionally, it also includes forming a second dielectric layer within the first extended opening after forming the buried power rail.

[0015] Optionally, the top surfaces of the first and second fins may also have a fin mask layer.

[0016] Optionally, the method for forming the sidewall includes: using an atomic layer deposition process to form a sidewall material film on the surface of the first dielectric layer, the surface of the first fin and the second fin, and the surface of the fin mask layer; and using an anisotropic etching process to etch the sidewall material film until the top surface of the fin mask layer and the surface of the first dielectric layer are exposed.

[0017] Optionally, it also includes: removing the first patterned layer after forming the embedded power rail; and removing the sidewall after removing the first patterned layer.

[0018] Optionally, the process for removing the sidewalls includes at least one of dry etching and wet etching.

[0019] Optionally, it further includes: after removing the sidewall, forming a first source / drain opening in the first fin on the first region; forming a first source / drain structure in the first source / drain opening; and after forming the first source / drain structure, forming a first conductive structure on the first region, wherein the first conductive structure contacts the top surface of the first source / drain structure and the top surface of the buried power rail in the first region.

[0020] Optionally, the power rail area further includes a third area. The first area, the second area, and the third area are arranged along a first direction. The first fin is located on the first area and the second area, and the second fin is located on the second area and the third area. The width of the embedded power rail in the third area is also greater than the width of the embedded power rail in the second area.

[0021] Optionally, it further includes: after removing the sidewall, forming a second source / drain opening in the second fin on the third region; forming a second source / drain structure in the second source / drain opening; and after forming the second source / drain structure, forming a second conductive structure on the third region, the second conductive structure contacting the top surface of the second source / drain structure and the top surface of the buried power rail in the third region.

[0022] Optionally, the power rail area further includes a third area, the first area, the second area and the third area are arranged along a first direction, the first fin is located on the first area and the second area, and the second fin is located on the second area and the third area.

[0023] Optionally, the method of forming the first fin and the second fin includes: forming an initial first fin and an initial second fin arranged along a second direction on a substrate, the initial first fin and the initial second fin spanning a first region, a second region and a third region; removing the initial first fin in the third region and the initial second fin in the first region to form the first fin and the second fin.

[0024] Optionally, the thickness of the sidewall ranges from 3 nanometers to 10 nanometers.

[0025] Optionally, the material of the buried power rail includes at least one of rubidium, tungsten, and cobalt.

[0026] Optionally, the material of the first patterning layer includes photoresist.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] In the semiconductor structure formation method provided by the present invention, since sidewalls are formed on the sidewalls of the first and second fins after the first and second fins are formed, a gap can be formed between the sidewalls of the formed power rail openings and the sidewalls of the first and second fins when etching the substrate using the first patterning layer as a mask, thereby achieving self-aligned etching. Therefore, not only can the pattern transfer of buried power rails be achieved with a larger first opening size, but also, through a regular first opening shape (rectangular), buried power rails of different widths can be formed in the first and second regions, increasing the width of the power rails in the first region. This increases the process window of the first patterning layer while forming buried power rails with lower parasitic resistance, improving the performance of the semiconductor structure. Attached Figure Description

[0029] Figures 1 to 5 This is a schematic diagram of the various steps involved in the formation of a semiconductor structure.

[0030] Figures 6 to 21 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, in the prior art, the process window for forming SRAM memory is relatively small, and the performance of SRAM memory needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.

[0032] Figures 1 to 5 This is a schematic diagram of the various steps involved in the formation of a semiconductor structure.

[0033] Please refer to Figure 1 , Figure 1 This is a top view schematic diagram of a semiconductor structure, providing a substrate 100 (such as... Figure 3 As shown in the figure, the substrate 100 includes a cell region C.

[0034] Cell region C is used to form a storage cell of SRAM memory. Cell region C includes a first region I, a second region II, and a third region III arranged along a first direction F.

[0035] The unit region C has a first fin 101, a second fin 102, a third fin 103, and a fourth fin 104 arranged along the second direction X. The substrate 100 surface between the first fin 101, the second fin 102, the third fin 103, and the fourth fin 104 has an isolation layer 110. Furthermore, the first fin 101, the second fin 102, the third fin 103, and the fourth fin 104 all span the first region I, the second region II, and the third region III.

[0036] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 A top-view structural diagram. Figure 3 It is along Figure 2 A cross-sectional structural diagram of the central direction X1-X2 shows that a first patterned layer 120 is formed on the surface of the isolation layer 110, the first fin 101, the second fin 102, the third fin 103, and the fourth fin 104 through photolithography processes such as exposure and development.

[0037] The material of the first patterning layer 120 includes photoresist.

[0038] The first patterned layer 120 has a first opening 121, a second opening 122, and a third opening 123. The first opening 121, the second opening 122, and the third opening 123 all penetrate the first region I, the second region II, and the third region III. Furthermore, the first opening 121 and the third opening 123 expose the isolation layers 110 on opposite sides of the first fin 101 and the fourth fin 104, respectively, while the second opening 122 exposes the isolation layer 110 between the second fin 102 and the third fin 103.

[0039] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A top-view structural diagram. Figure 5 yes Figure 4 A cross-sectional structural diagram along the X3-X4 direction, using the first graphic layer 120 (e.g., Figure 2 and Figure 3 (As shown) Mask etching of isolation layer 110 and substrate 100. A first power rail opening (not shown), a second power rail opening (not shown), and a third power rail opening (not shown) are formed in isolation layer 110 and substrate 100. A first buried power rail 111 is formed in the first power rail opening, and an isolation film (not shown) is provided between the first buried power rail 111 and the inner wall surface of the first power rail opening. A second buried power rail 112 is formed in the second power rail opening, and an isolation film (not shown) is provided between the second buried power rail 112 and the inner wall surface of the second power rail opening. A third buried power rail 113 is formed in the third power rail opening, and an isolation film (not shown) is provided between the third buried power rail 113 and the inner wall surface of the third power rail opening.

[0040] The first buried power rail 111 and the third buried power rail 113 are both used to connect to the common ground terminal VSS, and the second buried power rail 112 is used to connect to the working voltage VDD.

[0041] By forming buried power rails (first buried power rail 111, second buried power rail 112, and third buried power rail 113) for voltage distribution within the substrate 100 and the isolation layer 110, the substrate space between the fins is better utilized. Furthermore, more space is left above the cell region C, allowing for the subsequent formation of structures such as bit lines with larger linewidths.

[0042] Please continue to refer to this. Figure 4 and Figure 5 After forming the first buried power rail 111, the second buried power rail 112 and the third buried power rail 113, the second fin 102 of the third region III and the third fin 103 of the first region I are removed.

[0043] Please continue to refer to this. Figure 4 and Figure 5 Next, an interlayer dielectric layer 130, a plurality of gates 131, a first source / drain structure 141 located in a second fin 102 in the first region I, a second source / drain structure (not shown) located in a third fin 103 in the third region III, a first conductive structure 151 located in the interlayer dielectric layer 130 in the first region I, and a second conductive structure 152 located in the interlayer dielectric layer 130 in the third region III are formed on the cell region C.

[0044] For ease of understanding, Figure 4 The interlayer dielectric layer 130 is not represented in the text, and, Figure 4 The projection 141a of the first source / drain structure 141 on the surface of the substrate 100 and the projection 142a of the second source / drain structure on the surface of the substrate 100 are schematically shown.

[0045] The first conductive structure 151 is in contact with the top of the source-drain structure 141 and the surface of the second buried power rail 112, and the second conductive structure 152 is in contact with the top of the source-drain structure 142 and the surface of the second buried power rail 112.

[0046] However, in the above method, since the pattern of the second power rail opening is defined by the pattern of the second opening 122, and the second opening 122 needs to be formed by precisely aligning the positions between the second gate 132 and the third gate 133, the dimensional accuracy requirements for the second opening 122 are high, and the overlay accuracy requirements for the pattern transferred by the second opening 122 are also high. This results in a small process window and high process difficulty for the photolithography process forming the first patterned layer 120.

[0047] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure and a method for forming the same. By forming sidewalls on the sidewalls of the first and second fins after forming the first and second fins, the performance of the semiconductor structure can be improved and the process window can be increased.

[0048] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figures 6 to 21 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0050] First, a substrate is formed, comprising a power rail region. The power rail region includes a first region and a second region arranged along a first direction. The power rail region has a first fin and a second fin arranged along a second direction, the first and second fins spanning the second region. The second direction is perpendicular to the first direction. For specific steps on forming the substrate, the first fin, and the second fin, please refer to [reference needed]. Figures 6 to 10 .

[0051] Please refer to Figures 6 to 8 , Figure 6 yes Figure 7 A top view of the structure along the central direction M. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along the M1-M2 direction. Figure 8 yes Figure 6 A three-dimensional structural schematic diagram is provided, including an initial substrate (not shown); the initial substrate is etched to form a substrate 200, and initial first fins 201 and initial second fins 202 arranged on the substrate 200 along the second direction X.

[0052] The substrate 200 is made of semiconductor material.

[0053] In this embodiment, the substrate 200 is made of silicon.

[0054] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0055] The substrate 200 includes a power rail region D. The power rail region D is used to form a buried power rail.

[0056] In this embodiment, the power rail region D includes a first region I, a second region II, and a third region III arranged along the first direction Y. The first region I, the second region II, and the third region III can distinguish the different positions of the subsequently formed first fin and second fin in the first direction Y.

[0057] The first direction Y and the second direction X are perpendicular to each other.

[0058] Specifically, the first fin that forms subsequently is located on the first zone I and the second zone II, and the second fin that forms subsequently is located on the second zone II and the third zone III.

[0059] In other embodiments, the power rail region includes a first region and a second region arranged along a first direction. Both the first fin and the second fin are located on the second region, and one of the first fin and the second fin is also located on the first region.

[0060] The initial first fin 201 provides material for the subsequent formation of the first fin, and the initial second fin 202 provides material for the subsequent formation of the second fin.

[0061] In this embodiment, the initial first fin 201 and the initial second fin 202 span the first region I, the second region II and the third region III.

[0062] In this embodiment, the substrate 200 also has a third fin 203 and a fourth fin 204. The third fin 203 and the fourth fin 204 are respectively located on the substrate 200 on both sides of the power rail region D.

[0063] In this embodiment, the subsequently formed first and second fins, as well as the third fin 203 and the fourth fin 204, are used to form an SRAM cell.

[0064] In this embodiment, the method of etching the initial substrate includes: forming a first mask layer 210 on the initial substrate, the first mask layer 210 exposing a portion of the initial substrate surface; etching the initial substrate using the first mask layer 210 as a mask until the substrate 200, initial first fin 201, initial second fin 202, third fin 203 and fourth fin 204 are formed.

[0065] It should be noted that, for ease of understanding, Figure 6 and Figure 8 The first mask layer 210 is not shown in the figure.

[0066] Please refer to Figure 9 and Figure 10 , Figure 9 yes Figure 10 A top view of the structure along the central direction M. Figure 10 yes Figure 9 A cross-sectional structural diagram along the direction M1-M2 shows the removal of the initial first fin 201 of the third region III and the initial second fin 202 of the first region I to form a first fin 205 and a second fin 206. The first fin 205 and the second fin 206 are arranged along the second direction X and span the second region II.

[0067] In this embodiment, the first fin 205 is located on the first region I and the second region II, and the second fin 206 is located on the second region II and the third region III.

[0068] By forming a first fin 205 on the first region I and the second region II, and a second fin 206 on the second region II and the third region III before forming the power rail opening, a larger reserved space is provided for forming the power rail opening in the first region I and the third region III. As a result, the width of the embedded power rail subsequently formed in the power rail opening in the first region I and the third region III can be increased.

[0069] In this embodiment, the method for removing the initial first fin 201 of the third region III and the initial second fin 202 of the first region I includes: forming a second mask layer (not shown) on the substrate 200, the initial first fin 201, the initial second fin 202, the third fin 203 and the fourth fin 204, the second mask layer exposing the first mask layer 210 on the initial first fin 201 of the third region III and the first mask layer 210 on the initial second fin 202 of the first region I; using the second mask layer as a mask, etching the first mask layer 210, the initial first fin 201 and the initial second fin 202 until the first mask layer 210 of the first region I and the third region III, the initial first fin 201 of the third region III and the initial second fin 202 of the first region I are removed, so as to form the first fin 205, the second fin 206 and the fin mask layer 211.

[0070] Specifically, the fin mask layer 211 is located on the top surface of the first fin 205, the second fin 206, the third fin 203 and the fourth fin 204.

[0071] Since the fin mask layer 211 is formed on the top surface of the first fin 205 and the second fin 206, the top surface of the first fin 205 and the second fin 206 can be protected by the fin mask layer 211 during the subsequent etching process to form the power rail opening, so as to reduce the etching damage to the top surface of the first fin 205 and the second fin 206, thereby improving the performance and reliability of the semiconductor structure.

[0072] In other embodiments, the method of forming the first fin, the second fin, the third fin, and the fourth fin includes: forming a patterned fin mask layer on an initial substrate; and etching the initial substrate using the fin mask layer as a mask until the substrate, the first fin, the second fin, the third fin, and the fourth fin are formed.

[0073] In this embodiment, the material of the fin mask layer 211 includes silicon nitride.

[0074] It should be noted that, for ease of understanding, Figure 9The fin mask layer 211 is not shown in the figure.

[0075] In this embodiment, after the formation of the first fin 205, the second fin 206, the third fin 203 and the fourth fin 204, and before the subsequent formation of the sidewalls, a first dielectric layer 220 is formed on the surface of the substrate 200, the surface of the first dielectric layer 220 being lower than the top surfaces of the first fin 205 and the second fin 206.

[0076] The material of the first dielectric layer 220 is different from the material of the fin mask layer 211. Therefore, in the subsequent etching process to form the power rail opening, a higher etching selectivity ratio can be achieved for the first dielectric layer 220 and the fin mask layer 211, reducing the risk of the fin mask layer 211 being worn down to the point of exposing the top surfaces of the first fin 205 and the second fin 206, thereby further reducing the risk of damage to the top surfaces of the first fin 205 and the second fin 206.

[0077] The material of the first dielectric layer 220 is a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0078] Preferably, the material of the first dielectric layer 220 includes silicon oxide.

[0079] Please refer to Figure 11 and Figure 12 , Figure 11 yes Figure 12 A top view of the structure along the central direction M. Figure 12 yes Figure 11 A cross-sectional structural diagram along the direction M1-M2 shows that sidewalls 230 are formed on the sidewalls of the first fin 205, the second fin 206, the third fin 203, and the fourth fin 204.

[0080] It should be noted that, for ease of understanding, Figure 11 The fin mask layer 211 is not shown in the figure.

[0081] In this embodiment, the method for forming the sidewall 230 includes: depositing a sidewall material film (not shown) on the surface of the first dielectric layer 220, the surface of the first fin 205, the surface of the second fin 206, the surface of the third fin 203, the surface of the fourth fin 204, and the surface of the fin mask layer 211; and using an anisotropic etching process to etch the sidewall material film in a direction perpendicular to the surface of the substrate 200 until the top surface of the fin mask layer 211 and the surface of the first dielectric layer 220 are exposed.

[0082] The process for depositing the sidewall material film includes chemical vapor deposition, atomic layer deposition, etc.

[0083] Preferably, the sidewall material film is formed using atomic layer deposition (ALD). ALD is chosen because it can form a thin, dense sidewall material film with uniform thickness, and it offers high process precision. Therefore, the thickness of the sidewall material film can be better controlled, ensuring that the thickness W1 of the formed sidewall 230 meets the design dimensions. Furthermore, the sidewall 230 exhibits uniform thickness, high dimensional accuracy, and a dense structure. This further improves the dimensional accuracy and morphology of the subsequently formed power rail openings, resulting in a more reliable and high-performance embedded power rail.

[0084] In this embodiment, the anisotropic etching process includes a dry etching process. Specifically, the dry etching process includes a plasma etching process.

[0085] In this embodiment, the thickness W1 of the sidewall 230 ranges from 3 nanometers to 10 nanometers.

[0086] If the thickness W1 is too small, there is a high risk that the sidewalls 230 will be worn down to the point of exposing the sidewalls of the first fin 205 and the second fin 206 during the subsequent etching process to form the power rail opening. This increases the risk of the subsequently formed buried power rail contacting the first fin 205 and the second fin 206, resulting in poor self-alignment of the etching through the sidewalls 230. If the thickness W1 is too large, the width of the formed power rail opening will be smaller, resulting in a smaller width of the subsequently formed buried power rail. This is not conducive to reducing contact resistance and leads to a poorer performance improvement of the semiconductor structure. Therefore, choosing a suitable thickness W1, i.e., when the thickness W1 is between 3 nanometers and 10 nanometers, on the one hand, better self-aligned etching is achieved, and on the other hand, the performance improvement of the semiconductor structure is better.

[0087] In this embodiment, the sidewall 230 is made of the same material as the fin mask layer 211, so that the sidewall 230 and the fin mask layer 211 can be removed in the same step, thereby simplifying the manufacturing process.

[0088] In this embodiment, the material of the sidewall 230 includes silicon nitride.

[0089] Please refer to Figures 13 to 15 , Figure 13 yes Figure 14 and Figure 15 A top view of the structure along the central direction M. Figure 14 yes Figure 13 A schematic diagram of the cross-sectional structure along the M1-M2 direction. Figure 15 yes Figure 13A cross-sectional structural diagram along the M3-M4 direction is shown. After the sidewall 230 is formed, a first patterned layer 240 is formed on the substrate 200. The top surface of the first patterned layer 240 is higher than the top surfaces of the first fin 205 and the second fin 206. The first patterned layer 240 has a first opening 241 that exposes the power rail region D.

[0090] It should be noted that, for ease of understanding, Figure 13 The fin mask layer 211 is not shown in the figure.

[0091] In this embodiment, the process of forming the first patterned layer 240 includes an exposure process and a development process.

[0092] In this embodiment, the material of the first patterning layer 240 includes photoresist.

[0093] In this embodiment, the first patterned layer 240 further includes a second opening 242 and a third opening 243, the bottoms of which expose the surface of the first dielectric layer 220. The second opening 242, the first opening 241, and the third opening 243 are arranged along the second direction X. The third fin 203 (e.g. Figure 11 The projection of the fourth fin 204 (as shown) onto the surface of the substrate 200 is located between the projection of the second opening 242 onto the surface of the substrate 200 and the projection of the first opening 241 onto the surface of the substrate 200. Figure 11 The projection of the first opening 241 onto the surface of the substrate 200 (as shown) is located between the projection of the first opening 241 onto the surface of the substrate 200 and the projection of the third opening 243 onto the surface of the substrate 200.

[0094] The second opening 242 is used to form a second embedded power rail, and the third opening 243 is used to form a third embedded power rail.

[0095] Please continue to refer to this. Figures 13 to 15 The substrate 200 is etched using the first patterning layer 240 as a mask to form a power rail opening 251 within the substrate 200.

[0096] The power rail opening 251 provides space for the subsequent formation of a buried power rail.

[0097] In this embodiment, the process of etching the substrate 200 using the first patterned layer 240 as a mask includes at least one of dry etching and wet etching.

[0098] Preferably, a dry etching process is used to etch the substrate 200 using the first patterned layer 240 as a mask. Specifically, the dry etching process includes anisotropic plasma etching.

[0099] In this embodiment, during the etching process of the substrate 200 using the first patterned layer 240 as a mask, the etching selectivity ratio of the substrate 200 to the sidewall 230 is greater than 5:1. Therefore, by using a larger etching selectivity ratio, the loss of the sidewall 230 is reduced, and the morphology of the power rail opening 251 is improved.

[0100] In this embodiment, the substrate 200 is etched using the first patterning layer 240 as a mask. While forming a power rail opening 251 in the substrate 200, a second power rail opening (not shown) is also formed in the substrate 200 below the second opening 242, and a third power rail opening (not shown) is formed in the substrate 200 below the third opening 243.

[0101] Specifically, the second power rail opening provides space for forming the second embedded power rail. The third power rail opening provides space for forming the third embedded power rail.

[0102] In this embodiment, before etching the substrate 200 using the first patterned layer 240 as a mask, the first dielectric layer 220 is also etched using the first patterned layer 240 as a mask until the surface of the substrate 200 is exposed, and a first extended opening 252 is formed in the first dielectric layer 220. The first extended opening 252 is connected to the power rail opening 251.

[0103] In this embodiment, the first extension opening 252 provides partial space for the subsequent formation of the buried power rail, that is, a portion of the buried power rail extends into the first extension opening 252.

[0104] In other embodiments, the buried power rail is not located within the first extended opening, which only provides space for forming a second dielectric layer covering the top surface of the buried power rail.

[0105] In this embodiment, the first dielectric layer 220 is etched using the first patterning layer 240 as a mask to form the first extended opening 252. At the same time, a second extended opening (not shown) is also formed in the first dielectric layer 220 below the second opening 242, and a third extended opening (not shown) is formed in the first dielectric layer 220 below the third opening 243. The second extended opening is connected to the second power rail opening, and the third extended opening is connected to the third power rail opening.

[0106] In this embodiment, the second extension opening provides partial space for the subsequent formation of the second embedded power rail; that is, a portion of the second embedded power rail extends into the second extension opening. The third extension opening provides partial space for the subsequent formation of the third embedded power rail; that is, a portion of the third embedded power rail extends into the third extension opening.

[0107] In other embodiments, the second embedded power rail is not located within the second extended opening, which only provides space for forming a second dielectric layer covering the top surface of the second embedded power rail.

[0108] In other embodiments, the third embedded power rail is not located within the third extended opening, which only provides space for forming a second dielectric layer covering the top surface of the third embedded power rail.

[0109] Please refer to Figures 16 to 18 , Figure 16 yes Figure 17 and Figure 18 A top view of the structure along the central direction M. Figure 17 yes Figure 16 A schematic diagram of the cross-sectional structure along the M1-M2 direction. Figure 18 yes Figure 16 A cross-sectional structural diagram along the direction M3-M4 shows an isolation membrane 261 formed on the inner wall surface of the power rail opening 251.

[0110] The function of the isolation membrane 261 is to provide electrical insulation between the substrate 200 and the subsequently formed buried power rail sidewalls and bottom surfaces.

[0111] In this embodiment, the isolation membrane 261 is also formed on the inner wall surface of the first extended opening 252.

[0112] In this embodiment, the isolation membrane 261 is also formed on the inner wall surface of the second power rail opening, the third power rail opening, the second extension opening, and the third extension opening.

[0113] In this embodiment, the material of the separator 261 is a dielectric material. The dielectric material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide.

[0114] Specifically, the material of the isolation membrane 261 in this embodiment includes silicon nitride.

[0115] In this embodiment, the process for forming the isolation membrane 261 includes chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Preferably, ALD is used to form the isolation membrane 261.

[0116] Please continue to refer to this. Figures 16 to 18 After the isolation membrane 261 is formed, a buried power rail 260 is formed in the power rail opening 251.

[0117] In the second direction X, the width T2 of the buried power rail 260 in the first region I is greater than the width T1 of the buried power rail 260 in the second region II.

[0118] Since sidewalls are formed on the sidewalls of the first fin 205 and the second fin 206 after their formation, when etching the substrate using the first patterning layer 240 as a mask, a gap can be formed between the sidewall of the power rail opening 251 and the sidewalls of the first fin 205 and the second fin 206 in a direction perpendicular to the sidewall of the power rail opening 251, thereby achieving self-aligned etching. Therefore, not only can the pattern transfer of the buried power rail 260 be achieved with a larger first opening 241, but also, through the regular shape (rectangular) of the first opening 241, buried power rails 260 with different widths (width T2 and width T1) can be formed in the first region I and the second region II, increasing the width of the buried power rail 260 in the first region I. This increases the process window of the first patterning layer 210 while forming a buried power rail 260 with lower parasitic resistance, improving the performance of the semiconductor structure.

[0119] Furthermore, since the width of the buried power rail 260 in the first region I has been increased, a larger first conductive structure can be formed subsequently. Moreover, the requirements for the position and size accuracy of the first conductive structure are reduced when forming the first conductive structure. This not only increases the process window for forming the first conductive structure, but also reduces the contact resistance between the first conductive structure and the buried power rail 260 in the first region I, thereby improving the performance of the semiconductor structure.

[0120] In this embodiment, in the second direction X, the width T3 of the buried power rail 260 in the third region III is also greater than the width T1 of the buried power rail 260 in the second region II.

[0121] As a result, the width of the buried power rail 260 in the third region III is also increased, thereby further increasing the process window of the first patterning layer 210 and further forming a buried power rail 260 with lower parasitic resistance, thus improving the performance of the semiconductor structure.

[0122] Furthermore, by increasing the width of the buried power rail 260 in the third region III, a larger second conductive structure can be formed subsequently. Moreover, the requirements for the positional and dimensional accuracy of the second conductive structure are reduced during its formation. This not only increases the process window for forming the second conductive structure but also reduces the contact resistance between the second conductive structure and the buried power rail 260 in the third region I, thereby further improving the performance of the semiconductor structure.

[0123] In this embodiment, the embedded power rail 260 is also formed within the first extended opening 252, and the surface of the embedded power rail 260 is lower than the top surface of the first dielectric layer 220.

[0124] In other embodiments, the surface of the buried power rail is flush with the surface of the substrate.

[0125] In this embodiment, the process for forming the buried power rail 260 includes metal electroplating, chemical vapor deposition, etc.

[0126] In this embodiment, the material of the buried power rail 260 includes at least one of rubidium, tungsten, and cobalt.

[0127] In this embodiment, after the embedded power rail 260 is formed, a second dielectric layer 270 is formed within the first extended opening 252.

[0128] Specifically, the material of the second dielectric layer 270 includes silicon oxide.

[0129] Since the second dielectric layer 270 is formed before the first patterning layer 240 and sidewall 230 are subsequently removed, the second dielectric layer 270 can protect the surface of the buried power rail 260 during the removal of the first patterning layer 240 and sidewall 230, reduce the damage to the surface of the buried power rail 260, and thus better improve the performance and reliability of the semiconductor structure.

[0130] It should be noted that, for ease of understanding, Figure 16 The second dielectric layer 270 is not shown in the figure.

[0131] In this embodiment, after the second dielectric layer 270 is formed, the first patterned layer 240 is removed; after the first patterned layer 240 is removed, the sidewall 230 and the fin mask layer 211 are removed.

[0132] In this embodiment, the process of removing the first patterned layer 240 includes an ashing process, etc.

[0133] In this embodiment, the process for removing the sidewall 230 and the fin mask layer 211 includes at least one of dry etching and wet etching.

[0134] In this embodiment, while a buried power rail 260 is formed in the power rail opening 251 and a portion of the first extension opening 252, a second buried power rail 262 is formed in the second power rail opening and a portion of the second extension opening, and a third buried power rail 263 is formed in the third power rail opening and a portion of the third extension opening, and the second dielectric layer 270 is also located in the second extension opening and the third extension opening.

[0135] Please refer to Figures 19 to 21 , Figure 19 yes Figure 20 A top view of the structure along the central direction M. Figure 20 yes Figure 19 A schematic diagram of the cross-sectional structure along the M3-M4 direction, 22 is... Figure 19 A cross-sectional structural diagram along the direction M5-M6 shows that after removing the sidewall 230, a first source / drain opening (not shown) is formed in the first fin 205 on the first region I; a first source / drain structure 281 is formed in the first source / drain opening; after removing the sidewall 230, a second source / drain opening (not shown) is also formed in the second fin 206 on the third region III; a second source / drain structure 282 is formed in the second source / drain opening.

[0136] In this embodiment, the method for forming the semiconductor structure further includes: forming a first gate 301, a second gate 302, a third gate 303, a fourth gate 304, and an interlayer dielectric layer 310 on the surface of the first dielectric layer 220 before subsequently forming the first conductive structure and the second conductive structure.

[0137] The first gate 301 spans the first fin 205, the second fin 206, and the third fin 203 of the second region II; the second gate 302 spans the fourth fin 204; the third gate 303 spans the third fin 203; and the fourth gate 304 spans the first fin 205, the second fin 206, and the fourth fin 204 of the second region II.

[0138] The interlayer dielectric layer 310 is located on the surfaces of the first source / drain structure 281, the second source / drain structure 282, and the exposed first fin 205, second fin 206, third fin 203, and fourth fin 204. The interlayer dielectric layer 310 is also located on the surfaces of the first gate 301, second gate 302, third gate 303, and fourth gate 304. The surface of the interlayer dielectric layer 310 is higher than the top surfaces of the first gate 301, second gate 302, third gate 303, and fourth gate 304.

[0139] The material of the interlayer dielectric layer 310 is a dielectric material. The dielectric material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0140] Preferably, the material of the interlayer dielectric layer 310 includes silicon oxide.

[0141] It should be noted that, for ease of understanding, Figure 19 The interlayer dielectric layer 310 is not shown in the figure.

[0142] Please continue to refer to this. Figures 19 to 21 After forming the first source-drain structure 281 and the second source-drain structure 282, a first conductive structure 291 is formed on the first region I, and a second conductive structure 292 is formed on the second region II. The first conductive structure 291 is in contact with the top surface of the first source-drain structure 281 and the top surface of the buried power rail 260 in the first region I. The second conductive structure 292 is in contact with the top surface of the second source-drain structure 282 and the top surface of the buried power rail 260 in the third region III.

[0143] In this embodiment, the method for forming the first conductive structure 291 and the second conductive structure 292 includes: forming a conductive structure mask layer (not shown) on the surface of the interlayer dielectric layer 310, the conductive structure mask layer exposing portions of the surface of the interlayer dielectric layer 310 in the first region I and the third region III; using the conductive structure mask layer as a mask, etching the exposed interlayer dielectric layer 310 and the second dielectric layer 270 until the top surfaces of the first source / drain structure 281, the second source / drain structure 282, the top surface of the buried power rail 260 in the first region I, and the top surface of the buried power rail 260 in the third region III are exposed, to form the first conductive opening (not shown) and the second conductive opening (not shown). The bottom of the first conductive opening exposes the top surface of the first source / drain structure 281 and the top surface of the buried power rail 260 in the first region I. The bottom of the second conductive opening exposes the top surface of the second source / drain structure 282 and the top surface of the buried power rail 260 in the third region III. A conductive material layer (not shown) is formed in the first conductive opening, the second conductive opening, and on the surface of the interlayer dielectric layer 310. The surface of the conductive material layer is higher than the surface of the interlayer dielectric layer 310. The conductive material layer is planarized until the surface of the interlayer dielectric layer 310 is exposed. The first conductive structure 291 is formed in the first conductive opening, and the second conductive structure 292 is formed in the second conductive opening.

[0144] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figures 19 to 21The system includes: a substrate 200, the substrate 200 including a power rail region D, the power rail region D including a first region I and a second region II arranged along a first direction Y, the power rail region D having a first fin 205 and a second fin 206 arranged along a second direction X, the first fin 205 and the second fin 206 spanning the second region II, the second direction X being perpendicular to the first direction Y; and a buried power rail 260 located within the power rail region D, the buried power rail 260 of the second region II being located within the substrate 200 between the first fin 205 and the second fin 206, and, in the second direction X, the width T2 of the buried power rail 260 of the first region I (e.g., ...) Figure 16 (As shown) is greater than the width T1 of the buried power rail 260 in Zone II (as shown) Figure 16 (as shown); the isolation membrane 261 is located between the buried power rail 260 and the substrate 200.

[0145] The substrate 200 is made of semiconductor material.

[0146] In this embodiment, the substrate 200 is made of silicon.

[0147] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0148] In this embodiment, the power rail region D further includes a third region III, and the first region I, the second region II and the third region III are arranged along the first direction Y.

[0149] Specifically, the first fin 205 is located on the first region I and the second region II, and the second fin 206 is located on the second region II and the third region III.

[0150] In this embodiment, in the second direction X, the width T3 of the buried power rail 260 in the third region III is also greater than the width T1 of the buried power rail 260 in the second region II.

[0151] In other embodiments, the power rail region includes a first region and a second region arranged along a first direction. Both the first fin and the second fin are located on the second region, and one of the first fin and the second fin is also located on the first region.

[0152] In this embodiment, the material of the buried power rail 260 includes at least one of rubidium, tungsten, and cobalt.

[0153] In this embodiment, the material of the insulating film 261 is a dielectric material. The dielectric material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide.

[0154] Specifically, the material of the isolation membrane 261 in this embodiment includes silicon nitride.

[0155] In this embodiment, the substrate 200 also has a third fin 203 and a fourth fin 204. The third fin 203 and the fourth fin 204 are respectively located on the substrate 200 on both sides of the power rail region D.

[0156] In this embodiment, the semiconductor structure further includes a first dielectric layer 220 located on the surface of the substrate 200. The first dielectric layer 220 is also located on the sidewalls of the first fin 205, the second fin 206, the third fin 203, and the fourth fin 204. The surface of the first dielectric layer 220 is lower than the top surface of the first fin 205, the second fin 206, the third fin 203, and the fourth fin 204.

[0157] The material of the first dielectric layer 220 is a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0158] Preferably, the material of the first dielectric layer 220 includes silicon oxide.

[0159] In this embodiment, the embedded power rail 260 extends upward into the first dielectric layer 220, and the isolation membrane 261 is located between the sidewall of the embedded power rail 260 and the first dielectric layer 220. The surface of the embedded power rail 260 is lower than the top surface of the first dielectric layer 220.

[0160] In other embodiments, the surface of the buried power rail is flush with the surface of the substrate.

[0161] In this embodiment, the semiconductor structure further includes a second dielectric layer 270 located on the top surface of the buried power rail 260, and the second dielectric layer 270 is also located within the first dielectric layer 220.

[0162] In this embodiment, the material of the second dielectric layer 270 includes silicon oxide.

[0163] In this embodiment, the semiconductor structure further includes: a first source / drain opening (not shown) located within a first fin 205 on the first region I; a first source / drain structure 281 located within the first source / drain opening; and a first conductive structure 291 located on the first region I, wherein the first conductive structure 291 is in contact with the top surface of the first source / drain structure 281 and the top surface of the buried power rail 260 of the first region I.

[0164] In this embodiment, the semiconductor structure further includes: a second source / drain opening (not shown) within the second fin 206 on the third region III; a second source / drain structure 282 within the second source / drain opening; and a second conductive structure 292 on the third region III, wherein the second conductive structure 292 contacts the top surface of the second source / drain structure 282 and the top surface of the buried power rail 260 of the third region III.

[0165] In this embodiment, the semiconductor structure further includes a first gate 301, a second gate 302, a third gate 303, a fourth gate 304, and an interlayer dielectric layer 310 located on the surface of the first dielectric layer 220.

[0166] The first gate 301 spans the first fin 205, the second fin 206, and the third fin 203 of the second region II; the second gate 302 spans the fourth fin 204; the third gate 303 spans the third fin 203; and the fourth gate 304 spans the first fin 205, the second fin 206, and the fourth fin 204 of the second region II.

[0167] The interlayer dielectric layer 310 is located on the surfaces of the first source / drain structure 281, the second source / drain structure 282, and the exposed first fin 205, second fin 206, third fin 203, and fourth fin 204. The interlayer dielectric layer 310 is also located on the surfaces of the first gate 301, second gate 302, third gate 303, and fourth gate 304. The surface of the interlayer dielectric layer 310 is higher than the top surfaces of the first gate 301, second gate 302, third gate 303, and fourth gate 304.

[0168] In this embodiment, the interlayer dielectric layer 310 is also located on the sidewalls of the first conductive structure 291 and the second conductive structure 292, and the interlayer dielectric layer 310 exposes the top surfaces of the first conductive structure 291 and the second conductive structure 292.

[0169] The material of the interlayer dielectric layer 310 is a dielectric material. The dielectric material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0170] Preferably, the material of the interlayer dielectric layer 310 includes silicon oxide.

[0171] In this embodiment, the semiconductor structure further includes a second buried power rail 262 and a third buried power rail 263 located within the substrate 200.

[0172] Specifically, the second buried power rail 262, the buried power rail 260, and the third buried power rail 263 are arranged along the second direction X. The projection of the third fin 203 onto the surface of the substrate 200 is located between the projections of the second buried power rail 262 onto the surface of the substrate 200 and the projections of the buried power rail 260 onto the surface of the substrate 200. The projection of the fourth fin 204 onto the surface of the substrate 200 is located between the projections of the buried power rail 260 onto the surface of the substrate 200 and the projections of the third buried power rail 263 onto the surface of the substrate 200.

[0173] In this embodiment, both the second buried power rail 262 and the third buried power rail 263 are used to connect to the common ground terminal VSS, and the buried power rail 263 is used to connect to the working voltage VDD.

[0174] In this embodiment, the second dielectric layer 270 is also located on the top surface of the second buried power rail 262 and the third buried power rail 263.

[0175] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a power rail region, the power rail region including a first region, a second region and a third region arranged along a first direction; The first fin is located only in the first and second regions, and the second fin is located only in the second and third regions. The first and second fins are arranged along a second direction, which is perpendicular to the first direction. The buried power rails are located within the power rail area, and the buried power rails of the second area are located within the substrate between the first fin and the second fin. Furthermore, in the second direction, the width of the buried power rails of the first area and the third area is greater than the width of the buried power rail of the second area. An isolation membrane located between the buried power rail and the substrate; A first dielectric layer is located on the surface of the substrate, the surface of the first dielectric layer being lower than the top surfaces of the first fin and the second fin; a first extended opening is formed within the first dielectric layer; the buried power rail is also formed within the first extended opening.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The isolation membrane is also located between the sidewall of the embedded power rail and the first dielectric layer, and the surface of the embedded power rail is lower than the top surface of the first dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, Also includes: A second dielectric layer is located on the top surface of the buried power rail, and the second dielectric layer is also located within the first dielectric layer.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first source drain opening is located within the first fin on the first region; The first source-drain structure located within the first source-drain opening; A first conductive structure located on the first region, the first conductive structure being in contact with the top surface of the first source / drain structure and the top surface of the buried power rail of the first region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: The second source drain opening is located within the second fin on the third region; The second source-drain structure located within the second source-drain opening; A second conductive structure located on the third region, the second conductive structure being in contact with the top surface of the second source / drain structure and the top surface of the buried power rail in the third region.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is formed, the substrate including a power rail region, the power rail region including a first region and a second region arranged along a first direction, the power rail region having a first fin and a second fin arranged along a second direction, the first fin and the second fin crossing the second region, the second direction being perpendicular to the first direction; After the first fin and the second fin are formed, sidewalls are formed on the sidewall surfaces of the first fin and the second fin; After sidewalls are formed on the sidewalls of the first fin and the second fin, a first patterned layer is formed on the substrate. The top surface of the first patterned layer is higher than the top surface of the first fin and the second fin. The first patterned layer has a first opening that exposes the power rail region. The substrate is etched using the first patterned layer as a mask to form a power rail opening in the substrate; An isolation membrane is formed on the inner wall surface of the power rail opening; After the isolation membrane is formed, a buried power rail is formed in the power rail opening. In the second direction, the width of the buried power rail in the first region is greater than the width of the buried power rail in the second region. Before forming the sidewalls, a first dielectric layer is formed on the substrate surface, the surface of the first dielectric layer being lower than the top surfaces of the first and second fins; before etching the substrate using the first patterned layer as a mask, the first dielectric layer is also etched using the first patterned layer as a mask until the substrate surface is exposed, forming a first extended opening in the first dielectric layer; the buried power rail is also formed in the first extended opening.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first extended opening communicates with the power rail opening, and the isolation membrane is also formed on the inner wall surface of the first extended opening. The surface of the embedded power rail is lower than the top surface of the first dielectric layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: After the embedded power rail is formed, a second dielectric layer is formed within the first extended opening.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The top surfaces of the first and second fins also have fin masking layers.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the sidewall includes: using an atomic layer deposition process to form a sidewall material film on the surface of the first dielectric layer, the surface of the first fin and the second fin, and the surface of the fin mask layer; and using an anisotropic etching process to etch the sidewall material film until the top surface of the fin mask layer and the surface of the first dielectric layer are exposed.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: After the embedded power rails are formed, the first patterning layer is removed; After removing the first graphical layer, remove the sidewalls.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process for removing the sidewalls includes at least one of dry etching and wet etching.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, Also includes: After removing the sidewall, a first source / drain opening is formed within the first fin in the first region; a first source / drain structure is formed within the first source / drain opening. After the first source-drain structure is formed, a first conductive structure is formed on the first region, and the first conductive structure is in contact with the top surface of the first source-drain structure and the top surface of the buried power rail in the first region.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The power rail area also includes a third area. The first area, the second area and the third area are arranged along a first direction. The first fin is located on the first area and the second area, and the second fin is located on the second area and the third area. The width of the embedded power rail in the third area is also greater than the width of the embedded power rail in the second area.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Also includes: After the sidewall is removed, a second source drain opening is formed in the second fin on the third region; A second source-drain structure is formed within the second source-drain opening; After the second source-drain structure is formed, a second conductive structure is formed on the third region, and the second conductive structure is in contact with the top surface of the second source-drain structure and the top surface of the buried power rail in the third region.

16. The method for forming a semiconductor structure as described in claim 6, characterized in that, The power rail area also includes a third area. The first area, the second area and the third area are arranged along a first direction. The first fin is located on the first area and the second area, and the second fin is located on the second area and the third area.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method of forming the first fin and the second fin includes: forming an initial first fin and an initial second fin arranged along a second direction on a substrate, the initial first fin and the initial second fin spanning a first region, a second region and a third region; removing the initial first fin in the third region and the initial second fin in the first region to form the first fin and the second fin.

18. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the sidewall ranges from 3 nanometers to 10 nanometers.

19. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the buried power rail includes at least one of rubidium, tungsten, and cobalt.

20. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the first patterning layer includes photoresist.

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