Memory device with low pin count interface and corresponding method and system

Abstract

A method may include, in an integrated circuit device: receiving a sequence of no less than three command value portions at a unidirectional command address (CA) bus having no more than four parallel inputs; latching each command value portion synchronously with a rising edge of a timing clock; determining an input command based on the sequence of no less than three command value portions; executing the input command in the integrated circuit device; outputting and inputting a sequence of data values ​​synchronously with rising and falling edges of a timing clock on a bidirectional data bus having no more than six data input / outputs (IOs). Corresponding devices and systems are also disclosed.

Description

Technical Field

[0001] The present disclosure relates generally to memory device interfaces, and more particularly to memory device interfaces having low pin counts and high data transfer rates. Background Art

[0002] Memory devices remain a critical component in most electronic systems. In terms of system performance, memory device data rate can be a limiting factor. In terms of system power consumption, any reduction in memory device power consumption is desirable. At the same time, for many systems, such as, for example, automobiles, it is desirable to keep the system bus size to a minimum. Therefore, low pin count memory devices are widely used in such systems.

[0003] 32A and 32B are diagrams showing conventional memory device types and performance. FIG. 32A shows a schematic diagram of a memory device that is compatible with the HyperBus 4000 released by Infineon Technologies Corp. and Cypress Semiconductor Corp. TM Example of a specification-compliant memory device 3201A. The memory device 3201A can provide a high-performance solution. In some configurations, the memory device 3201A can operate at a clock speed of approximately 200 MHz, providing data on both the rising and falling edges of the clock signal (i.e., double data rate, DDR). The device 3201A can include low voltage CMOS (LVCMOS) signaling. The memory device 3201A can be a non-volatile memory device (e.g., NOR flash) or a volatile memory (e.g., hidden refresh DRAM).

[0004] FIG32B shows a memory device 3201B compatible with the low power DDR4 (LPDDR4) standard JESD209-4D promulgated by the Joint Electron Device Engineering Council (JEDEC). Memory device 3201B is a synchronous DRAM (SDRAM) that can provide high performance while using a relatively high pin count. Memory device 3201B can have a differential clock input (CK_1 / CK_c) and a differential data strobe (DS_t / DS_c). Although FIG32B shows a device with x8 data input / output (IO), other LPDDR4 SDRAMs can have larger IOs (i.e., x16). Memory device 3201B can run at clock speeds starting at approximately 800 MHz and utilize low voltage swing termination logic (LVSTL) signaling.

[0005] 32C is a timing diagram illustrating command processing operations of a conventional LPDDR4 device, such as that shown in FIG32B. In response to an active (high) chip select (CS) signal, the device may latch the first six-bit portion of the command at the rising edge of the clock signal (CK), and then latch the second six-bit portion of the command at the next rising edge of the clock signal (CS is inactive).

[0006] While providing the desired high-speed signaling, the large pin count of conventional approaches makes them unsuitable for low pin count applications. Additionally, the volatile storage of LPPDR4 SDRAM makes them unsuitable for many applications, such as storage of firmware in a system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1D is a diagram showing a memory device pinout according to an embodiment.

[0008] Figure 2 is a timing chart illustrating a command input operation according to an embodiment.

[0009] Figure 3A and Figure 3B is a timing diagram comparing a read operation according to a conventional operation and an operation according to an embodiment.

[0010] Figure 4 is a table showing pin types and functions of a memory device according to an embodiment.

[0011] FIG. 5A to FIG. 5C is a timing diagram comparing conventional error correction code (ECC) data transmission with data transmission of the embodiment.

[0012] FIG. 6A to FIG. 6C is a timing diagram illustrating a command bus training operation of a memory device according to an embodiment.

[0013] Figure 7 is a timing diagram illustrating a write leveling operation of a memory device according to an embodiment.

[0014] Fig. 8A and Figure 8B is a diagram illustrating a read data bus calibration operation according to an embodiment.

[0015] Fig. 9A and Fig. 9B is a timing diagram illustrating a data strobe-data bus training operation according to an embodiment.

[0016] Fig. 10A and Fig. 10B is a timing diagram illustrating the operation of a data strobe interval oscillator according to an embodiment.

[0017] Fig.11 is a timing diagram illustrating a read leader training operation according to an embodiment.

[0018] Fig. 12A and Fig. 12B is a timing diagram illustrating a reference voltage training operation according to an embodiment.

[0019] Fig.13 is a block diagram of a memory device according to an embodiment.

[0020] Fig.14 is a block diagram of a memory device according to another embodiment.

[0021] Fig.15 is a block diagram of an interface circuit according to an embodiment.

[0022] FIG. 16A to FIG. 16E is a diagram of various interface circuits according to an embodiment.

[0023] Fig.17A and Fig. 17B is a diagram of a memory cell array that may be included in an embodiment.

[0024] Fig.18 is a block diagram of a memory device according to another embodiment.

[0025] Fig.19 is a block diagram of a system according to an embodiment.

[0026] Fig. 20 is a block diagram of a system according to another embodiment.

[0027] Fig.21 is a block diagram of a memory controller according to an embodiment.

[0028] Fig.22A and Fig. 22B is a diagram of a memory controller circuit according to an embodiment.

[0029] Fig.23 is a diagram of an integrated circuit device according to an embodiment.

[0030] Fig.24 is a diagram of an automotive system according to an embodiment.

[0031] Fig.25 is a flowchart of a method of operating a memory device according to an embodiment.

[0032] Fig.26 is a flowchart of a method of providing error correction code data according to an embodiment.

[0033] Fig. 27 is a flow chart of a method of training a memory device according to an embodiment.

[0034] Fig.28 is a flowchart of a method of indicating a data output portion using a data mask inversion (DMI) signal according to an embodiment.

[0035] Fig.29 is a flow chart of a method for indicating a data bus configuration using a DMI signal according to an embodiment.

[0036] Figure 30A to Fig. 30C is a graph comparing the performance of a memory device according to an embodiment with the performance of a conventional memory device.

[0037] Fig.31 is a diagram showing an application of a memory device according to an embodiment.

[0038] 32A to 32C are diagrams illustrating conventional memory devices, performance, and operations. DETAILED DESCRIPTION

[0039] According to an embodiment, a memory device can provide high-speed signaling with a relatively low pin count. Command and address data can be received on a relatively small size command address (CA) bus, with commands received in multiple parts, received on three or more consecutive edges (e.g., rising edges) of a timing clock. Data for the memory device can be received and sent at a double data rate (DDR) on a relatively small data bus, resulting in receiving / sending data bytes on more than two consecutive rising and falling edges of the timing clock.

[0040] In some embodiments, the CA bus may be three bits and receive a 12-bit command as four consecutive 3-bit command portions.

[0041] In some embodiments, the data bus may be four bits, and DDR data may be sent and received in four-bit nibbles.

[0042] In some embodiments, a memory device may include a data mask inversion (DMI) input / output (IO). As data is transmitted on a data bus, the DMI IO may send both inverted data and / or error correction code (ECC) data in the same clock cycle. In some embodiments, as data is transmitted in portions on the data bus, the DMI IO may indicate more significant bits and less significant bits of the data portion.

[0043] In some embodiments, in calibration mode, the memory device may receive calibration setting data on both the CA bus and the data bus simultaneously. In some embodiments, the calibration setting data may be a reference voltage setting used in a CA bus training operation and / or a data bus training operation.

[0044] In some embodiments, the memory device may be a non-volatile memory device that provides high-speed signaling at a low pin count.

[0045] Figure 1AIt is a block diagram of a memory device 100A according to an embodiment. The memory device 100A can provide a relatively low pin count while providing relatively high-speed signaling. The main signaling pins for the memory device 100A may include a chip select (CS) input, a clock (CK) input, a clock enable (CKE) input, a command address (CA) input, a data strobe (DQS) IO, a data mask inversion (DMI) IO, and a data IO (DQ). A CA input may include no more than five inputs, and a DQ IO may include no more than six IOs. In some embodiments, the remaining inputs and IOs may be single. Therefore, the device 100A may have a total pin count of no more than 16 (excluding dedicated pins). According to an embodiment, the memory device 100A may store data in a non-volatile memory cell, a volatile memory cell, or a combination thereof.

[0046] Figure 1B is a block diagram of a memory device 100B according to another embodiment. The memory device 100B may be Figure 1A However, the memory device 100B may include a device similar to Figure 1A The CA input may be 3 bits and the DQ IO may be 4 bits. In such an arrangement, the memory device 100B may have a relatively low pin count of 12 pins.

[0047] Figure 1C is a block diagram of a memory device 100C according to another embodiment. The memory device 100C may be Figure 1A However, the memory device 100C may include a device similar to Figure 1B In the example of the project, the clock input may include a complementary clock input (CK / CKB). In addition, the data strobe IO may be complementary (DQS / DQSB). In such an arrangement, the memory device 100B may have a relatively low pin count of 14 pins.

[0048] Figure 1D is a block diagram of a memory device 100D according to another embodiment. The memory device 100C may be Figure 1A The memory device 100C may include a memory device similar to Figure 1B The project of the project can be a dual channel device, providing two different interfaces. Other embodiments may include a greater number of low pin count interfaces.

[0049] Figure 2 is a timing chart illustrating a command input operation according to an embodiment. Figure 2 The waveforms of the clock input CK, chip select input CS, and command address input CA[2:0] are shown.

[0050] At time t0, CK can transition high. At the same time, CS can be high, activating the device. On the CA bus, the three-bit portion (CMD[11:9]) of the 12-bit command (CMD1) can be received.

[0051] At time t1, CS may return low. In the following three high transitions of the clock signal, the remaining 3-bit portion of the command (CMD[8:6], CMD[5:3] CMD[2:0]) may be received. Figure 2 A second command (CMD2) is shown being received immediately after the first command.

[0052] Figure 3A and Figure 3B is a timing diagram comparing conventional read access operations compatible with the LPDDR4 standard with those according to an embodiment. Figure 3A is a timing diagram showing the CK and CS inputs, the six-bit CA[5:0] inputs, the DQS IO, and the 8-bit DQ[7:0] IO.

[0053] At time t0, at the rising edge of CK, CS can be high and the first six bits of the first activation command (ACT1) can be received. Then CS can return to low. At the next rising edge of the CK signal, the last six bits of ACT1 can be received. At time t1, the second activation command (ACT2) can be received.

[0054] At time t3, after the activate command (ACT1 / ACT2), a read command pair (READ / CAS2) may be input. The CAS2 command must be completed after the RAS to CAS delay (tRCD) after the last 6 bits of ACT2, shown from time t2 to t5.

[0055] At time t6, after the read wait time (RL) after the last part of the CAS2 command, the data select signal (DQS) can be activated to enable the output of the data. At time t7, DQS can be activated for the leading time tRPRE. At time t8, DQS can begin to convert synchronously with CK, and data can be output on DQ[7:0] at a double data rate timed with DQS. 8 bits can be output per half clock cycle, for a total of 8 clock cycles (shown as D0 to D15). After the output of the read data, DQS can remain activated during the post-synchronization code period (tRPST).

[0056] Figure 3B Is displayed corresponding to Figure 3A The timing diagram of the read operation is similar to that of the Figure 1B device of the device. Figure 3BWaveform with the same set of signals, but the CA input is 3 bits instead of 6 bits, and the DQ IO is 4 bits instead of 8 bits.

[0057] In some embodiments, Figure 3B A read operation can be performed with Figure 3A The same command, but receiving the command in more clock cycles, and outputting the read data in more clock cycles. In some embodiments, Figure 3B The read operation can be performed with Figure 3A Operate under the same timing constraints, including tRCD, RL, tDQSCK, tRPRE, and tRPST.

[0058] Still reference Figure 3B , at time t0, the reception of the ACT1 command is accompanied by CS activation on the rising edge of CK. However, only the 3-bit portion of the 12-bit command is received. As CS returns low, different 3-bit portions of ACT1 can be received on the next three rising edges of CK until all 12 bits are received.

[0059] At time t1 , an ACT2 command may be received, which is clocked in on four rising edges in the same manner as ACT1 .

[0060] READ and CAS2 commands can be received no earlier than tRCD time period, such as for Figure 3A As described, each such command may also be received in four 3-bit parts.

[0061] At time t8, the read data can be output in DDR fashion, but on a 4-bit data bus, over 16 clock cycles (shown as D0 to D31).

[0062] In this way, memory devices with low pin counts can execute commands compatible with existing standards. In some embodiments, the memory device can be compatible with the LPDDR4 standard, but with additional clock cycles for receiving command address values ​​and for inputting data values ​​in write operations and outputting data values ​​in read operations.

[0063] Figure 4 is a table showing interface connection (ie, pin) types and functions according to embodiments. The CS, CK, and CKE inputs may function in a conventional manner, with some embodiments including differential clocks (CK_t, CK_c).

[0064] The CA[2:0] bus may be a reduced size bus to achieve low pin count. Optionally, the CA[2:0] bus may receive calibration data, such as a portion of a reference voltage value, in a calibration mode. The functionality of the CA[2:0] bus may be established by a mode register setting.

[0065] DQS IO may be used as a data alignment signal synchronized with CK, and may optionally include differential signals (DQS_t, DQS_c).

[0066] The DMI IO can have any of a variety of functions, including providing a data mask value in a write operation, indicating data inversion, providing ECC data, and / or indicating the upper and lower nibbles of the same byte for data output on bus DQ[3:0]. The function of the DMI signal can be established by the mode register setting.

[0067] DQ[3:0] may be a reduced size data IO bus.

[0068] Figure 4 Also included are support inputs that may be included in embodiments. RESET_n and ODT(ca) may have conventional functions.

[0069] FIG. 5A to FIG. 5C is a timing diagram comparing conventional ECC data transfers with those according to one embodiment.

[0070] Figure 5A A conventional arrangement for providing "in-band" ECC data is shown. 64 bits of data are sent in 8 bursts on DQ[7:0]. The data transmission is DDR, and the 8 bits of data are sent synchronously with the rising and falling edges of the clock (CK_t). For each 8-bit data value, the DMI IO can indicate data inversion (e.g., DMI high) or no data inversion. After the data burst, 8 bits of ECC data (ECC7:0) corresponding to the 64 bits of data are provided on DQ[7:0]. That is, additional bus time is required to receive the ECC data.

[0071] Figure 5B shows a conventional arrangement for providing "out-of-band" ECC data. 64 bits of data are sent on DQ[7:0] as DMI values, with Figure 5A However, an ECC IO is also included, which enables one bit of ECC data to be sent with each data byte on DQ[7:0]. This arrangement requires a further increase in pin count.

[0072] Figure 5C The transmission of "in-band" ECC data according to an embodiment is shown. Figure 5CWaveforms of the timing clock CK, the reduced size data bus DQ[3:0], and the multifunction IO (DMI) are shown. 64 bits of data are sent in 16 bursts on DQ[3:0]. The data transmission is DDR, and 4 bits of data (i.e., half a byte) are sent synchronously with the rising and falling edges of the clock (CK). Within one clock cycle, the DMI signal can provide both a data mask inversion value (for two half bytes) and an ECC value. For example, the data mask inversion value DMI0 can indicate the data inversion of half bytes D3:0 and D7:4. Such an arrangement can allow ECC data to be sent in-band without the need for additional data bus time.

[0073] In some embodiments, the DMI signal indicates a data mask for a write operation. When the DMI signal has one value (e.g., high), the data value can be masked to prevent it from being written to the device. When the DMI signal has another value (e.g., low), the data can be written to the device. Figure 5C , in a data mask operation, there will be no ECC value. A high DMI value for nibble D3:0 will cause such a value to not be written. If the DMI signal is low in the subsequent half cycle (shown as ECC0), nibble D7:4 will be written.

[0074] Fig. 6A and Figure 6B is a timing diagram of a command bus training operation of a memory device according to one embodiment. Fig. 6A Waveforms including CK, CKE, CS, CA[2:0], DQS, DQ[3:0], and DMI, which may be as described herein, or an equivalent. Fig. 6A The following other waveforms are also included: Command, which describes the value entered on CA[2:0]; VrefCA, the state of the calibration reference voltage; and ODT of DQ, the on-chip termination state of the DQ bus. Figure 6B Included with Fig. 6A Same waveform, but showing DQ[2:0] and DQ[3] separately.

[0075] refer to Fig. 6A At time t0, the memory device may receive two 12-bit commands (e.g., mode register write commands, MRW-1 / MRW-2) that may place the memory device in command bus training mode. As described herein, each of these commands may be received in four 3-bit portions on consecutive rising edges of CK.

[0076] At time t1, a predetermined period of time before CKE transitions low, DQS may go low. At time t2, CKE may transition low. Subsequently, there may be an update of the frequency set point value (FSP) (shown in VrefCA), a switch between mode registers may begin (shown in ODT_CA), and a transition of the ODT setting of the data IO (shown in ODT of DQ[3:0]).

[0077] At time t3, a portion of the reference value Vref[3:0] may be driven on DQ[3:0] according to a predetermined timing. DMI may be low to indicate that the reference value portion includes lower (ie, less significant) bits of the Vref value.

[0078] At time t4, DQS_t may be strobed high to indicate the presence of the Vref[3:0] value on DQ[3:0]. In some embodiments, DQS_t may be strobed high more than once to ensure that the reference value is captured.

[0079] At time t5, a second portion of the reference value Vref[6:4] may be driven on DQ[3:0]. DMI may be driven high to indicate that the reference value portion includes the higher (i.e., more significant) bits of Vref. At time t6, DQS_t may be driven high one or more times to indicate the presence of the second reference value portion. In the illustrated embodiment, the reference value is seven bits, however alternative embodiments may include a greater or lesser number of bits, including a four-bit value that will not include a DMI transition.

[0080] At time t7, a calibration pattern (Pattern A) may be driven on CA[2:0].

[0081] Reference Figure 6B , at time t8, after applying the calibration pattern on CA[2:0], the pattern (Pattern A) received by the memory device can be provided on DQ[2:0]. In the embodiment shown, DQ[3] can be driven to a predetermined level (in this case, high) to indicate the presence of a captured pattern value. In an alternative embodiment, DMI can be used to indicate the presence of captured pattern data. At time t9, DQ[3] can return to the previous level (in this case, low).

[0082] In the illustrated embodiment, at time t10, a second calibration pattern (pattern B) may be applied to CA[3:0] and the calibration operation may continue.

[0083] Figure 6C FIG. 1 is a timing diagram of a command bus training operation according to another embodiment. The training operation may be performed by a training mode command, such as Fig. 6A shown between the time t0 and t1.

[0084] and Fig. 6A Differently, at time t3, calibration data may be present on both the CA[2:0] bus and the DQ[3:0] bus. At time t4, DQS_t may be activated one or more times to indicate the presence of calibration data. In some embodiments, DMI IO may be driven low, which may indicate that DQ[3:0] is to operate as an input. Calibration operations may then be performed, such as Figure 6B As shown, a calibration pattern is applied at CA[2:0] and detected by the memory device and can then be output on DQ[3:0] at time t8. In some embodiments, DMI IO can be driven high, which can indicate that DQ[3:0] will operate as an output, providing pattern data.

[0085] Figure 7 is a timing diagram of a write leveling operation of a memory device according to one embodiment. Figure 7 Includes the waveforms of CK, CKE, CS, CA[2:0], command, DQ[3:0], and DMI described earlier in this article. Figure 7 A differential data strobe signal DQS_t / (c) is also included. However, alternative embodiments may include a single-ended DQS signal.

[0086] At time t0, the memory device may receive two 12-bit mode register write commands (MRW-1, MRW-2) that may place the memory device in write-leveling mode. As described herein, each of these commands may be received in four 3-bit portions on consecutive rising edges of CK.

[0087] At time t1, after a time period tWLMRD after the last portion of MWR-2, the data strobe signal (DQS_t or DQS_c) may transition. The time period tWLMRD may be established by the controller device. At this point, the memory device may sample the strobe signal to generate a feedback value. In some embodiments, the clock CK may be used to sample the data strobe signal (DQS_t or DQS_c). If the sampled DQS signal has one value (e.g., high), all data buses DQ[3:0] may have that value (e.g., high). If the sampled DQS signal has another value (e.g., low), all data buses DQ[3:0] may have that value (e.g., low).

[0088] At time t2, after write equalization output delay (tWLO), the memory device can output a feedback value (e.g., a sampled clock state). A first portion of the feedback value (Fdbk[3:0]) can be output. At time t3, a second portion of the feedback value (Fdbk[7:4]) can be output. The value of DMI can change, indicating a change in the half-byte value (in this case, the more significant bit). At time t4, a third portion of the feedback value (Fdbk[11:8]) can be output, followed by a fourth portion (Fdbk[15:12]).

[0089] Based on these feedback values, the controller can adjust the placement of the DQS_t / DQS_c signals relative to the clock CK.

[0090] Fig. 8A and 8B is a diagram illustrating a read data bus (RD DQ) calibration operation for a memory device according to an embodiment. Fig. 8A is a timing diagram that includes the waveforms described previously herein. Figure 8B Included is a table showing the bit sequence output on DQ IO and DMI IO in RD DQ calibration operation.

[0091] refer to Fig. 8A , at time t0, the memory device may receive two 12-bit commands, including a multi-purpose command (MPC-1) followed by a CAS-2 command. Such commands may place the memory device in RD DQ calibration mode. As described herein, each of these commands may be received in four 3-bit portions on consecutive rising edges of CK. In RD DQ calibration mode, the memory device may access mode registers and output patterns defined in such registers on the DQ outputs.

[0092] After a read latency (RL) and an output access time (tDQSCK), the test pattern may be output on the reduced-size bus DQ[3:0] at time t3.

[0093] refer to Figure 8B , Table 802 shows a bit sequence that can be output on the DQ IO according to the value stored in the mode register 804. The mode register 804 can store values ​​corresponding to test patterns and inversion masks of these test patterns. In the RD DQ calibration operation shown, the DMI value is not inverted and does not indicate an inversion of the DQ output value. The register value 804 can be programmable and can also be set to a default value.

[0094] Fig. 9A and Fig. 9B1 is a timing diagram illustrating a data strobe to data bus (DQS-DQ) training operation for a memory device according to an embodiment. The DQS-DQ training operation can generate a test pattern to enable proper alignment of the data strobe signal DQS with the DQ value (e.g., DQS enables the DQ data latch in the center of the data "eye"). Fig. 9A A test FIFO write operation is shown. Fig. 9B A test FIFO read operation is shown.

[0095] refer to Fig. 9A , at time t0, the memory device may receive two 12-bit commands, including a multi-purpose command (MPC WR FIFO) followed by a CAS-2 command. Such commands may place the memory device in a write test FIFO mode. As described herein, each of these commands may be received in four 3-bit portions on consecutive rising edges of CK. In the illustrated embodiment, the write FIFO command is repeated at time t1.

[0096] At time t2, after write latency and other timing constraints, a write data value may be driven on DQ[3:0] (and optionally DMI). The data value may be selected by a controller device, etc. In addition, a data strobe value DQS_t with initial timing may be provided for the data value DQ[3:0]. Such a write data value may be stored in an entry (entry x) of the test FIFO. Depending on the training type of the controller, the test data may take any suitable form. In the illustrated embodiment, due to the timing of the two write test FIFO commands, the data of the next entry (entry x+1) may follow the data of the previous entry at time t3. In some embodiments, each write FIFO operation may write data to the next FIFO entry until the last FIFO entry is reached.

[0097] refer to Fig. 9B , after the test data has been written to the test FIFO with an initial DQS_t timing, such data values ​​may be read out from the test FIFO to evaluate the DQS_t timing.

[0098] refer to Fig. 9B , at time t0, the memory device may receive two FIFO read commands, each read command consisting of an MPC RD FIFO command followed by a CAS-2 command.

[0099] At time t1, after read latency and other delays, the data value from the first FIFO entry (entry x) can be output on DQ{3:0] (and optionally DMI). Based on these data values, the controller can determine the performance of the current DQS_t timing and adjust such timing if necessary. In the embodiment shown, due to the timing of the two reads from the test FIFO command, the data of the next entry (entry x+1) can follow the data of the previous entry at time t2. In some embodiments, each read FIFO operation can read data from the next FIFO entry until the last FIFO entry is reached.

[0100] Fig. 10A and Fig. 10B is a timing diagram illustrating a DQS interval oscillator read operation for a memory device according to an embodiment. In such an operation, an oscillator comprising a DQS clock tree path may be started and stopped to generate a count value. The count value may be used to detect any changes in the DQS clock tree path. If any such changes are large enough, the memory device may be retrained.

[0101] refer to Fig. 10A At time t0, the memory device may receive a 12-bit multipurpose command to start the DQS interval oscillator. As described herein, the command may be received as four 3-bit portions on consecutive rising edges of the CK signal.

[0102] At time t1, after a measurement period that may be selected by a controller or the like, the memory device may receive a 12-bit multipurpose command that captures the count value. This command may be received in the same manner as the start oscillator command (MPC command). Upon receipt of the stop oscillator command, the count value may be stored in a register.

[0103] At time t2, a read register command may be issued to read the counter value from the appropriate register. In the illustrated embodiment, this may include two 12-bit commands, including a mode register read (MRR) command followed by a CAS-2 command. In some embodiments, such a command may be received no earlier than a predetermined delay (tOSCO).

[0104] At time t3, after read latency and other delays, the oscillator counter value from the register can be output on DQ[3:0]. Based on this data value, the controller can determine whether additional training is needed to account for the delay variation introduced by the DQS_t clock tree path.

[0105] Fig. 10B is a timing diagram for an alternative method of obtaining the DQS interval oscillator count value. Fig. 10B The operation in can be similar to Fig. 10A, but a read register command (issued at t1) can cause the count value to be stored in the register and then output on DQ[3:0] (at time t3).

[0106] Fig.11 is a timing diagram for a read preamble training operation of a memory device according to an embodiment. Fig.11 Including waveforms as described herein. The read preamble training operation can be used to establish the read preamble timing for the DQS_t signal. Although Fig.11 Only DQS_t is shown, other embodiments may include a differential data strobe signal DQS_t / DQS_c, where the DQS_c signal will be driven to an opposite level as DQS_t.

[0107] At time t0, the memory device may receive 12-bit commands MRW-1 and MRW-2 that may place the memory device in a read preamble training mode. As described herein, each of these commands may be received in four 3-bit portions on consecutive rising edges of CK. After a delay tDSO after the last 3-bit portion of MRW-2, DQS_t may be driven low at time t1. After such a transition, the memory device will not lead the output data with a standard preamble or follow the output data with a standard postamble.

[0108] At time t2, the memory device may receive the 12-bit command MPC-1 and CAS-2 within 8 rising transitions of CK to initiate a training operation. At time t3, in response to such a command, after a read latency and other delays (e.g., tDQSCK), the DQS_t signal may transition synchronously with the data output on DQ[3:0]. In some embodiments, such output data may be data stored in a register (e.g., Figure 8B Based on such data, the controller can evaluate or train its DQS receiver.

[0109] Fig. 12A and Fig. 12B is a timing diagram illustrating a CA Vref training operation according to an embodiment. The CA Vref training operation may be used to establish a reference voltage for the CA input. However, the same process may be used to establish any other suitable reference value in a memory device. Fig. 12A is a timing diagram showing waveforms as described herein. Fig. 12B is a timing diagram detailing the data included in a received command.

[0110] refer to Fig. 12AAt time t0, the memory device may receive 12-bit commands MRW-1 and MRW-2 that may place the memory device in a reference value setting operation. As described herein, each such command may be received in four 3-bit portions on consecutive rising edges of CK.

[0111] After receiving the last part of MRW-2, after a delay of Vref_time, a new reference value may be established. In some embodiments, the delay Vref_time may vary depending on the magnitude of the change.

[0112] refer to Fig. 12B , a command structure in a reference setting operation according to an embodiment is shown in a timing diagram. The data types included in the command may include command data, CMD (i.e., a bit identifying the command); address value, ADD (i.e., a bit identifying the register address); reference value, Vref (i.e., a bit that can set the reference value); and DATA (which may include other data).

[0113] exist Fig. 12B In an embodiment of the present invention, the first command (MRW-1) may include command data in the first two parts and address data in the second two parts. The second command (MRW-2) may include command data in the first two parts and a reference value in the second two parts. In one embodiment in which the reference value establishes the CA reference voltage, such a reference value may include one bit for the Vref(CA) value range and six bits for setting the Vref(CA) value.

[0114] Understandably, Fig. 12B The specific values ​​shown in are merely an example and should not be construed as limiting.

[0115] Used for Figures 6A to 12B The command and address data values ​​for the various operations shown in the can take any suitable form. However, in some embodiments, the command and address values ​​can be compatible with the LPDDR4 standard (JESD209-4D), but can be sent on the novel CA bus and method described herein and its equivalent.

[0116] Fig.131 is a block diagram of a memory device 1302 according to an embodiment. The memory device 1302 may include a x4 DDR interface (I / F) circuit 1304, one or more memory arrays 1306, and a control circuit 1308. The x4 DDR I / F circuit 1304 may include CK, CS, CA[2:0] inputs, and DQS, DQ[3:0], and DMI IO or equivalent as described herein. Although the CK and DQS inputs are shown as single-ended, in alternative embodiments, one or both of such inputs may be differential inputs. As described herein, the x4 DDR I / F circuit 1304 may be a parallel interface because data is sent in parallel as nibbles on DQ[3:0]. The x4 DDR I / F circuit 1304 may include a DMI control circuit 1304-0, which may provide functionality for the DMI IO in addition to indicating data masking during a write operation or indicating data inversion during a read or write operation. Such additional functionality may include, but is not limited to, providing ECC data for read and write operations, an upper or lower nibble indicator for reading or writing data on DQ[3:0], and / or the status of DQ[3:0] (e.g., receiving or transmitting data).

[0117] In some embodiments, the x4 DDR I / F circuit 1304 may include an oscillator circuit 1304-1. The oscillator circuit 1304-1 may include at least a portion of the DQS signal path and may be used to determine a delay value for the DQS signal path. In some embodiments, the x4 DDR I / F circuit 1304 may include a training circuit 1304-2. The training circuit 1304-2 may enable data received on CA[2:0] to be provided to circuits other than command and / or address decoding circuits. In some embodiments, the training circuit 1304-2 may enable a portion of a reference value (e.g., those that establish a reference voltage) to be input to the DQ[3:0] IO along with another portion of the reference value.

[0118] The memory array 1306 may include one or more memory cell arrays that can store data in a write operation and output data in response to a read operation. The memory cell array may include memory cells of any suitable type (e.g., volatile, non-volatile) or architecture (random access, NOR, NAND). The memory array 1306 may also include corresponding decoding circuits, read path circuits, and write path circuits, including programming and erasing circuits in the case of non-volatile memory cells.

[0119] The control circuit 1308 may control the operation of the memory device and may include logic for performing operations indicated by commands received via the x4 DDR I / F circuit 1304. The control circuit 1308 may include registers 1308-2 (e.g., mode registers) for storing configuration and other values. All or a portion of such registers 1308-2 may be accessed via mode register read and mode register write commands.

[0120] In some embodiments, control circuit 1308 may include FIFO 1308-1 and / or reference voltage generator 1308-0. FIFO 1308-1 may store values ​​received at x4 DDR I / F circuit 1304 for subsequent readout during calibration operations. Reference voltage generator 1308-0 may generate a reference voltage in response to a configuration reference value received at x4 DDR I / F circuit 1304.

[0121] Fig.14 1402 is a block diagram of a memory device 1402 according to another embodiment. The memory device 1402 may include a memory device similar to Fig.13 Items of the memory device 1402 are denoted by the same reference characters, but preceded by a numeral "14" instead of "13". Fig.13 1406-0 to 1406-3, and the memory device 1402 may also include a serial IF 1410. The serial IF 1410 may enable serial data transactions on one or more serial data IOs (four, shown as S_DQ0 to S_DQ3) in synchronization with the serial clock S_CK and the serial chip select S_CS. In some embodiments, the serial IF 1410 may be compatible with the serial peripheral interface (SPI) standard. However, alternative embodiments may include an interface compatible with any other suitable serial standard.

[0122] Each of the memory banks (1406-0 to 1406-3) may include a plurality of non-volatile memory (NVM) cells. Within each memory bank (1406-0 to 1406-3), the NVM cells may be arranged in one or more arrays. The NVM cells may take any suitable form, and in some embodiments may be "flash memory" type NVM cells. The memory banks (1406-0 to 1406-3) may be separately addressable. That is, the physical addressing of the device 1402 may have separate memory bank addresses (1406-0 to 1406-3) for each memory bank. In the illustrated embodiment, all memory banks (1406-0 to 1406-3) may be connected to the first bus system 1412A or the second bus system 1412B. The first bus system 1412A may connect the memory banks (1406-0 to 1406-3) to the x4 DDR IF 1404, and the second bus system 1412B may connect the memory banks (1402-0 to 1402-3) to the second I / F 1406. Fig.14 A device having four memory banks is shown, embodiments may include a greater or lesser number of memory banks.

[0123] Fig.15 1 is a block diagram of an interface circuit 1514 that may be included in an embodiment. The interface circuit may include a physical receiver circuit 1516-0 and a physical transmitter circuit 1516-1, a CA input circuit 1518, a data input path circuit 1520, a data output path circuit 1522, a training path circuit 1524, and a DMI control circuit 1526. In some embodiments, the receiver and transmitter circuits 1516-0 / 1 may be low voltage swing stop logic (LVSTL) circuits.

[0124] CA input circuit 1518 may receive a three-bit value from CA[2:0] input and provide a value such as CA DATA IN. In some embodiments, CA DATA IN may be a six-bit input value consisting of two 3-bit input values. In some embodiments, CA input circuit 1518 may also provide data from CA[2:0] to training path circuit 1524.

[0125] Data input path circuit 1520 may receive a 4-bit data value from DQ[3:0] and provide a value such as internal data DATA_INT. Data output path circuit 1522 may receive output data from DATA_INT and provide such data as a 4-bit data value on DQ[3:0]. In some embodiments, DATA_INT may be a larger multiple of four bits, such as 8 bits, 16 bits, etc. Training path circuit 1524 may selectively connect data received on CA[2:0] input to data output path circuit 1522, such as in CA training mode.

[0126] The DMI control circuit 1504-0 may enable the DMI IO to provide various functions in addition to data masking and data inversion, including but not limited to providing ECC data for read and write operations, indicating the upper or lower nibble value of the read or write data on DQ[3:0], or indicating whether DQ[3;0] is to transmit or receive data. The DMI control circuit 1504-0 may receive an output DMI value and provide a DMI input value (DMI IO), and may provide and / or receive ECC data.

[0127] Fig.16A 1 is a schematic diagram of a CA input circuit 1618 according to an embodiment. The CA input circuit 1618 may include an input latch 1618-0, an input demultiplexer (deMUX) 1618-1, a deMUX logic 1618-3, and a command latch 1618-2. The input latch 1618-0 may latch a 3-bit value from CA[2:0] in response to a clock signal CK', which may be generated in response to a CK input (which may be other input states, such as CS). In response to the deMUX logic 1618-3, the deMUX 1618-2 may selectively pass the 3-bit value to different positions of the command latch 1618-2. The command latch 1618-2 may constitute a 12-bit command, which may be processed by a command decoder circuit, etc. The deMUX logic 1618-3 may generate a signal for clocking in a 3-bit portion of CA[2:0] to constitute a 12-bit command.

[0128] Although Fig.16A The embodiment of shows an arrangement for converting a 3-bit value into a 12-bit value for processing by a command decoding circuit or the like, and such an embodiment should not be construed as limiting. Alternative embodiments may include a device having a command decoding circuit that operates on the 3-bit portion of a command.

[0129] Fig. 16B 1 is a schematic diagram of a data path 1620 / 1622 according to an embodiment. In the illustrated embodiment, the data input path 1620 may include a DQ latch 1620-0, an input data control logic 1620-1, an input deMUX 1620-2, and an input data latch 1620-3. The DQ latch 1620-0 may latch a 4-bit value from DQ[3:0] in response to a signal DQS', which may be generated in response to an input data strobe and other signals. In response to the input deMUX logic 1620-1, the input deMUX 1620-2 may selectively pass a 4-bit value to different locations of the input latch 1620-3. The input data latch 1620-3 may constitute an 8-bit data value, which may or may not constitute part of a larger data value.

[0130] The data output path 1622 may include an output data latch 1622-0, an output data control logic 1622-1, an output MUX 1622-2, and an output driver 1622-3. The output data latch 1622-0 may store an 8-bit value for output on DQ[3:0]. In response to the output MUX logic 1622-1, the output MUX 1622-2 may selectively pass a 4-bit value from a different position of the output latch 1620-0 as output data. Such a data value may be driven by the output driver 1622-3 on DQ[3:0].

[0131] According to an embodiment, in some operations (such as Figure 6C Operation shown), DMI IO can indicate the status of DQ[3:0] IO. Fig. 16C is a schematic diagram showing one such embodiment. Fig. 16C The DMI control circuit 1604-0 includes a data output path circuit 1620B, a data input path circuit 1622B, a DMI control circuit 1604-0, and a mode control circuit 1624. The data output path circuit 1620B can provide data for output on DQ[3:0] and can be enabled or disabled by the mode control circuit 1624. The data input path circuit 1622B can receive data at DQ[3:0] as input data and can also be enabled by the mode control circuit 1624.

[0132] DMI control circuit 1604-0 may receive an input DMI signal and provide an output DMI signal. In addition, in response to mode control circuit 1624 detecting a low DMI input signal, data input path circuit 1622B may be enabled to receive input data (e.g., calibration value) on DQ[3:0] (and possibly on the CA bus). Subsequently, DMI control circuit 1604-0 may generate a DMI output signal indicating that DQ[3:0] is providing output data (e.g., a test pattern received on the CA bus).

[0133] According to an embodiment, in some operations (such as Fig. 6A and Figure 7 ), the DMI IO can indicate the importance of the output nibble on the DQ[3:0] IO. Fig.16D is a schematic diagram showing one such embodiment. Fig.16D The data output path circuit 1620D includes a data output path circuit 1622D, a data input path circuit 1622D, and a DMI control circuit 1604-0. The data output path circuit 1620D can provide data to be output on DQ[3:0], such as for Fig. 16BAs described, in response to the NIBBLE_CTRL signal, a 4-bit data value is multiplexed and output. The data input path circuit 1622B may receive data at DQ[3:0] according to any embodiment or equivalent herein.

[0134] The DMI control circuit 1604-0D may include an output portion 1604-0_Out that provides an output DMI signal and an input portion 1604-0_In that receives an input DMI signal. In addition, in response to the mode control signal MODE, the output portion 1604-0_Out may generate a DMI output signal that indicates a change in the half-byte importance and / or half-byte value of the data on DQ[3:0]IO. Similarly, the input portion 1604-0_In may receive an input DMI signal that indicates a change in the half-byte importance and / or half-byte value of the data on DQ[3:0]IO. As just two of many possible examples, in one type of calibration operation, the input DMI signal may have one value (e.g., low) to indicate a less significant bit of the input reference value on DQ[3:0], followed by another value (e.g., high) to indicate the presence of a more significant bit of the input reference value on DQ[3:0]; in another calibration operation, an output DMI signal may be generated having one value (e.g., low) when a less significant bit of the output value is driven on DQ[3:0], and an output DMI signal may be generated having another value (e.g., high) when a more significant bit of the output value is driven on DQ[3:0].

[0135] According to an embodiment, in some operations (such as Figure 6C ), the data received on CA[2:0] can be combined with the data received on DQ[3:0] to form a reference value (e.g., Vref[5:0]). Fig.16E is a schematic diagram showing one such embodiment. Fig.16E The CA input circuit 1618E, the data input path circuit 1620E, the data output path circuit 1622E, the DMI control circuit 1604-0E and the training path circuit 1624 are included. The data input path circuit 1620E can receive the data input values ​​and equivalents as described herein. The data output path circuit 1622E can provide the data output values ​​and equivalents as described herein.

[0136] CA input circuit 1618E may receive the 3-bit CA[2:0] values ​​and provide them to the command and / or address decoder. However, in addition, CA input circuit 1618E may include circuit 1618-4 that provides the CA[2:0] input values ​​to training path circuit 1624.

[0137] In some embodiments, training path circuit 1624 may include circuit 1624-1 for selectively providing data from CA[2:0] (e.g., CA pattern) as output data on data output path circuit 1620E. In some embodiments, training path circuit 1624 may include circuit 1624-0 for selectively providing data from CA[2:0] (e.g., Vref[2:0]) as a portion of the reference value, with DQ[3:0] providing another portion of the reference value (e.g., Vref[6:4]).

[0138] Although FIG. 16B to FIG. 16E The embodiment of the embodiment shows an arrangement for converting a 4-bit value on DQ[3:0] to an 8-bit value for transmission on the internal data bus, such an embodiment should not be construed as limiting. Alternative embodiments may include devices with native narrow (e.g., 3-bit CA, 4-bit data) internal buses.

[0139] While embodiments may include any suitable memory cell array structure, some embodiments may include a 1-transistor (1T) NOR type array. Fig.17A is a schematic diagram of a 1T NOR array 1706A that may be included in an embodiment. The array 1706A may include a plurality of memory cells (one shown as 1726-0) arranged in rows and columns, with memory cells in the same row connected to the same word line (one shown as 1726-2), and memory cells in the same column connected to the same bit line (one shown as 1726-3). In some embodiments, the memory cell (1726-0) may be constructed with a single transistor structure having a charge storage structure 1726-1 between the control gate and the channel. The charge storage structure 1726-1 may store one or more bits of data as a charge (including the absence of a charge). The charge storage structure 1726-1 may take any suitable form, including but not limited to: a floating gate, a charge storage dielectric (e.g., a replacement gate), or a combination thereof.

[0140] Although embodiments may include non-volatile memory cells, embodiments may also include any suitable volatile array structure or volatile memory cell type. Fig. 17B is a schematic diagram of a possible volatile memory cell array that may be included in an embodiment. Fig. 17BAn array 1706B is shown which may include a plurality of volatile memory cells (one shown as 1726-0V) arranged in rows and columns and connected to one or more bit lines (e.g., 1726-3) and word lines (e.g., 1726-2). The volatile memory cells may take any suitable form including, but not limited to, DRAM cells 1726-0V1 and / or SRAM cells 1726-0V2. The SRAM cells 1726-0V2 may include, but are not limited to, 4-transistor (4T), 6T, and / or 8T variations.

[0141] Fig.18 is a block diagram of an NVM device 1802 according to another embodiment. The NVM device 1802 can be an implementation of any of the devices shown herein. The NVM device 1802 can include a x4 LPDDR4 IF 1804, a plurality of memory banks 1806-0 to -7, a control circuit 1808, and a quad SPI (QSPI) compatible IF 1810. The x4 LPDDR4 IF can include a CS input, a CK input, a CKE input, a CA[2:0] input, a DQS IO, a DMI IO, and a DQ[3:0] IO. In some embodiments, the x4 LPDDR IF can have signaling requirements compatible with the LPDDR4 standard (JESD209-4D), but receives commands on a reduced CA bus size and provides data on a reduced DQ bus size, as described herein, or an equivalent. In some embodiments, the x4 LPDDR4 IF 1804 may have differential signals, including any differential clock inputs (CK_t, CK_c) or differential data strobes (DQS_t, DQS_c).

[0142] In some embodiments, each memory bank (1806-0 to 1806-7) may include NVM cells arranged in rows and columns. Each memory bank (1806-0 to 1806-7) may be separately accessible via a unique memory bank address. In some embodiments, the NVM cells may be erasable in groups (e.g., flash memory type cells). The first memory bank access circuit 1828-0 may implement read or write access to its corresponding memory bank (1802-0 to 1802-7) from the x4 LPDDR4 IF 1804 via the first bus system 1812A. The second memory bank access circuit 1828-1 may implement read or write access to its corresponding memory bank (1802-0 to 1802-7) from the QSPI IF 1810 via the second bus system 1812B. Different memory bank access circuits 1828-0 / 1 may implement simultaneous access to different memory banks via different interfaces 1804 / 1810.

[0143] Control circuitry 1808 may control the operation of device 1802 and may include any of the control circuit features described herein, including Fig.13 Those shown in .

[0144] QSPI IF 1810 may include a serial chip select SPI_CS, a serial clock input SPI_CK, and four serial data IOs SPI_DQ. Such IOs may be connected to an SPI-compatible serial bus. QSPI IF 1810 may process commands received via SPI_DQ. Such commands may include read and write (e.g., program, erase) commands.

[0145] While embodiments may include devices, circuits, and corresponding methods and operations, embodiments may also include systems having devices with reduced pin count interfaces connected to each other via a small high performance bus. One such embodiment is Fig.19 Shown in.

[0146] Fig.19 1 is a block diagram of a system 1930 according to an embodiment. The system 1930 may include a host microcontroller (MCU) 1932, a first memory device 1902, and a second memory device 1934. The host memory device 1932 may include a x4 DDR4 controller (controller) 1932. The controller 1932 may be connected to a DDR bus 1936, which may include signal lines according to any low pin count interface described herein. The DDR bus 1936 may include a CS input (CS_dram, CS_nvm) for each device. Although Fig.19 A bus of size 13 is shown, which may correspond to Figure 1B As with the devices shown, alternative embodiments may include smaller or larger bus sizes.

[0147] According to any embodiment herein, the first memory device 1902 may be an NVM device with a low pin count. According to any embodiment herein, the second memory device 1934 may be an NVM device with a low pin count. In this way, the system 1930 may include volatile and non-volatile storage while also including high performance signaling on a bus with reduced size.

[0148] Fig. 202030, and a plurality of other devices, three of which are shown as 2002, 2034, and 2038. The host system 2032 may include a x4 LPDDR4 memory controller (MC) 2032-0 and a serial bus MC 2032-1. The x4 LPDDR4 MC 2032-0 may access devices through the x4 LPDDR4 bus 2036 by issuing commands and data according to the embodiments disclosed herein or equivalents. The x4 LPDDR4 bus 2036 may include a reduced size CA bus (i.e., no more than five) and a reduced size DQ bus (i.e., no more than six) according to the embodiments disclosed herein and equivalents. The serial bus MC 2032-1 may access devices through the serial bus 2040 according to any suitable serial communication protocol.

[0149] Device 2002 may be an NVM device having an NVM array 2006 and may be connected to a x4 LPDDR bus 2036 via a x4 LPDDR IF 2004 and to a serial bus 2040 via a serial bus IF 2010. Device 2002 may take the form and equivalent of any device described herein. Device 2034 may be a DRAM device and may be connected to a x4 LPDDR bus 2036 via a x4 LPDDR IF 2004D. Device 2038 may be a serial device 2038 connected to a serial bus 2040.

[0150] The x4 LPDDR4 MC 2032-0 may issue commands (and possibly data) to a device 2002 or 2034 or equivalent as described herein.

[0151] While embodiments may include devices, systems, and corresponding methods, embodiments may also include a memory controller that may generate commands, addresses, and data values ​​via a x4 LPDDR I / F and equivalents as described herein. Fig.21 A memory controller 2132-0 according to such an embodiment is shown.

[0152] The memory controller 2132-0 may include a command queue 2142-0, a write queue 2142-1, a read queue 2142-2, a transaction processing circuit 2142-3, an MC IF 2104, and an ECC circuit 2142-5. The command queue 2142-0, the write queue 2142-1, and the read queue 2142-2 may be connected to a controller IF, which may be connected to a controller (e.g., a host processor), etc. The command queue 2142-0 may receive a memory request through the controller IF to access a memory device, or perform other operations (e.g., calibration or training). The write queue 2142-1 may receive write data to be written through the MC IF 2104. The read queue 2142-2 may provide read data received from the MC IF 2104.

[0153] The transaction processing circuit 2142-3 can encode the request into a command with predetermined bit values. In some embodiments, this can include encoding the command into a 12-bit command consisting of two 6-bit parts. In some embodiments, such a command can be compatible with the LPDDR4 standard (JESD209-4D). The transaction processing circuit can also format write data for output and read data received through the x4 LPDDR4 IF2104.

[0154] MC IF 2104 may generate commands and equivalents as described herein. In some embodiments, MC IF 2104 may receive 12-bit commands and output them as four 3-bit values ​​on CA[2:0]. Data values ​​may be received and sent in nibbles on DQ[3:0]. MC IF 2104 may enable DMI signals on DMI IO to also provide indications or equivalents in addition to masking and inversion as described herein. This may include, but is not limited to: encoding ECC data with inverted data; indicating the input or output state of DQ[3:0]; or indicating the upper or lower nibble of an 8-bit value on DQ[3:0].

[0155] Fig.22A 2 is a schematic diagram of a CA output circuit 2244 for a host device according to an embodiment. The CA output circuit 2244 may include an output latch 2244-0 and an output MUX 2240-1. The output latch 2240-0 may latch a 12-bit command. The MUX 2240-1 may output such a 3-bit portion on CA[2:0]. In some embodiments, the 12-bit command value may be issued in four 3-bit portions on consecutive rising edges of a timing clock (e.g., CK).

[0156] Fig. 22Bis a schematic diagram illustrating an MC DMI circuit 2246 according to an embodiment. The MC DMI circuit 2246 may generate a DMI output value on DMIIO that may include inverted data with ECC data in the same cycle of the timing clock. The MC DMI circuit 2246 may include a storage device 2246-1 for inverted or masked data, and a storage device 2246-2 for storing ECC data 2246-2. The storage devices 2246-0 / 1 may be registers or latches, etc. MUX 2246-3 may selectively output ECC data or DMI data including inverted and / or masked data. In some embodiments, such multiplexing may include providing mask / inverted data during half of the timing clock and providing ECC data during the other half of the timing clock, for example Figure 5C The one shown in is only an example.

[0157] While embodiments may include systems having a memory device operating in conjunction with a host device, embodiments may also include standalone devices having a reduced pin count interface as described herein, and equivalents. Such embodiments may include a memory device having a reduced pin count interface as described herein, and equivalents. Fig.23 Shown in. Fig.23 The packaged memory device 2303 is shown in a perspective top view. The memory device 2302 can take the form of any device described herein or an equivalent. In some embodiments, the memory device 2302 can include a single integrated circuit die. The memory device 2302 can include multiple physical connections (e.g., pins), one shown as 2348. In some embodiments, the memory device 2302 can provide high-speed LVSTL signaling, but with a relatively low pin count as described herein.

[0158] refer to Fig.24, an automotive system 2430 according to an embodiment is shown. The automotive system 2430 may have many subsystems (two are shown as 2430-0 and 2430-1). Subsystem 2430-0 / 1 may operate with a host device (e.g., a CPU subsystem) that communicates with one or more memory devices. Such a subsystem 2430-0 / 1 may include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, such a subsystem may include a dashboard display / control subsystem and / or an infotainment subsystem, just as two of many possible examples. Each subsystem 2430-0 / 1 may include a host device that can access a memory device, such as those described herein, via a reduced-size memory bus. That is, the host device may have a low-pin-count interface, and the memory device may be a low-pin-count memory device. In some embodiments, the host device may be configured to execute code directly from an NVM memory device and may benefit from high-speed data transfer rates, such as those compatible with LPDDR4 signaling.

[0159] Although the described devices and systems disclose various methods according to embodiments, additional methods will be described with reference to the flow charts.

[0160] Fig.25 2550-1 , a flow chart of a method 2550 of operating a memory device according to one embodiment. The method 2550 may include receiving a 3-bit portion of a command 2550-0. In some embodiments, this may include latching different command portions on a rising edge of a timing clock. Although the last portion of the command is not received (N from 2550-1), the next command portion 2550-2 may be received. When the last command portion has been received (Y from 2550-1), the received command 2550-4 may be processed. In some embodiments, the command may be a 12-bit command, and receiving the last command portion may include receiving a fourth 3-bit portion.

[0161] If the command is a write command (write from 2550-4), the method 2550 may include receiving the write data as a sequence of 4-bit nibbles on a 4-bit data bus 2550-5. In some embodiments, the command portion may be received at the rising and falling edges of the timing clock signal, and the 4-bit value may be received synchronously with the rising and falling edges of the timing clock signal (i.e., DDR mode). If the command is a read command (read from 2550-4), the method 2550 may output the read data as a sequence of 4-bit nibbles on a 4-bit data bus 2550-6. In some embodiments, such a value may be output in DDR mode. If the command is some other type of command, the command may be processed 2550-7. In some embodiments, this may include processing calibration / training operations as described herein.

[0162] Fig.26 26 is a flow chart of a method 2650 for providing inverted data for ECC data on a DMI IO according to an embodiment. In some embodiments, the method 2650 may be performed by a memory device. The method 2650 may include receiving a command 2650-0. Such actions may include receiving a command according to an embodiment described herein or an equivalent, including receiving multiple command portions on a reduced size CA bus over three or more clock cycle transitions.

[0163] Method 2650 may determine whether DMI ECC is enabled 2560-1. Such actions may include, but are not limited to, causing a configuration register to be programmed to a predetermined value, having a specific device ID, or causing a received command to indicate that the DMI signal will have ECC functionality. If DMI ECC is not enabled (N from 2650-1), method 2650 may execute command 2650-2.

[0164] If DMI ECC is enabled (Y from 2650-1), method 2650 can determine whether the command is a read or write command 2650-3. If the command is a read command (read from 2650-3), inversion data 2650-4 can be output on the DMI IO during half of the data clock cycle, and ECC data 2650-5 can be output on the other half of the data clock cycle. In some embodiments, such inversion data and ECC data can correspond to data output on the data IO (e.g., DQ[3:0]). If the command is a write command (write from 2650-3), inversion data 2650-6 can be received on the DMI IO during half of the data clock cycle, and ECC data 2650-7 can be received on the other half of the data clock cycle. In some embodiments, such inversion data and ECC data can correspond to data received on the data IO.

[0165] Fig. 27 2750 is a flow chart of a method 2750 for training inputs or outputs of a memory device according to an embodiment. The method 2750 may include receiving a command 2750-0. Such actions may include any of the actions described herein, or equivalents. The method 2750 may determine whether the received command indicates a training mode 2750-1. In some embodiments, such actions may include decoding a command to determine whether the command indicates a training mode in which one or more reference values ​​are expected to be received. As one of many possible actions, such actions may determine whether the command places the memory device in a CA bus training mode or a DQ training mode. If the training mode is not entered (N from 2750-1), the method 2750 may execute the received command 2750-2.

[0166] If training mode is entered (Y from 2750-1), method 2750 may include receiving a multi-bit reference value on both the CA bus and the DQ bus 2750-3. In some embodiments, such actions may include receiving a first portion of the reference value on the CA bus, and receiving the remainder of the reference value on the DQ bus. In some embodiments, different portions of the same reference value may be received simultaneously on the CA and DQ buses. In some embodiments, the reference value may be for a reference voltage used in a CA bus training operation.

[0167] Method 2750 may include configuring device 2750-4 with a reference value. In some embodiments, such actions may include generating an analog value based on bits of the reference value. In some embodiments, a reference voltage may be generated based on bits of the reference value.

[0168] Method 2750 may perform training operations 2750-5. Such actions may include providing additional inputs to the memory device, or requesting additional outputs from the memory device. In some embodiments, such actions may include applying a test pattern as an input to the CA bus and then receiving such values ​​received by the memory device on the DQ IO bus. The training operation may continue (N from 2750-6) until exiting training mode 2750-6. In some embodiments, exiting training mode includes receiving a predetermined command. However, in other embodiments, training mode may be exited after a predetermined period of time.

[0169] Fig.282850 is a flow chart of a method 2850 for indicating a portion of an output data value using a DMI signal according to an embodiment. This method can be performed by a memory device, a command issuing device (e.g., a storage controller), or a combination thereof. Method 2850 may include receiving a command 2850-0. Such an action may include any of the actions described herein, or an equivalent. Method 2850 may determine whether the received command indicates a special DMI mode 2850-1. In some embodiments, such an action may include decoding a command. As one of many possible actions, such an action may determine whether the command is placing the memory device in a CA bus training mode. If the special DMI mode is not entered (N from 2850-1), method 2850 may execute the received command 2850-2.

[0170] If entering training mode (Y from 2850-1), method 2850 may include generating data 2850-3. Such actions may include a memory device generating data for output on a data bus, or a command issuing device generating data for input to a memory device. DMI IO 2850-4 may be provided to a first portion of the data at a first level, and DMI IO 2850-5 may be provided to a second portion of the data at a second level. The DMI level may be established by the memory device, the command issuing device, or a combination thereof.

[0171] Fig.29 2950 is a flow chart of a method 2950 for indicating the state (i.e., input or output) of a bidirectional data bus with a DMI signal according to an embodiment. This method can be performed by a memory device, a command issuing device, or a combination thereof. The method 2950 may include receiving a command 2950-0. Such an action may include any of the actions described herein, or an equivalent. The method 2950 may determine whether the received command indicates a special DMI IO mode 2950-1. In some embodiments, such an action may include decoding the command. As one of many possible actions, such an action may determine whether the command is placing the memory device in a CA bus training mode. If the special DMI IO mode is not entered (N from 2950-1), the method 2750 may execute the received command 2950-2.

[0172] If a special DMI IO mode is entered (Y from 2950-1), method 2950 may include driving the DMI IO to a first level to indicate that the DQ will receive data 2950-3. Such an action may include driving a single DMI IO to a level to indicate that data is to be received on the DQ[3:0] data bus. In some embodiments, such an action may include a command issuing device that drives the DMI to a first level to indicate that a reference value is present on the DQ bus and / or the CA bus. Method 2950 may also include driving the DMI IO to a second level to indicate that the DQ is outputting data. In some embodiments, such an action may include a memory device driving the DMI to a second level to indicate that a test pattern value latched on the CA[3:0] input is available as output data on the DQ bus.

[0173] Figure 30A to Fig. 30C is a graph comparing the performance of a memory device according to an embodiment with conventional storage solutions.

[0174] FIG. 30A is a timing diagram showing a continuous read operation of a conventional x8 LPDDR4 SDRAM. These operations can be considered as "LPDDR x8" type operations. These operations can occur at a clock speed of 800MHz, and each read operation accesses 32 bytes of data. The read data is output at a double data rate, so 2 bytes will be provided per clock cycle in 16 clock cycles. The SDRAM can have a tRCD value of 18ns (i.e., 16 clocks) and an RL of 14 clocks. FIG. 30A includes CS, CA6 (i.e., 6-bit command address bus), a wait time corresponding to the first read command (Lat1), a wait time corresponding to the second read command (Lat2), and a waveform of DQ8 (i.e., 8-bit DQ IO bus).

[0175] Still referring to FIG. 30A , each read command may include two activation commands (ACT1 / ACT2) followed by a read command and a CAS command (RD / CAS). The RD / CS command may be received after a tRCD delay. The read data will be output after the RL following the CAS command. The read operations are timed to provide back-to-back bursts (16 clocks each), each providing 32 bytes of data.

[0176] Fig. 30B 30A is a timing diagram illustrating sequential read operations of a memory device according to one embodiment. These operations may be considered "LPDDR x4" operations. The memory device may be a DRAM, a non-volatile memory (e.g., NOR flash), or a combination thereof. These operations may include timing similar to that of FIG. 30A, including a clock speed of 800 MHz, a tRCD of 16 clocks, and an RL of 14 clocks. However, Fig. 30BThe operation includes a 3-bit reduced CA bus and a 4-bit reduced DQ bus. Therefore, although each read operation accesses 32 bytes of data, as shown in FIG30A, the read operation will provide 1 byte per clock cycle within 32 clocks. Fig. 30B Includes waveforms for CS, CA3 (ie, 3-bit command address bus), Lat1, Lat2, and DQ4 (ie, 4-bit DQ IO bus).

[0177] Still reference Fig. 30B , the same commands as in the case of FIG. 30A can be processed, however, due to CA3, the command can be received in four cycles instead of two. The read operations are timed to provide back-to-back bursts (32 clocks each), each providing 32 bytes of data.

[0178] Fig. 30C It is to combine the performance of conventional equipment with Fig. 30B A table comparing the performance of LPDDR x4 embodiments is shown. Fig. 30C The table includes parameters such as tCK (clock speed); number of pins; available bandwidth (estimated data transfer rate); and signaling (type of IO signaling used). The table contains parameters for HBM x16 memory, LPDDR x8, and LPDDR x4 embodiments. As shown, the LPDDR x4 embodiment can provide high performance with a low pin count (12).

[0179] Fig.31 is a diagram showing how a high-performance, reduced pin count memory device 3100 (eg, LPDDR4x4 RAM) according to an embodiment can be used as a solution between conventional devices with higher pin counts and / or lower performance.

[0180] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. Therefore, it is emphasized and should be understood that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. In addition, particular features, structures, or characteristics may be appropriately combined in one or more embodiments of the present invention.

[0181] Similarly, it should be understood that in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes combined in a single embodiment, figure or description thereof to simplify the disclosure to help understand one or more different inventive aspects. However, this disclosed method should not be interpreted as reflecting the intention that the claims require more features than those explicitly listed in each claim. On the contrary, inventive aspects do not lie in all the features of a single aforementioned disclosed embodiment. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, and each claim exists independently as a separate embodiment of the present invention.

Claims

1. A method, include: In integrated circuit devices: receiving a sequence of not less than three command value portions at a unidirectional command address (CA) bus having not more than four parallel inputs; Latching each command value portion synchronously with the rising edge of the timing clock; determining an input command based on a sequence of not less than three command value parts; executing the input command in the integrated circuit device; as well as A sequence of data values ​​that is output and input synchronously with the rising and falling edges of a data timing clock on a bidirectional data bus having no more than six data input / outputs (IOs).

2. The method according to claim 1, in: The sequence of receiving the command value portions includes receiving three-bit command value portions over four consecutive cycles of the timing clock to form a twelve-bit command.

3. The method according to claim 1, further comprising: include: In a first portion of the training mode of operation, at a data mask inversion (DMI) IO, driving a DMI signal on the DMI IO to a predetermined value to indicate that the data bus is configured to receive input data, and In a second portion of the training mode of operation, at least one data bus line is driven to a predetermined value to indicate that other ones of the data bus lines are providing output data.

4. The method according to claim 1, in: The sequence of output and input data values ​​includes receiving and transmitting data bytes as 4-bit nibbles on successive rising and falling edges of a data strobe clock synchronized with the timing clock.

5. The method according to claim 1, further comprising: include: In at least a first mode of operation, at a data mask inversion (DMI) IO, driving the DMI signal to a first value to indicate the less significant nibble of the output byte, and The DMI signal is driven to a second value to indicate a more significant nibble of the output byte.

6. The method according to claim 5, further comprising: include: receiving a test pattern value on the CA bus before driving the DMI IO; as well as The output bytes include a test pattern captured by the integrated circuit device.

7. The method according to claim 1, further comprising: include: In training mode receiving a voltage reference value on at least a data IO, and After receiving the voltage reference value, an input training value is received.

8. The method according to claim 7, in: Receiving the voltage reference value includes receiving a first portion of the voltage reference value on the data IO and subsequently receiving a second portion of the voltage reference value on the data IO.

9. The method according to claim 7, in: Receiving the voltage reference value includes receiving a first portion of the voltage reference value on the CA bus, and A second portion of the voltage reference value is received on the data bus concurrently with the first portion.

10. An integrated circuit (IC) device, include: Interfaces, including at least one clock input configured to receive a periodic timing clock; a command address (CA) bus having no more than four parallel inputs, the CA bus configured to receive a sequence of no less than three command value portions; at least one chip select (CS) configured to receive a chip select signal indicating valid CA data on the CA bus; a bidirectional data strobe input / output (IO) configured to output and receive a data strobe signal derived using the timing clock; a bidirectional data bus having no more than six parallel IOs, the bidirectional data bus being configured to receive data values ​​and transmit data values ​​synchronously with rising and falling edges of the data strobe signal; control circuitry configured to execute commands received as not less than three command value portions over successive cycles of the timing clock; as well as An array of memory cells is configured to retrieve and store data values ​​in response to commands received on the CA bus.

11. The IC device according to claim 10, in: The CA bus is configured to receive a three-bit command value portion; as well as The control circuit is configured to execute a command received as part of a command value over four consecutive cycles of the timing clock.

12. The IC device according to claim 10, in: The interface also includes a data mask inversion (DMI) I / O; and The IC device further includes a DMI control circuit, wherein the DMI control circuit is configured to: In a first portion of the training mode, driving a DMI signal on the DMI IO to a predetermined value to indicate that the data bus is configured to receive input data, and In a second portion of the training pattern, at least one data IO is driven to a predetermined value to indicate that other ones of the data IOs are providing output data.

13. The IC device according to claim 10, further comprising: include: The interface also includes a data mask inversion (DMI) IO; The data bus is configured to receive and transmit data bytes as 4-bit nibbles on successive rising and falling edges of a data strobe clock synchronized with the timing clock; as well as The DMI control circuit is configured as driving the DMI signal on the DMI IO to a first value to indicate a less significant nibble of an output byte, and The DMI signal is driven to a second value to indicate a more significant nibble of the output byte.

14. The IC device according to claim 10, further comprising: include: a training circuit configured to receive a first portion of a reference value via the CA bus and to receive a second portion of the reference value via the data bus; as well as A voltage reference circuit is configured to generate a reference voltage in response to the reference value.

15. The IC device according to claim 10, further comprising: include: The control circuit is further configured to receive a first portion of a reference value via the data IO and subsequently receive a second portion of the reference value via the data IO; as well as A voltage reference circuit is configured to generate a reference voltage in response to the reference value.

16. The IC device according to claim 10, further comprising: include: The interface also includes a data mask inversion (DMI) I / O; as well as The IC device also includes a DMI control circuit configured to, in a data mask write operation, prohibit writing of a data value received at the data IO when a DMI signal on the DMI IO has a first value, and allow writing of the data value received at the data IO when the DMI signal has a second value.

17. The IC device according to claim 10, in: The memory cell array includes non-volatile memory cells.

18. A system, include: A first memory device comprising: Device interface, which includes a clock input configured to receive a timing clock; a command address (CA) bus having no more than four parallel inputs, the CA bus configured to receive a single command over no less than three cycles of a timing clock; a bidirectional data bus having no more than six parallel input / outputs (IOs), the bidirectional data bus being configured to receive data values ​​and transmit data values ​​synchronously with rising and falling edges of a data strobe signal; and a memory cell array configured to retrieve and store data values ​​in response to commands received on the CA bus; and A system bus is coupled to the clock input, the CA bus, and the data bus.

19. The system according to claim 18, in: The first memory device is configured to receiving a command as a sequence of three-bit data values ​​on the CA bus over four cycles, and Data is received and transmitted on the data bus in sequences of four nibbles.

20. The system according to claim 18, further comprising: include: A host device is coupled to the system bus and is configured to issue a command to at least the first memory device as a sequence of four three-bit command value portions.

21. The system according to claim 18, in: The host device is configured, in a training mode of operation, issuing test pattern data for receipt on a CA bus of said first memory device, receiving, from the first memory device, the test pattern data received by the first memory device, and Adjust the timing of publishing data on the CA bus.

22. The system according to claim 18, further comprising: include: The memory cell array of the first memory device includes non-volatile memory cells; as well as A second memory device coupled to the system bus includes an array of volatile memory cells.

23. The system according to claim 18, in: The first memory device also includes a serial interface configured to send serial data on a serial data bus in synchronization with a serial clock; as well as A host device is coupled to the serial data bus.

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