Automatic overclocking controller based on circuit delay measurement

Abstract

The application discloses an automatic overclocking controller based on circuit delay measurement, and has the characteristics of including a CPU, a clock generator and a circuit delay measurer controller. Compared with the prior art, the application has the innovation that a two-dimensional multi-frame synthesis technology is used to process the sampling results of the circuit delay measurer, so that sampling noise is eliminated; and the automatic overclocking controller running on a heterogeneous FPGA can automatically find the highest frequency at which the accelerator can safely run.

Description

Technical Field

[0001] This invention relates to an automatic overclocking controller suitable for FPGA neural network accelerators. Background Technology

[0002] In recent years, FPGA-based neural network accelerators have been widely used [1], and various performance optimization methods have been proposed one after another [2]. Currently, the mainstream FPGA static timing analysis tools retain a certain timing margin to use the worst operating conditions, so overclocking technology can be used to remove the overly conservative timing margin to maximize performance. Although overclocking technology may cause timing errors, several studies have shown that neural networks can tolerate a small number of errors [3], which makes it possible to combine overclocking technology with neural network accelerators.

[0003] There are currently two main methods for handling potential timing errors: Algorithm-Based Fault Tolerance (ABFT) and timing error warning / delay measurement. The ABFT method verifies the algorithm input and output [4]. If the verification value does not meet certain features, an error occurs. The main limitation of this method is that it can only be applied to convolution calculations and cannot be applied to other operators in neural networks. Although the timing error warning / delay measurement method can be applied to any operator, the timing detector used cannot be applied to all timing paths [5].

[0004] References

[0005] [1] Yun Liang, Liqiang Lu, and Jiaming Xie. OMNI: A framework for integrating hardware and software optimizations for sparse cnns. IEEETrans.Comput.Aided Des.Integr.Circuits Syst., 40(8):1648–1661, 2021.

[0006] [2] Duy Thanh Nguyen, Tuan Nghia Nguyen, Hyun Kim, and Hyuk-Jae Lee. A high-throughput and power-efficient FPGA implementation of YOLO CNN for object detection. IEEE Trans. Very Large Scale Integr. Syst., 27(8): 1861–1873, 2019.

[0007] [3] Muhammad Abdullah Hanif, Rehan Hafiz, and Muhammad Shafique. Error resilience analysis for systematically employing approximate computing in convolutional neural networks. In Design, Automation & Test in Europe, DATE, pages 913–916. IEEE, 2018.

[0008] [4] Thibaut Marty, Tomofumi Yuki, and Steven Derrien. Safe overclocking for CNN accelerators through algorithm-level error detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39(12): 4777–4790, 2020.

[0009] [5] Jose L. Nunez-Yanez. Energy proportional neural network inference with adaptive voltage and frequency scaling. IEEE Trans. Computers, 68(5): 676–687, 2019. Summary of the Invention

[0010] The computational problem to be solved by this invention is that the existing ABFT method is mainly limited to convolution calculations and cannot be applied to other operators in neural networks; the timing detector used in the method based on timing error warning / delay measurement cannot be applied to all timing paths.

[0011] To solve the above-mentioned technical problems, the technical solution of the present invention is to provide an automatic overclocking controller based on circuit delay measurement, characterized in that it includes a CPU, a clock generator, and a circuit delay measurement controller, wherein:

[0012] The phase of the phase-shifted clock SCLK output by the clock generator is adjusted from 0° to 360°. The circuit delay measurement controller controls the circuit delay detector to sample the clock generator N times in the same phase before moving to the next phase, until sampling of the clock generator is completed in all phases. The final sample value of each phase is the average of the sample values ​​obtained by sampling N times in the current phase.

[0013] The circuit delay measurement controller is also used to perform lateral multi-frame synthesis on the final sampled values ​​of all obtained phases to obtain the transition points θ1 and θ2, where:

[0014] When performing horizontal multi-frame synthesis, the final sampled value of each phase is defined as one frame of data. Therefore, for the nth frame of data, after horizontal multi-frame synthesis, the nth frame of data is... Frame data up to the first The mean of the frame data, where M is the horizontal multi-frame synthesis coefficient;

[0015] The transition point θ1 is the point where the sampled value changes from 0 to 1 after horizontal multi-frame synthesis; the transition point θ2 is the point where the sampled value changes from 1 to 0 after horizontal multi-frame synthesis.

[0016] The CPU obtains the jump points θ1 and θ2 from the circuit delay meter controller and then calculates the circuit delay t. d And according to the circuit delay t d Determine the frequency f of the accelerator in the next operating cycle next .

[0017] Preferably, if the mean of the sampled values ​​obtained by N samplings of the current phase is not greater than 0.5, then the final sampled value of the current phase is 0; otherwise, the final sampled value of the current phase is 1.

[0018] Preferably, the circuit delay measurement controller includes a sampler and a jump point finder, wherein the sampler controls the circuit delay detector to obtain the final sampled values ​​of all phases and perform the lateral multi-frame synthesis, and the jump point finder finds the jump points θ1 and θ2.

[0019] Preferably, the sampler shares multiple circuit delay detectors, and the CPU calculates the circuit delay t of multiple paths through the multiple circuit delay detectors. d Delay t from multiple of the circuits d Select the longest circuit delay t d To determine the frequency f of the accelerator in the next operating cycle next .

[0020] Preferably, the CPU calculates the circuit delay t using the following formula. d :

[0021]

[0022] In the formula, T is the clock cycle.

[0023] The innovation of this invention compared to existing technologies lies in:

[0024] 1) Two-dimensional multi-frame synthesis technology is used to process the sampling results of the circuit delay meter to eliminate sampling noise;

[0025] 2) An automatic overclocking controller running on a heterogeneous FPGA can automatically find the highest frequency at which the accelerator can operate safely. Attached Figure Description

[0026] Figure 1 This illustration shows the automatic overclocking controller disclosed in this embodiment;

[0027] Figure 2 The flowchart illustrates the operation of the automatic overclocking controller;

[0028] Figure 3 This is the state transition diagram for the automatic overclocking controller;

[0029] Figure 4 This illustrates the circuit delay detector used in this embodiment;

[0030] Figure 5 The timing diagram of the circuit delay detector is shown;

[0031] Figure 6 This illustrates how the sampled value of the circuit delay meter varies with t. θ change;

[0032] Figure 7 This is a schematic diagram of horizontal multi-frame synthesis. Detailed Implementation

[0033] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0034] To efficiently implement an automatic overclocking controller, this embodiment proposes a control scheme based on a hybrid FPGA, comprising three parts: a CPU, a clock generator, and a Timing Delay Monitor Controller (TDM controller). Figure 1 As shown, its workflow is as follows: Figure 2 As shown.

[0035] The TDM controller consists of a sampler and a transition point finder, and is divided into three states: Idle, SampleValues, and Post-processing (Find Transition Points). Figure 3 As shown. To save space, multiple circuit delay detectors can share a single sampler. The circuit delay detector used in this embodiment is as follows. Figure 4 As shown, its working principle is described in detail in [1], and will only be briefly reiterated here. The delay detector of this circuit consists of a phase-shifted clock (ShadowClock, SCLK), two shadow registers S1 and S2, a synchronization register Y, and an OR gate. The combinational logic output serves as the clock signal for S1 and S2, where S1 captures the rising edge and S2 captures the falling edge. The shadow clock is connected to the data ports of S1 and S2. SCLK maintains the same frequency as the master clock, but has a phase θ that lags behind the master clock. The outputs Q1 and Q2 of the shadow registers are ORed by the synchronization register Y. Figure 4 The meanings of the symbols in the text are as follows:

[0036] D: Combinational logic output port.

[0037] t comb The time lag between the rising edge of the clock signal and the moment when the combinational logic output port D generates the output signal is relative to the time lag when the output signal arrives at the clock port C. In FPGA, the combinational logic delay includes both the propagation delay of the LUTs and the line delay between LUTs, but it can be considered as a whole.

[0038] t D-T Line delay from the combinational logic output port D to the path endpoint input port T.

[0039] t D-SLine delay from combinational logic output port D to the clock ports of shadow registers S1 and S2.

[0040] t d The time t represents the delay between the arrival of the output signal edge (T) from the rising edge of the clock signal at the C clock port and the arrival time (T) of the output signal edge generated by the combinational logic. d =t comb +t D-T .

[0041] t shadow The time t that lags between the arrival of the output signal edge generated by the combinational logic at the clock ports of shadow registers S1 and S2 and the arrival of the rising edge of the clock signal at the clock port C. shadow =t comb +t D-S .

[0042] t θ The phase-shift clock SCLK has the same frequency as the master clock MCLK, but its rising edge lags behind the master clock MCLK by a certain time. T is the clock cycle.

[0043] Among them, t shadow It is the delay measured by the circuit delay detector, and t d The desired delay is the two, which can be approximated as equal.

[0044] like Figure 5 As shown, when t θ When the value is small, the circuit delay detector sample value is 0; as t... θ Increasing the sample value to θ1 results in a value of 1, and as t... θ Continue increasing the value until the sampled value of θ2 becomes 0 again. θ2 That is, the measured delay t d Since the duty cycle of the clock signal is typically 50%, θ1 and θ2 will be 180° out of phase. However, during the process of the sampled value changing from 1 to 0, there is a period of unstable sampled value, called sampling jitter, i.e., θ 1′ to θ 1″ and θ 2′ to θ 2″ Two stages, such as Figure 6 As shown in the shaded area. To handle the stage where sampled values ​​are unstable, this invention proposes a two-dimensional multi-frame fusion (2D-MFF) technique. 2D-MFF consists of two steps: vertical multi-frame fusion and horizontal multi-frame fusion.

[0045] Vertical synthesis is completed during the sampling process. The sampler control circuit delays the detector multiple times in the same phase, and the average of these multiple samples is taken as the sample value of the current frame corresponding to that phase. For example, if 5 samples are taken at 100°, the sample values ​​are 10010, with an average of 0.4, then 0 is taken as the sample value for 100°. Horizontal multi-frame synthesis is completed after sampling, and it must be performed for each phase. The number of frames to be synthesized is defined by the developer as needed. In this embodiment, the horizontal multi-frame synthesis coefficient is 7. Therefore, for the sample value of the nth frame, its horizontal multi-frame synthesized value is the average of the sample values ​​of the (n-3), (n-2), (n-1), original nth frame, (n+3), (n+2), and (n+1)th frames. Before implementing horizontal multi-frame synthesis, the ends of the sampled sequence are padded to cover boundary conditions. Assuming a complete phase of 360° and a horizontal multi-frame synthesis coefficient of 7, the data values ​​at 357°, 358°, and 359° need to be padded to -3°, -2°, and -1°, respectively. The data value for the 0° phase is determined by the average of the data values ​​from the seven phase points between -3° and 3°. This process continues, with the final value for each phase point determined by the average of its neighboring phase samples. In hardware implementation, horizontal multi-frame synthesis can be achieved using a FIFO, for example... Figure 7 As shown: Period 1, the FIFO is filled with 1110110, and the mean is 1; Period 2, the FIFO outputs a 1 and inputs a 0, and the mean is still 1; ... After horizontal multi-frame synthesis, the original sampled value has an unstable phase of 011001 in the process of changing from 1 to 0. After two-dimensional multi-frame synthesis, this unstable phase becomes 111000, and the jitter disappears.

[0046] First, the CPU sends a start signal, and the accelerator and TDM controller start simultaneously. The sampler samples multiple times in the same phase before moving to the next phase, until all phases have been sampled. Then, the jump point finder performs lateral multi-frame synthesis for each path and finds jump points θ1 and θ2. Note that this operation must be completed before the accelerator stops running. When the accelerator stops running, the CPU obtains the jump points of each path from the TDM controller and calculates the circuit delay t. d And based on the longest delay t d Determine the frequency f of the accelerator in the next operating cycle next The frequency modulation strategy is determined by the developer. The simplest frequency modulation strategy is: if t d If the clock frequency is less than the current clock cycle, the operating frequency will increase by 1MHz; otherwise, it will decrease by 1MHz.

[0047] The above technical solution can be applied to FPGA-based neural network accelerators.

Claims

1. An automatic overclocking controller based on circuit delay measurement, characterized in that, Includes a CPU, clock generator, and circuit delay measurement controller, wherein: The phase of the phase-shifted clock SCLK output by the clock generator is adjusted from 0° to 360°. The circuit delay measurement controller controls the circuit delay detector to sample the clock generator N times in the same phase before moving to the next phase, until sampling of the clock generator is completed in all phases. The final sample value of each phase is the average of the sample values ​​obtained by sampling N times in the current phase. The circuit delay measurement controller is also used to perform lateral multi-frame synthesis on the final sampled values ​​of all obtained phases to obtain the transition points θ1 and θ2, where: When performing horizontal multi-frame synthesis, the final sampled value of each phase is defined as one frame of data. Therefore, for the nth frame of data, after horizontal multi-frame synthesis, the nth frame of data is... Frame data up to the first The mean of the frame data, where M is the horizontal multi-frame synthesis coefficient; The transition point θ1 is the point where the sampled value changes from 0 to 1 after horizontal multi-frame synthesis; the transition point θ2 is the point where the sampled value changes from 1 to 0 after horizontal multi-frame synthesis. The CPU obtains the jump points θ1 and θ2 from the circuit delay meter controller and then calculates the circuit delay t. d And according to the circuit delay t d Determine the frequency f of the accelerator in the next operating cycle next .

2. The automatic overclocking controller based on circuit delay measurement as described in claim 1, characterized in that, If the mean of the sampled values ​​obtained by N samplings of the current phase is not greater than 0.5, then the final sampled value of the current phase is 0; otherwise, the final sampled value of the current phase is 1.

3. The automatic overclocking controller based on circuit delay measurement as described in claim 1, characterized in that, The circuit delay measurement controller includes a sampler and a jump point finder, wherein the sampler controls the circuit delay detector to obtain the final sampled values ​​of all phases and perform the lateral multi-frame synthesis, and the jump point finder finds the jump points θ1 and θ2.

4. An automatic overclocking controller based on circuit delay measurement as described in claim 3, characterized in that, The sampler shares multiple circuit delay detectors, and the CPU calculates the circuit delay t for multiple paths using these multiple circuit delay detectors. d Delay t from multiple of the circuits d Select the longest circuit delay t d To determine the frequency f of the accelerator in the next operating cycle next .

5. An automatic overclocking controller based on circuit delay measurement as described in claim 1, characterized in that, The CPU calculates the circuit delay t using the following formula. d : In the formula, T is the clock cycle.

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