An IEGT device with enhanced anti-latch-up characteristics and a method of manufacturing the same

Abstract

The application discloses an IEGT device with enhanced anti-latch-up performance and a manufacturing method thereof, and solves the problem that the IEGT device is prone to latch-up under high temperature and large current in the prior art. The technical scheme is as follows: a P-type dummy region of the IEGT is formed on a zone-fusion single crystal silicon substrate sheet, groove trenches are etched on both sides, a sacrifice oxide layer is thermally grown, the sacrifice oxide layer is peeled off, a gate oxide layer is grown again, polycrystalline silicon is deposited in the groove trenches, a trench gate of the IEGT is formed, a PBody region and an emission region are formed by ion implantation on the front surface in sequence, a contact hole is etched, boron and boron difluoride are ion implanted on the front surface to form an ohmic contact area of the contact hole and deposit metal, a field stop FS layer and a collector region are formed by ion implantation on the back surface, and the back surface is sputtered with metal. The layout structure of the emitter N+ of the IEGT device is changed, the emitter resistance of the NPN transistor is increased, the current gain of the NPN transistor is reduced, and the anti-latch-up performance of the IEGT device is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to an IEGT device with enhanced anti-latch-up characteristics and a manufacturing method thereof. BACKGROUND

[0002] IEGT, namely, Injection Enhanced insulated Gate bipolar Transistor, is a technology of introducing a hole accumulation zone through an emitter near-surface layer to increase the injection efficiency of carrier electrons.

[0003] In the IEGT device, there is a parasitic NPNP thyristor structure composed of an emitter N+, a Pbody region, an N- region and a collector. In the case that the hole current is large or the collector-emitter voltage rising speed is too fast in the switching process, the Pbody / N+ junction will be turned on, which leads to the fact that the IEGT cannot be controlled to be turned off through the gate, and further leads to the fact that the IGBT fails due to overheating, namely, the so-called latch-up effect.

[0004] Figure 1 is an equivalent circuit diagram of the IEGT device. In order to prevent the latch-up effect of the IEGT device, the conduction of the PNP transistor and the NPN transistor in the parasitic NPNP thyristor structure must be inhibited. Usually, the method of reducing the common-base amplification factor of the two is adopted. The common-base amplification factor of the PNP transistor is usually reduced by reducing the injection efficiency of the collector of the IEGT, but this will cause the on-state voltage drop Vceon of the IEGT device to increase. Therefore, it is a better choice to reduce the common-base amplification factor of the NPN transistor. The common-base amplification factor of the NPN transistor can be reduced by increasing the emitter resistance R E of the NPN transistor. SUMMARY

[0005] The application aims to provide an IEGT device with enhanced anti-latch-up characteristics and a manufacturing method thereof, and solves the problem of latch-up of the IEGT device under high temperature and large current in the prior art.

[0006] A manufacturing method of an IEGT device with enhanced anti-latch-up characteristics, specifically comprising the following steps:

[0007] Step one, preparing a light-doped zone-fusion single crystal silicon substrate sheet;

[0008] Step two, performing P+ injection and promotion on the zone-fusion single crystal silicon substrate sheet to form a P-type dummy region of the IEGT;

[0009] Step three, etching a groove on the front surface, growing a sacrifice oxide layer, peeling off the sacrifice oxide layer and then growing a gate oxide layer again;

[0010] Step four, depositing polysilicon in the trench, completely filling the trench and etching back the Si wafer surface to form the trench gate of the IEGT;

[0011] Step five, front side ion implantation of boron B and thermal promotion to form the PBody region;

[0012] Step six, front side ion implantation of arsenic As and thermal promotion to form the emitter region;

[0013] Step seven, front side deposition of the interlayer dielectric layer composed of USG and BPSG;

[0014] Step eight, front side etching of the contact hole, with the etching depth of the bulk silicon region being below the emitter region;

[0015] Step nine, front side ion implantation of boron B and boron difluoride BF2 to form the contact hole ohmic contact region, and deposition of the metal;

[0016] Step ten, back side ion implantation to form the field stop FS layer;

[0017] Step eleven, back side ion implantation of B to form the collector region, and sputtering of the back side metal.

[0018] In step three, the etching position of the trench is on both sides of the P-type dummy region.

[0019] In step five, the PBody region is located on the other side adjacent to the P-type dummy region of the trench.

[0020] In step six, the emitter region is located above the PBody region.

[0021] In step seven, the interlayer dielectric layer covers the entire upper surface of the device.

[0022] In step eight, the contact hole is located above the emitter region and away from the trench.

[0023] An IEGT device with enhanced anti-latch-up characteristics manufactured by the above manufacturing method.

[0024] The beneficial effects of the present application are:

[0025] The present application increases the emitter resistance of the NPN transistor, reduces the current gain of the NPN tube, and improves the anti-latch-up capability of the IEGT device by changing the Layout structure of the emitter N+ of the IEGT device. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is the equivalent circuit diagram of the IEGT device;

[0027] Figure 2 is the top view of the existing IEGT device;

[0028] Figure 3 Top view of the IEGT device of the present invention;

[0029] Figure 4 Cross-sectional view of the prior art IEGT device;

[0030] Figure 5 Cross-sectional view of the IEGT device of the present invention;

[0031] Figure 6 Schematic diagram of step one of the present invention;

[0032] Figure 7 Schematic diagram of step two of the present invention;

[0033] Figure 8 Schematic diagram of step three of the present invention;

[0034] Figure 9 Schematic diagram of step four of the present invention;

[0035] Figure 10 Schematic diagram of step five of the present invention;

[0036] Figure 11 Schematic diagram of step six of the present invention;

[0037] Figure 12 Schematic diagram of step seven of the present invention;

[0038] Figure 13 Schematic diagram of step eight of the present invention;

[0039] Figure 14 Schematic diagram of step nine of the present invention;

[0040] Figure 15 Schematic diagram of step ten of the present invention;

[0041] Figure 16 Schematic diagram of step eleven of the present invention.

[0042] In the figure, 1 - Trench gate, 2 - dummy P+ implant region, 3 - Emitter N+ implant region, 4 - Contact hole region;

[0043] 100 - Substrate wafer, 200 - P-type dummy region, 300 - Trench, 301 - Gate oxide layer, 400 - PBody region, 500 - Emitter region, 600 - Interlayer dielectric layer, 700 - Contact hole, 800 - Contact hole ohmic contact region, 900 - Deposited metal, 101 - Field stop FS layer, 102 - Collector region, 103 - Backside metal. DETAILED DESCRIPTION

[0044] The present application will be described in detail below in conjunction with the drawings and specific embodiments. Since the IEGT device of the present application has the same regional structure and process flow as the existing IEGT device, in order to facilitate the display of the cross-sectional structure, the implementation process of the present application is described by using the cell structure which is symmetrical and inverted at the A-A' tangent position.

[0045] Figure 2 and Figure 3 are respectively the top view of the structure of the existing IEGT device and the top view of the structure of the IEGT device of the present application, in which the Trench gate is 1, the dummy P+ injection area is 2, the emitter N+ injection area is 3, and the contact hole area is 4. As shown in the figure, the present application enhances the anti-latch-up characteristics of the IEGT device by changing the emitter layout structure of the IEGT device and increasing the resistance of the emitter N+.

[0046] As Figures 6-16 shown, the present application specifically discloses a manufacturing method of an IEGT device with enhanced anti-latch-up characteristics, which specifically comprises the following steps:

[0047] Step one, preparing a light-doped zone fusion (Float Zone, FZ) single crystal silicon substrate sheet 100;

[0048] Step two, performing P+ injection and advancing on the zone fusion single crystal silicon substrate sheet to form a P-type dummy area 200 of the IEGT;

[0049] Step three, etching a trench 300 on the front side, the etching position being on both sides of the P-type dummy area, thermally growing a sacrificial oxide layer, peeling off and then growing a gate oxide layer 301 again;

[0050] Step four, depositing polycrystalline silicon in the trench 300 to completely fill the trench, and etching back the Si wafer surface on the top of the trench to form a trench gate of the IEGT;

[0051] Step five, performing front-side ion injection of boron B and thermal advancement on the zone fusion single crystal silicon substrate sheet outside the trench to form a PBody area 400;

[0052] Step six, performing front-side ion injection of arsenic As and thermal advancement on the PBody area 400 to form an emitter area 500;

[0053] Step seven, depositing an interlayer dielectric layer (ILD) 600 composed of USG and BPSG on the front side;

[0054] Step eight, etching a contact hole 700 on the outer edge of the PBody area position on both sides of the front side, and the etching body silicon area below is the emitter area;

[0055] Step nine, performing front-side ion injection of boron B and boron difluoride BF2 in the contact hole 700 to form a contact hole ohmic contact area 800, and depositing a metal 900.

[0056] Step ten, back ion implantation forms field stop FS layer 101;

[0057] Step eleven, back ion implantation B forms collector region 102, and sputtering back metal 103.

[0058] The anti-latch-up capability of the IEGT is obtained by reducing the current amplification gain of PNP and NPN or both, reducing the current gain of PNP will increase the on-state voltage drop, resulting in the increase of conduction loss of the device, so it is necessary to reduce the current gain of NPN, and the resistance of the NPN emitter is increased by layout structure revision, so that it has a positive temperature coefficient, and the anti-latch-up capability of the IEGT device is enhanced.

[0059] The content of the application is not limited to the examples listed, any equivalent transformation of the technical scheme of the application adopted by a person skilled in the art by reading the description of the application is covered by the claims of the application.

Claims

1. A method for manufacturing an IEGT device with enhanced anti-latch-up characteristics, characterized in that, Specifically, the following steps are included: Step 1: Prepare a lightly doped zone-melted single-crystal silicon substrate (100). Step 2: P+ implantation and advancement are performed on the zone-melted single-crystal silicon substrate to form the P-type dummy region (200) of IEGT. Step 3: Etch trenches (300) on the front side, thermally grow a sacrificial oxide layer, and then grow a gate oxide layer (301) after stripping. Step 4: Deposit polysilicon in the trench (300) to completely fill the trench, and etch back the Si wafer surface to form the trench gate of the IEGT; Step 5: Positive ion implantation of boron (B) followed by thermal propulsion to form the PBody region (400). Step 6: Implant arsenic (As) ions onto the front side and thermally propel it to form the emission region (500). Step 7: Deposit an interlayer dielectric layer (600) consisting of USG and BPSG on the front side. Step 8: Etch the contact hole (700) on the front side, with the depth of the etched silicon area below the emitter region; Step 9: Implant boron B and boron difluoride BF2 onto the front side to form an ohmic contact region (800) of the contact hole, and deposit metal (900). Step 10: Backside ion implantation to form a field-stop FS layer (101); Step 11: Ion implantation of B on the back side forms a current collector region (102), and sputtering of back side metal (103). The contact hole region (4) of the IEGT device manufactured by the above method is arranged in an intermittent form. The resistance of the emitter N+ injection region (3) includes the region between the Trench gate (1) and the contact hole region (4) and the resistance along the sidewall of the Trench gate (1) and at the discontinuity of the contact hole.

2. The method for manufacturing an IEGT device with enhanced anti-latch-up characteristics according to claim 1, characterized in that: In step three, the etching locations of the trench (300) are on both sides of the P-type dummy region (200).

3. The method for manufacturing an IEGT device with enhanced anti-latch-up characteristics according to claim 2, characterized in that: In step five, the PBody area is located on the other side adjacent to the P-type dummy area of ​​the trench (300).

4. The method for manufacturing an IEGT device with enhanced anti-latch-up characteristics according to claim 3, characterized in that: In step six, the emission area (500) is located above the PBody area (400).

5. The method for manufacturing an IEGT device with enhanced anti-latch-up characteristics according to claim 4, characterized in that: In step seven, the interlayer dielectric layer (600) covers the entire upper surface of the device.

6. A method for manufacturing an IEGT device with enhanced anti-latch-up characteristics according to claim 5, characterized in that: In step eight, the contact hole (700) is located above the emission area and away from the trench (300).

7. An IEGT device with enhanced anti-latch-up characteristics manufactured by the manufacturing method of claim 1.

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