A low-power circuit suitable for wireless detection of lees pH and its control method

Abstract

The invention provides a low-power circuit suitable for wireless detection of pH value of distiller's grains and a control method thereof, belonging to the technical field of detection circuits. The invention solves the problem of high energy consumption and data duplication caused by the existing distiller's grains wireless detection sensor continuously uploading data with little pH value change. The invention comprises a two-time pH value acquisition circuit and a two-time pH value judgment circuit, wherein the two-time pH value acquisition circuit includes two acquisition circuit parts with completely identical structures, wherein the two acquisition circuits are respectively provided with switch tubes Q1 and Q2, and only one of Q1 and Q2 can be turned on, and the D poles of Q1 and Q2 are both connected to the voltage value output by the pH sensor. The two-time pH value judgment circuit judges the values of the pH sensor collected twice and triggers a single-chip microcomputer and a wireless module to send data according to a threshold value. The invention is applied to pH value detection and judgment.

Description

Technical Field

[0001] The invention provides a low-power consumption circuit suitable for wireless detection of pH value of lees and a control method thereof, belonging to the technical field of detection circuits. Background Art

[0002] Currently, a wireless wine lees pH detection sensor is generally used to detect the pH value of the wine lees in real time during the wine lees fermentation process. During the detection process, the pH value of the wine lees is continuously sent according to the set sampling frequency. However, during the wine lees fermentation process, the pH value generally rises slowly, that is, the pH value generally does not change much in a short period of time. However, the existing sensor still continuously sends data through the wireless module, which consumes a lot of power for the sensor and is not energy-saving. At the same time, a large amount of approximate data is obtained in a short period of time, which also causes a certain amount of waste in data storage. Summary of the Invention

[0003] In order to solve the problem that the existing lees wireless detection sensor continuously uploads data with little pH change, resulting in high energy consumption and data duplication, the present invention proposes a low-power circuit suitable for wireless detection of lees pH and a control method thereof.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a low-power circuit suitable for wireless detection of lees pH, including two pH value acquisition circuits and two pH value judgment circuits, wherein the two pH value acquisition circuits include two acquisition circuits with exactly the same structure, wherein the two acquisition circuits are respectively provided with switch tubes Q1 and Q2, and Q1 and Q2 can only be turned on at one, and the D poles of Q1 and Q2 are both connected to the voltage value output by the pH sensor, and the S pole of Q1 or Q2 is respectively connected in parallel to one end of the inductor in the respective acquisition circuit, the D pole of Q3 or Q4, and the non-inverting input end of the voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator, and the other end of the inductor is connected in parallel to one end of the capacitor, the inverting end of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator. The phase input terminal and the non-phase input terminal of the voltage comparator, the other end of the capacitor is grounded, the output terminal of the voltage comparator is connected to the exclusive OR circuit composed of logic gates, the output terminal of the exclusive OR circuit in the acquisition circuit controlled by Q1 is connected in parallel to the input terminals of two NOT gates U20 and U19, the output terminal of the exclusive OR circuit in the acquisition circuit controlled by Q2 serves as an input terminal of the AND gate U18, the output terminal of the NOT gate U20 is connected to the G pole of Q1, the output terminal of the NOT gate U19 is connected in parallel to the delay circuit composed of capacitor L3 and resistor R3 and then connected to the other input terminal of the AND gate U18, the output terminal of the AND gate U18 is connected to the NOT gate U21 and then connected to the G pole of Q2, the S pole of Q5 is also connected between the capacitor L3 and the resistor R3, the G pole of Q5 is connected in parallel to the G pole of Q4 and the G pole of Q3, and the D pole of Q5 is grounded;

[0005] The two pH value judgment circuits include a NAND gate U17, the input ends of the NAND gate U17 are respectively connected to the output ends of the NOT gate U20 and the output ends of U21, the output end of the NAND gate U17 is connected to the G pole of Q6, the non-inverting input ends of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator in the two acquisition circuits are respectively used as the two input ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and the differential amplifier U22A, the output ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A are respectively connected to the non-inverting input end of the voltage comparator U24 and the non-inverting input end of the voltage comparator U23, the output end of the voltage comparator U23 is connected to the G pole of Q5, the inverting input end of the voltage comparator U24 is connected to the voltage V1, and the output end of the voltage comparator U24 is connected to the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOT gate U26.

[0006] The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R8, R9, R10, R11, a voltage comparator U3, and a differential amplifier U28A in a circuit controlled by Q1, wherein one end of the resistor R8 is grounded, the other end of the resistor R8 is connected in parallel to one end of the resistor R11 and then connected to the non-inverting input end of the differential amplifier U28A, one end of the resistor R9 is connected to the inverting input end of the differential amplifier U28A, the other end of the resistor R9 is connected in parallel to one end of the resistor R10 and then connected to an end connected to the inductor L1 and the capacitor C1, and also serves as the non-inverting input end of the voltage comparator U2, the other end of the resistor R10 is connected in parallel to the output end of the differential amplifier U28A and then connected to the non-inverting input end of the voltage comparator U3, and the inverting input end of the voltage comparator U3 is grounded;

[0007] The other end of the inductor L1 is connected in parallel to the other end of the resistor R11 , the S pole of the switch tube Q1 , and the D pole of the switch tube Q3 . The S pole of the switch tube Q3 is grounded.

[0008] The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q1 includes an AND gate U4, a NOT gate U5, an OR gate U6, a NOT gate U7, and an AND gate U8. The two input ends of the AND gate U4 are respectively connected to the output end of the NOT gate U5 and the output end of the NOT gate U7. The input end of the NOT gate U5 is connected in parallel to the output end of the voltage comparator U2 and one input end of the AND gate U8. The input end of the NOT gate U7 is connected in parallel to the output end of the voltage comparator U3 and the other input end of the AND gate U8. The output end of the NOT gate U5 and the output end of the NOT gate U7 serve as the two input ends of the AND gate U4 respectively. The output end of the AND gate U4 is connected to one input end of the OR gate U6. The other input end of the OR gate U6 is connected to the output end of the AND gate U8. The output end of the OR gate U6 is connected in parallel to the input end of the NOT gate U20 and the input end of the NOT gate U19.

[0009] The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R12, R13, R14, R15, a voltage comparator U11, and a differential amplifier U1A in the circuit controlled by Q2, wherein one end of the resistor R12 is grounded, the other end of the resistor R12 is connected in parallel to one end of the resistor R13 and then connected to the non-inverting input end of the differential amplifier U1A, one end of the resistor R14 is connected in parallel to one end of the resistor R15 and then connected to the inverting input end of the differential amplifier U1A, the other end of the resistor R14 is connected in parallel to one end of the resistor R10 and then connected to one end connected to the inductor L2 and the capacitor C2, and also serves as the non-inverting input end of the voltage comparator U10, the other end of the resistor R15 is connected in parallel to the output end of the differential amplifier U1A and then connected to the non-inverting input end of the voltage comparator U11, and the inverting input end of the voltage comparator U11 is grounded;

[0010] The other end of the inductor L2 is connected in parallel to the other end of the resistor R13, the S pole of the switch tube Q2, and the D pole of the switch tube Q4. The S pole of the switch tube Q4 is grounded.

[0011] The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q2 includes an AND gate U12, a NOT gate U13, an OR gate U14, a NOT gate U15, and an AND gate U16. The two input ends of the AND gate U12 are respectively connected to the output end of the NOT gate U13 and the output end of the NOT gate U15. The input end of the NOT gate U13 is connected in parallel to the output end of the voltage comparator U10 and one input end of the AND gate U16. The input end of the NOT gate U15 is connected in parallel to the output end of the voltage comparator U11 and the other input end of the AND gate U16. The output end of the NOT gate U13 and the output end of the NOT gate U15 serve as the two input ends of the AND gate U12 respectively. The output end of the AND gate U12 is connected to one input end of the OR gate U14. The other input end of the OR gate U14 is connected to the output end of the AND gate U16. The output end of the OR gate U14 is connected to one input end of the AND gate U18.

[0012] The structure of the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOR gate U26 is as follows:

[0013] One end of the capacitor C4 is connected to the output end of the voltage comparator U24, the other end of the capacitor C4 is connected in parallel to one end of the resistor and then to an input end of the NOR gate U25, the other end of the resistor R5 is grounded, the other input end of the NOR gate U25 is connected in parallel to the output end of the NOR gate U26 and the input end of the NOR gate U27, the output end of the NOR gate U25 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected in parallel to one end of the resistor R6 and the input end of the NOR gate U26, the other end of the resistor R6 is connected to the power supply, the output end of the NOR gate U27 is connected to the G pole of the switch tube Q7, the D pole of the switch tube Q7 is connected to the power supply, and the S pole of the switch tube Q7 is connected in series with the resistor R7 and then to the ground.

[0014] The differential amplifier circuit structure composed of R1, R2, R3, R4, Q6, and differential amplifier U22A is as follows:

[0015] The non-inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R1 and one end of the resistor R4, the other end of the resistor R1 is connected to one end of the inductor L1 and the capacitor C1, and the other end of the resistor R4 is grounded;

[0016] The inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R2 and one end of the resistor R3. The other end of the resistor R2 is connected in parallel to the output terminal of the differential amplifier U22A, the non-inverting input terminal of the voltage comparator U23, and the non-inverting input terminal of the voltage comparator U24. The other end of the resistor R3 is connected to one end of the inductor L2 connected to the capacitor C2.

[0017] The positive power supply of the differential amplifier U22A is connected to the S pole of the switch tube Q6, the negative power supply of the differential amplifier U22A is grounded, and the D pole of the switch tube Q6 is connected to the power supply.

[0018] A control method for a low-power circuit suitable for wireless detection of lees pH value, using the low-power circuit suitable for wireless detection of lees pH value, and defining the connection point between an inductor L1 and a capacitor C1 as A, the connection point between an inductor L2 and a capacitor C2 as B, the G pole of Q1 as point C, the connection point between the G pole of Q1 and a NOT gate U20 as I, the G pole of Q2 as point D, the connection point between the G pole of Q2 and a NOT gate U21 as H, the G poles of Q3 and Q4 connected in parallel as point E, the connection point between the NOT gate U20 and the NOT gate U19 as F, the output end of an OR gate U14 as point G, the connection point between the NOT gate U19 and the inductor L3 as R, the connection point between the inductor L3 and the AND gate U18 as L, the point where the output end of a voltage comparator U3 is connected in parallel with NAND gates U7 and U8 as J, and the point where the voltage comparator U2 is connected in parallel with NAND gates U5 and U8 as K.

[0019] The steps include:

[0020] Step 1: The pH sensor starts measuring. In the initial state, F is at a high level. After passing through the NOT gate U20, the voltage at point C becomes a low level. At this time, Q1 is turned on by the low level at point C. The pH voltage at this moment starts to charge C1. After C1 is fully charged, it outputs a high level at point K through the voltage comparator U2. The voltage difference between both ends of L1 is 0. After passing through the voltage comparison circuit composed of the differential amplifier U28A and the voltage comparator U3, the output voltage at point J is 0. J and K pass through the exclusive OR circuit composed of U4, U5, U6, U7, and U8. At this time, point F becomes a low level.

[0021] Step 2: The switching transistor Q1 changes from conducting to off state, and the voltage at point G remains low from the initial state. When the voltage at point F becomes low, after passing through the NOT gate U19, the voltage at point R becomes high. At this time, through the delay circuit composed of L3 and C3, after a time T = L3C3, the voltage at point L becomes high; at this time, after passing through the AND gate U18 and the NOT gate U21 between G and L, the voltage at point H becomes low, and the switching transistor Q2 conducts. Using the PH voltage value at this moment to start charging C2, the principle is the same as in Step 1. Finally, the voltage at point G becomes low, and Q2 turns off; thus, the PH voltage values are collected twice;

[0022] Step 3: When the PH values are collected twice, the voltages at points H and I become high. At this time, after passing through the NAND gate U17, Q6 conducts, and the differential amplifier U22A starts to work; the voltages at points A and B are amplified by the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A and then output U1. At this time, there is a high-level output at E, and the NMOS transistors Q3, Q4, and Q5 conduct, discharging C1, C2, and C3 completely;

[0023] Step 4: To determine whether the two measured PH voltage values are greater than the set reference voltage value, U1 needs to pass through the voltage comparator U24 with V1 as the reference voltage. If U1 > V1, the high-level value output at point Q is controlled by the monostable flip-flop composed of C4, R5, U25, C5, R6, and U26 for pulse delay. During the period when Q maintains a high level, the voltage at point R is low, and the PMOS transistor Q7 conducts. At this time, the power supply connecting the microcontroller and the wireless module represented by R7 is on, that is, the microcontroller and the wireless module are powered on and work normally: collect the PH value and send data;

[0024] If U1 < V1, the voltage at point Q outputs low level, and the PMOS transistor Q7 does not conduct, and the microcontroller and the wireless module lose power and do not collect or send data;

[0025] Step 5: Repeat the above Steps 1 - 4 for cyclic judgment.

[0026] The beneficial effects of the present invention compared with the prior art are as follows: The low-power circuit provided by the present invention mainly controls whether the microcontroller and the wireless module are powered on to process and send data through the difference between the two measured PH values. Within a certain time interval, when the difference between the two measured PH values is less than the set value, the microcontroller and the wireless module lose power and do not process or send data. When the difference between the two measured PH values is greater than the set value, the microcontroller and the wireless module are powered on to collect and send data, reducing the power consumption of the sensor and reducing invalid data. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following further describes the present invention with reference to the drawings:

[0028] Figure 1This is a circuit schematic diagram of the present invention for collecting the sensor output voltage twice;

[0029] Figure 2 This is a schematic diagram of the circuit for comparing the output voltages of two sensors in the present invention. DETAILED DESCRIPTION

[0030] like Figures 1 to 2 As shown, the present invention provides a low-power circuit suitable for wireless detection of lees pH, including two pH value acquisition circuits and two pH value judgment circuits, wherein the two pH value acquisition circuits include two acquisition circuits with exactly the same structure, wherein the two acquisition circuits are respectively provided with switch tubes Q1 and Q2, and Q1 and Q2 can only be turned on at one, and the D poles of Q1 and Q2 are both connected to the voltage value output by the pH sensor, and the S pole of Q1 or Q2 is respectively connected in parallel to one end of the inductor in the respective acquisition circuit, the D pole of Q3 or Q4, and the non-inverting input end of the voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator, and the other end of the inductor is connected in parallel to one end of the capacitor, the inverting input end of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator, and the voltage comparator. The non-inverting input terminal of the comparator and the other end of the capacitor are grounded. The output terminal of the voltage comparator is connected to the exclusive OR circuit composed of logic gates. The output terminal of the exclusive OR circuit in the acquisition circuit controlled by Q1 is connected in parallel to the input terminals of two NOT gates U20 and U19. The output terminal of the exclusive OR circuit in the acquisition circuit controlled by Q2 serves as an input terminal of the AND gate U18. The output terminal of the NOT gate U20 is connected to the G pole of Q1. The output terminal of the NOT gate U19 is connected in parallel to the delay circuit composed of capacitor L3 and resistor R3 and then connected to the other input terminal of the AND gate U18. The output terminal of the AND gate U18 is connected to the NOT gate U21 and then connected to the G pole of Q2. The S pole of Q5 is also connected between the capacitor L3 and the resistor R3. The G pole of Q5 is connected in parallel to the G pole of Q4 and the G pole of Q3. The D pole of Q5 is grounded.

[0031] The two pH value judgment circuits include a NAND gate U17, the input ends of the NAND gate U17 are respectively connected to the output ends of the NOT gate U20 and the output ends of U21, the output end of the NAND gate U17 is connected to the G pole of Q6, the non-inverting input ends of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator in the two acquisition circuits are respectively used as the two input ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and the differential amplifier U22A, the output ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A are respectively connected to the non-inverting input end of the voltage comparator U24 and the non-inverting input end of the voltage comparator U23, the output end of the voltage comparator U23 is connected to the G pole of Q5, the inverting input end of the voltage comparator U24 is connected to the voltage V1, and the output end of the voltage comparator U24 is connected to the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOT gate U26.

[0032] The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R8, R9, R10, R11, a voltage comparator U3, and a differential amplifier U28A in a circuit controlled by Q1, wherein one end of the resistor R8 is grounded, the other end of the resistor R8 is connected in parallel to one end of the resistor R11 and then connected to the non-inverting input end of the differential amplifier U28A, one end of the resistor R9 is connected to the inverting input end of the differential amplifier U28A, the other end of the resistor R9 is connected in parallel to one end of the resistor R10 and then connected to an end connected to the inductor L1 and the capacitor C1, and also serves as the non-inverting input end of the voltage comparator U2, the other end of the resistor R10 is connected in parallel to the output end of the differential amplifier U28A and then connected to the non-inverting input end of the voltage comparator U3, and the inverting input end of the voltage comparator U3 is grounded;

[0033] The other end of the inductor L1 is connected in parallel to the other end of the resistor R11 , the S pole of the switch tube Q1 , and the D pole of the switch tube Q3 . The S pole of the switch tube Q3 is grounded.

[0034] The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q1 includes an AND gate U4, a NOT gate U5, an OR gate U6, a NOT gate U7, and an AND gate U8. The two input ends of the AND gate U4 are respectively connected to the output end of the NOT gate U5 and the output end of the NOT gate U7. The input end of the NOT gate U5 is connected in parallel to the output end of the voltage comparator U2 and one input end of the AND gate U8. The input end of the NOT gate U7 is connected in parallel to the output end of the voltage comparator U3 and the other input end of the AND gate U8. The output end of the NOT gate U5 and the output end of the NOT gate U7 serve as the two input ends of the AND gate U4 respectively. The output end of the AND gate U4 is connected to one input end of the OR gate U6. The other input end of the OR gate U6 is connected to the output end of the AND gate U8. The output end of the OR gate U6 is connected in parallel to the input end of the NOT gate U20 and the input end of the NOT gate U19.

[0035] The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R12, R13, R14, R15, a voltage comparator U11, and a differential amplifier U1A in the circuit controlled by Q2, wherein one end of the resistor R12 is grounded, the other end of the resistor R12 is connected in parallel to one end of the resistor R13 and then connected to the non-inverting input end of the differential amplifier U1A, one end of the resistor R14 is connected in parallel to one end of the resistor R15 and then connected to the inverting input end of the differential amplifier U1A, the other end of the resistor R14 is connected in parallel to one end of the resistor R10 and then connected to one end connected to the inductor L2 and the capacitor C2, and also serves as the non-inverting input end of the voltage comparator U10, the other end of the resistor R15 is connected in parallel to the output end of the differential amplifier U1A and then connected to the non-inverting input end of the voltage comparator U11, and the inverting input end of the voltage comparator U11 is grounded;

[0036] The other end of the inductor L2 is connected in parallel to the other end of the resistor R13, the S pole of the switch tube Q2, and the D pole of the switch tube Q4. The S pole of the switch tube Q4 is grounded.

[0037] The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q2 includes an AND gate U12, a NOT gate U13, an OR gate U14, a NOT gate U15, and an AND gate U16. The two input ends of the AND gate U12 are respectively connected to the output end of the NOT gate U13 and the output end of the NOT gate U15. The input end of the NOT gate U13 is connected in parallel to the output end of the voltage comparator U10 and one input end of the AND gate U16. The input end of the NOT gate U15 is connected in parallel to the output end of the voltage comparator U11 and the other input end of the AND gate U16. The output end of the NOT gate U13 and the output end of the NOT gate U15 serve as the two input ends of the AND gate U12 respectively. The output end of the AND gate U12 is connected to one input end of the OR gate U14. The other input end of the OR gate U14 is connected to the output end of the AND gate U16. The output end of the OR gate U14 is connected to one input end of the AND gate U18.

[0038] The structure of the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOR gate U26 is as follows:

[0039] One end of the capacitor C4 is connected to the output end of the voltage comparator U24, the other end of the capacitor C4 is connected in parallel to one end of the resistor and then to an input end of the NOR gate U25, the other end of the resistor R5 is grounded, the other input end of the NOR gate U25 is connected in parallel to the output end of the NOR gate U26 and the input end of the NOR gate U27, the output end of the NOR gate U25 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected in parallel to one end of the resistor R6 and the input end of the NOR gate U26, the other end of the resistor R6 is connected to the power supply, the output end of the NOR gate U27 is connected to the G pole of the switch tube Q7, the D pole of the switch tube Q7 is connected to the power supply, and the S pole of the switch tube Q7 is connected in series with the resistor R7 and then to the ground.

[0040] The differential amplifier circuit structure composed of R1, R2, R3, R4, Q6, and differential amplifier U22A is as follows:

[0041] The non-inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R1 and one end of the resistor R4, the other end of the resistor R1 is connected to one end of the inductor L1 and the capacitor C1, and the other end of the resistor R4 is grounded;

[0042] The inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R2 and one end of the resistor R3. The other end of the resistor R2 is connected in parallel to the output terminal of the differential amplifier U22A, the non-inverting input terminal of the voltage comparator U23, and the non-inverting input terminal of the voltage comparator U24. The other end of the resistor R3 is connected to one end of the inductor L2 connected to the capacitor C2.

[0043] The positive power supply of the differential amplifier U22A is connected to the S pole of the switch tube Q6, the negative power supply of the differential amplifier U22A is grounded, and the D pole of the switch tube Q6 is connected to the power supply.

[0044] The present invention is based on Figure 1 and Figure 2 The process of realizing two pH value detection and comparison by the circuit is as follows: define the connection point between the inductor L1 and the capacitor C1 as A, the connection point between the inductor L2 and the capacitor C2 as B, the G pole of Q1 as point C, the connection point between the G pole of Q1 and the NOT gate U20 as I, the G pole of Q2 as point D, the connection point between the G pole of Q2 and the NOT gate U21 as H, the G pole of Q3 and Q4 connected in parallel as point E, the connection point between the NOT gate U20 and the NOT gate U19 as F, the output end of the OR gate U14 as point G, the connection point between the NOT gate U19 and the inductor L3 as R, the connection point between the inductor L3 and the AND gate U18 as L, the point where the output end of the voltage comparator U3 is connected in parallel with the NOT gate U7 and the AND gate U8 as J, and the point where the voltage comparator U2 is connected in parallel with the NAND gate U5 and the AND gate U8 as K;

[0045] Step 1: The pH sensor starts measuring. Initially, F is at a high level. After passing through the NOT gate U20, the voltage at point C becomes a low level. Q1 is a PMOS switch tube. At this time, Q1 is turned on by the low level at point C. The pH voltage value at this moment is used to charge C1. During this process, the truth table satisfied by the levels at points J and K and the level at point F is shown in Table 1 below.

[0046]

[0047] Table 1 Truth table satisfied by points J, K and F.

[0048] After C1 is fully charged, it outputs a high level at point K through the voltage comparator U2, and the voltage difference across L1 is 0. After passing through the voltage comparison circuit composed of the differential amplifier U28A and the voltage comparator U3, the output voltage at point J is 0. J and K pass through the exclusive OR circuit composed of U4, U5, U6, U7, and U8, and point F becomes a low level.

[0049] Step 2: The switching transistor Q1 changes from the conducting state to the off state, and the voltage at point G remains low from the initial state. When the voltage at point F becomes low, after passing through the inverter U19, the voltage at point R becomes high. At this time, through the delay circuit composed of L3 and C3, after a time T = L3 * C3, the voltage at point L becomes high. At this time, after passing through the AND gate U18 and the NOT gate U21 between G and L, the voltage at point H becomes low, and at this time the PMOS switching transistor Q2 conducts. Use the PH voltage value at this moment to start charging C2. The principle is the same as in Step 1. Finally, the voltage at point G becomes low and Q2 turns off.至此,两次PH电压值采集完毕。The truth table satisfied by points F, G, and H is shown in Table 2. When the voltage at point F is low and the voltage at point G is high, the voltage at point H is low and Q2 will conduct, that is, only when C1 is fully charged will C2 start to charge. If C1 is not fully charged, C2 will not charge.

[0050]

[0051] Table 2. The truth table satisfied by points F, G, and H.

[0052] Step 3: When the two PH value acquisitions are completed, the voltages at points H and I become high. At this time, after passing through the NAND gate U17, the PMOS transistor Q6 conducts and U22A starts to work. The voltages at points A and B are amplified by the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A and then output U1. At this time, there is a high-level output at E, and the NMOS transistors Q3, Q4, and Q5 conduct, causing C1, C2, and C3 to complete discharging.

[0053] Step 4: To determine whether the two measured PH voltage values are greater than the set reference voltage value, U1 needs to pass through a voltage comparator with V1 as the reference voltage. If U1 > V1, the high-level value output at Q is pulse-delay controlled by the monostable flip-flop composed of C4, R5, U25, C5, R6, and U26. During the period when Q maintains a high level, the voltage at point R is low and the PMOS transistor Q7 conducts. At this time, the power supply connecting the microcontroller and the wireless module represented by R7 is on, that is, the microcontroller and the wireless module are powered on and work normally: collect the PH value and send data. If U1 < V1, the output at point Q is low and the PMOS transistor Q7 does not conduct, and the microcontroller and the wireless module lose power and do not collect or send data.

[0054] Step 5: Repeat the above Steps 1 - 4 for cyclic judgment.

[0055] Regarding the specific structure of the present invention, it should be noted that the connection relationship between the various component modules adopted in the present invention is definite and feasible. Except for those specifically described in the embodiments, the specific connection relationship can bring about corresponding technical effects and solve the technical problems raised by the present invention without relying on the execution of corresponding software programs. The components, modules, models of specific components appearing in the present invention, the connection methods between each other, and the conventional usage methods and expected technical effects brought about by the above-mentioned technical features, except for those specifically described, all belong to the disclosed contents in patents, journal articles, technical manuals, technical dictionaries, and textbooks that can be obtained by technical personnel in this field before the application date, or belong to the existing technologies such as conventional technology and common knowledge in this field. There is no need to elaborate, so that the technical solution provided in this case is clear, complete, and feasible, and the corresponding physical products can be reproduced or obtained based on this technical means.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power circuit suitable for wireless detection of pH value of lees, characterized by: It includes two pH value acquisition circuits and two pH value judgment circuits, wherein the two pH value acquisition circuits include two acquisition circuits with exactly the same structure, wherein the two acquisition circuits are respectively provided with switch tubes Q1 and Q2, and Q1 and Q2 can only be turned on at one, and the D poles of Q1 and Q2 are both connected to the voltage value output by the pH sensor, and the S pole of Q1 or Q2 is respectively connected in parallel to one end of the inductor in the respective acquisition circuit, the D pole of Q3 or Q4, and the non-inverting input end of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator, the other end of the inductor is connected in parallel to one end of the capacitor, the inverting input end of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator, and the non-inverting input end of the voltage comparator, and the other end of the capacitor is connected in parallel to the inverting input end of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator. One end is grounded, and the output end of the voltage comparator is connected to the exclusive OR circuit composed of logic gates. The output end of the exclusive OR circuit in the acquisition circuit controlled by Q1 is connected in parallel to the input ends of two NOT gates U20 and U19. The output end of the exclusive OR circuit in the acquisition circuit controlled by Q2 serves as an input end of the AND gate U18. The output end of the NOT gate U20 is connected to the G pole of Q1. The output end of the NOT gate U19 is connected in parallel to the delay circuit composed of capacitor L3 and resistor R3 and then connected to the other input end of the AND gate U18. The output end of the AND gate U18 is connected to the NOT gate U21 and then connected to the G pole of Q2. The S pole of Q5 is also connected between the capacitor L3 and the resistor R3. The G pole of Q5 is connected in parallel to the G pole of Q4 and the G pole of Q3. The D pole of Q5 is grounded. The two pH value judgment circuits include a NAND gate U17, the input ends of the NAND gate U17 are respectively connected to the output ends of the NOT gate U20 and the output ends of U21, the output end of the NAND gate U17 is connected to the G pole of Q6, the non-inverting input ends of the voltage comparison circuit composed of the differential amplifier circuit and the voltage comparator in the two acquisition circuits are respectively used as the two input ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and the differential amplifier U22A, the output ends of the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A are respectively connected to the non-inverting input end of the voltage comparator U24 and the non-inverting input end of the voltage comparator U23, the output end of the voltage comparator U23 is connected to the G pole of Q5, the inverting input end of the voltage comparator U24 is connected to the voltage V1, and the output end of the voltage comparator U24 is connected to the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOT gate U26.

2. A low-power consumption circuit suitable for wireless detection of lees pH according to claim 1, characterized in that: The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R8, R9, R10, R11, a voltage comparator U3, and a differential amplifier U28A in a circuit controlled by Q1, wherein one end of the resistor R8 is grounded, the other end of the resistor R8 is connected in parallel to one end of the resistor R11 and then connected to the non-inverting input end of the differential amplifier U28A, one end of the resistor R9 is connected to the inverting input end of the differential amplifier U28A, the other end of the resistor R9 is connected in parallel to one end of the resistor R10 and then connected to an end connected to the inductor L1 and the capacitor C1, and also serves as the non-inverting input end of the voltage comparator U2, the other end of the resistor R10 is connected in parallel to the output end of the differential amplifier U28A and then connected to the non-inverting input end of the voltage comparator U3, and the inverting input end of the voltage comparator U3 is grounded; The other end of the inductor L1 is connected in parallel to the other end of the resistor R11 , the S pole of the switch tube Q1 , and the D pole of the switch tube Q3 . The S pole of the switch tube Q3 is grounded.

3. A low-power consumption circuit suitable for wireless detection of lees pH according to claim 2, characterized in that: The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q1 includes an AND gate U4, a NOT gate U5, an OR gate U6, a NOT gate U7, and an AND gate U8. The two input ends of the AND gate U4 are respectively connected to the output end of the NOT gate U5 and the output end of the NOT gate U7. The input end of the NOT gate U5 is connected in parallel to the output end of the voltage comparator U2 and one input end of the AND gate U8. The input end of the NOT gate U7 is connected in parallel to the output end of the voltage comparator U3 and the other input end of the AND gate U8. The output end of the NOT gate U5 and the output end of the NOT gate U7 serve as the two input ends of the AND gate U4 respectively. The output end of the AND gate U4 is connected to one input end of the OR gate U6. The other input end of the OR gate U6 is connected to the output end of the AND gate U8. The output end of the OR gate U6 is connected in parallel to the input end of the NOT gate U20 and the input end of the NOT gate U19.

4. A low-power consumption circuit suitable for wireless detection of lees pH according to claim 1, characterized in that: The voltage comparison circuit composed of a differential amplifier circuit and a voltage comparator includes resistors R12, R13, R14, R15, a voltage comparator U11, and a differential amplifier U1A in the circuit controlled by Q2, wherein one end of the resistor R12 is grounded, the other end of the resistor R12 is connected in parallel to one end of the resistor R13 and then connected to the non-inverting input end of the differential amplifier U1A, one end of the resistor R14 is connected in parallel to one end of the resistor R15 and then connected to the inverting input end of the differential amplifier U1A, the other end of the resistor R14 is connected in parallel to one end of the resistor R10 and then connected to one end connected to the inductor L2 and the capacitor C2, and also serves as the non-inverting input end of the voltage comparator U10, the other end of the resistor R15 is connected in parallel to the output end of the differential amplifier U1A and then connected to the non-inverting input end of the voltage comparator U11, and the inverting input end of the voltage comparator U11 is grounded; The other end of the inductor L2 is connected in parallel to the other end of the resistor R13, the S pole of the switch tube Q2, and the D pole of the switch tube Q4. The S pole of the switch tube Q4 is grounded.

5. A low-power consumption circuit suitable for wireless detection of lees pH according to claim 4, characterized in that: The circuit structure of the exclusive-OR circuit composed of logic gates in the acquisition circuit controlled by Q2 includes an AND gate U12, a NOT gate U13, an OR gate U14, a NOT gate U15, and an AND gate U16. The two input ends of the AND gate U12 are respectively connected to the output end of the NOT gate U13 and the output end of the NOT gate U15. The input end of the NOT gate U13 is connected in parallel to the output end of the voltage comparator U10 and one input end of the AND gate U16. The input end of the NOT gate U15 is connected in parallel to the output end of the voltage comparator U11 and the other input end of the AND gate U16. The output end of the NOT gate U13 and the output end of the NOT gate U15 serve as the two input ends of the AND gate U12 respectively. The output end of the AND gate U12 is connected to one input end of the OR gate U14. The other input end of the OR gate U14 is connected to the output end of the AND gate U16. The output end of the OR gate U14 is connected to one input end of the AND gate U18.

6. A low-power circuit suitable for wireless detection of lees pH according to claim 3 or 5, characterized in that: The structure of the monostable trigger pulse delay control circuit composed of capacitor C4, resistor R5, NOR gate U25, capacitor C5, resistor R6, and NOR gate U26 is as follows: One end of the capacitor C4 is connected to the output end of the voltage comparator U24, the other end of the capacitor C4 is connected in parallel to one end of the resistor and then to an input end of the NOR gate U25, the other end of the resistor R5 is grounded, the other input end of the NOR gate U25 is connected in parallel to the output end of the NOR gate U26 and the input end of the NOR gate U27, the output end of the NOR gate U25 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected in parallel to one end of the resistor R6 and the input end of the NOR gate U26, the other end of the resistor R6 is connected to the power supply, the output end of the NOR gate U27 is connected to the G pole of the switch tube Q7, the D pole of the switch tube Q7 is connected to the power supply, and the S pole of the switch tube Q7 is connected in series with the resistor R7 and then to the ground.

7. A low-power consumption circuit suitable for wireless detection of lees pH according to claim 6, characterized in that: The differential amplifier circuit structure composed of R1, R2, R3, R4, Q6, and differential amplifier U22A is as follows: The non-inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R1 and one end of the resistor R4, the other end of the resistor R1 is connected to one end of the inductor L1 and the capacitor C1, and the other end of the resistor R4 is grounded; The inverting input terminal of the differential amplifier U22A is connected in parallel to one end of the resistor R2 and one end of the resistor R3. The other end of the resistor R2 is connected in parallel to the output terminal of the differential amplifier U22A, the non-inverting input terminal of the voltage comparator U23, and the non-inverting input terminal of the voltage comparator U24. The other end of the resistor R3 is connected to one end of the inductor L2 connected to the capacitor C2. The positive power supply of the differential amplifier U22A is connected to the S pole of the switch tube Q6, the negative power supply of the differential amplifier U22A is grounded, and the D pole of the switch tube Q6 is connected to the power supply.

8. A control method for a low-power circuit suitable for wireless detection of distiller's grains pH, employing the low-power circuit suitable for wireless detection of distiller's grains pH as claimed in claim 7, wherein the connection point between inductor L1 and capacitor C1 is defined as A, the connection point between inductor L2 and capacitor C2 is defined as B, the G pole of Q1 is defined as point C, the connection point between the G pole of Q1 and NOT gate U20 is defined as I, the G pole of Q2 is defined as point D, the connection point between the G pole of Q2 and NOT gate U21 is defined as H, the G poles of Q3 and Q4 connected in parallel is defined as point E, the connection point between NOT gate U20 and NOT gate U19 is defined as F, the output end of OR gate U14 is defined as point G, the connection point between NOT gate U19 and inductor L3 is defined as R, the connection point between inductor L3 and AND gate U18 is defined as L, the point where the output end of voltage comparator U3 is connected in parallel with NOT gates U7 and U8 is defined as J, and the point where voltage comparator U2 is connected in parallel with NOT gates U5 and U8 is defined as K. Its characteristics are: The steps include: Step 1: The pH sensor starts measuring. In the initial state, F is at a high level. After passing through the NOT gate U20, the voltage at point C becomes a low level. At this time, Q1 is turned on by the low level at point C. The pH voltage at this moment starts to charge C1. After C1 is fully charged, it outputs a high level at point K through the voltage comparator U2. The voltage difference between both ends of L1 is 0. After passing through the voltage comparison circuit composed of the differential amplifier U28A and the voltage comparator U3, the output voltage at point J is 0. J and K pass through the exclusive OR circuit composed of U4, U5, U6, U7, and U8. At this time, point F becomes a low level. Step 2: The switch tube Q1 changes from on to off, and the voltage at point G remains low from the initial state. When point F changes to a low level, point R changes to a high level after passing through the NOT gate U19. At this time, after passing through the delay circuit composed of L3 and C3, point L changes to a high level after a time T=L3C3. At this time, after G and L pass through the AND gate U18 and the NOT gate U21, point H changes to a low level, and the switch tube Q2 turns on. The pH voltage value at this moment starts to charge C2. The principle is the same as step 1. Finally, point G changes to a low level and Q2 turns off. At this point, the two pH voltage value acquisitions are completed. Step 3: After the two pH value acquisitions are completed, the voltages at points H and I become high. At this time, after passing through the NAND gate U17, Q6 is turned on, and the differential amplifier U22A starts working. The voltages at points A and B are amplified by the differential amplifier circuit composed of R1, R2, R3, R4, Q6, and U22A, and then output to U1. At this time, E has a high-level output, and the NMOS tubes Q3, Q4, and Q5 are turned on, completing the discharge of C1, C2, and C3. Step 4: To determine whether the two measured PH voltage values are greater than the set reference voltage value, U1 needs to pass through a voltage comparator U24 with V1 as the reference voltage. If U1 > V1, the high-level value output at Q is pulse-delay controlled by a monostable flip-flop composed of C4, R5, U25, C5, R6, and U26. During the period when Q maintains a high level, the R point is at a low level, and the PMOS transistor Q7 conducts. At this time, the power supply connecting the microcontroller and the wireless module represented by R7 is on, that is, the microcontroller and the wireless module are powered on and work normally: collect PH values and send data; If U1 < V1, the Q point outputs a low level, the PMOS transistor Q7 does not conduct, and the microcontroller and the wireless module are powered off and do not collect or send data; Step 5: Repeat the above steps 1-4 for cyclic judgment.

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