A driving circuit and a display panel

Abstract

The present application discloses a driving circuit and a display panel, the driving circuit comprising: a signal input circuit writes a first level signal based on a first write signal at a corresponding timing, or writes a second level signal based on a second write signal; the control end of the first switch tube is connected to the output end of the signal input circuit, and the first end receives a clock signal; a boost circuit is used to boost the first write signal or the second write signal; a mixing circuit is connected to the boost circuit and the second end of the first switch tube, and is used to receive a DC signal, wherein a first node is formed between the second end of the first switch tube and the mixing circuit, and the DC signal and the clock signal are superimposed at the first node to obtain a driving output signal output by the driving circuit. The present application adds a mixing circuit so that the output driving output signal is formed by superimposing the clock signal and the DC signal, which can improve the pre-charging effect of the driving circuit under low temperature conditions, and the output of the driving output signal is more stable.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display panel. Background Art

[0002] With the rapid development of science and technology, electronic products have undergone tremendous changes. With the recent advent of touch-screen electronic products, touch-screen products have become increasingly popular. They not only save space and are easy to carry, but also can be directly operated by users with fingers or styluses, making them comfortable and convenient to use. Among many touch-screen products, liquid crystal panels are usually used as corresponding display panels, and the charging ratio is an important indicator of liquid crystal panels, and its size directly affects the display performance of liquid crystal panels such as brightness, penetration, and image quality. The evaluation method of the charging ratio of liquid crystal panels has been under continuous discussion by all parties.

[0003] Most of the LCD panels in the prior art use GDL (Gate Driver Less) circuits for display driving. Different temperatures will also have a certain impact on the output of the GDL circuit. Under high temperature and normal temperature conditions, the output effect will be better, while under low temperature conditions, the pre-charge will be poor and the output waveform will also be poor. Summary of the invention

[0004] The present application at least provides a driving circuit and a display panel to solve the problem of GDL circuit pre-charge difference and output waveform difference under low temperature conditions.

[0005] A first aspect of the present application provides a driving circuit, the driving circuit comprising:

[0006] A signal input circuit, used for receiving a first level signal, a second level signal, a first write signal and a second write signal, and writing a corresponding first level signal based on the first write signal or writing a corresponding second level signal based on the second write signal at a corresponding timing; wherein the first level signal and the second level signal are clock signals with opposite level states;

[0007] A first switch tube, wherein a control end of the first switch tube is connected to an output end of the signal input circuit, and a first end of the first switch tube receives a clock signal;

[0008] A boost circuit, connected between the output end of the signal input circuit and the control end of the first switch tube, for boosting the first write signal or the second write signal to obtain a start voltage, and the start voltage is used to control the first switch tube to conduct;

[0009] The voltage mixing circuit is connected between the boost circuit and the second end of the first switch tube, and is used to receive a DC signal, wherein a first node is formed between the second end of the first switch tube and the voltage mixing circuit, and the DC signal and the clock signal are superimposed at the first node to obtain a driving output signal output by the driving circuit.

[0010] Optionally, the mixing circuit includes a second switch tube, the control end of the second switch tube is connected to the boost circuit to receive a starting voltage and is turned on based on the starting voltage, the first end of the second switch tube receives a DC signal, and the second end of the second switch tube is connected to the first node.

[0011] Optionally, the boost circuit includes a bootstrap capacitor, a first end of the bootstrap capacitor is connected to the output end of the signal input circuit, the control end of the second switch tube and the control end of the first switch tube, and a second end of the bootstrap capacitor is connected to the second end of the second switch tube.

[0012] Optionally, a second node is formed between the first end of the bootstrap capacitor, the output end of the signal input circuit, the control end of the second switch tube, and the control end of the first switch tube. The bootstrap capacitor receives a DC signal and charges, and when the first write signal or the second write signal is transmitted to the second node, the voltage of the second node is adjusted to a starting voltage.

[0013] Optionally, the driving circuit further includes a reset circuit, and the reset circuit includes a third switch tube and a fourth switch tube;

[0014] The first end of the third switch tube is connected to the first node, and the control end of the third switch tube receives a first reset signal to reset the voltage of the first node to a zero level based on the first reset signal;

[0015] The first end of the fourth switch tube is connected to the second node, and the control end of the fourth switch tube receives the second reset signal to reset the voltage of the second node to a zero level based on the second reset signal.

[0016] Optionally, the driving circuit further includes a voltage clamping circuit, and the voltage clamping circuit includes a fifth switch tube, a sixth switch tube and a seventh switch tube;

[0017] A first end of the fifth switch tube is connected to a second end of the third switch tube, a second end of the fifth switch tube is connected to a second end of the seventh switch tube, a control end of the fifth switch tube is connected to a second node, a first end of the sixth switch tube is connected to a second end of the fourth switch tube, a second end of the sixth switch tube is connected to a control end and a first end of the seventh switch tube, a control end of the sixth switch tube is connected to a control end of the fifth switch tube, and a first end of the seventh switch tube receives a high level signal;

[0018] A third node is formed between the second end of the fifth switch tube and the second end of the seventh switch tube, and the potentials of the third node and the second node are clamped to each other.

[0019] Optionally, the driving circuit further includes a noise reduction circuit, and the noise reduction circuit includes an eighth switch tube and a ninth switch tube.

[0020] A first end of the eighth switch tube is connected to the first node, a second end of the eighth switch tube is connected to the first end of the ninth switch tube, a control end of the eighth switch tube is connected to the control end of the ninth switch tube and the third node, and a second end of the ninth switch tube is connected to the second node;

[0021] Among them, a fourth node is formed between the second end of the eighth switch tube and the first end of the ninth switch tube, a fifth node is formed between the first end of the fifth switch tube and the second end of the third switch tube, and a sixth node is formed between the first end of the sixth switch tube and the second end of the fourth switch tube. The fourth node, the fifth node and the sixth node respectively receive noise reduction signals to filter out noise signals in the first write signal, the second write signal, the DC signal and / or the clock signal.

[0022] Optionally, the signal input circuit includes a tenth switch tube and an eleventh switch tube,

[0023] The first end of the tenth switch tube receives a first level signal, the control end of the tenth switch tube receives a first write signal, the first end of the eleventh switch tube receives a second level signal, the control end of the eleventh switch tube receives a second write signal, and the second end of the tenth switch tube is connected to the second end of the eleventh switch tube and the second node.

[0024] Optionally, the first level signal is a high level signal, and the second level signal is a low level signal;

[0025] At the first timing, the tenth switch tube is turned on and writes the first write signal, and the level of the first node is a high level;

[0026] In the second timing, the eleventh switch is turned on and writes the second write signal, and the level of the first node is low level;

[0027] Alternatively, the first level signal is a low level signal, and the second level signal is a high level signal;

[0028] At the first timing, the tenth switch tube is turned on and writes the first write signal, and the level of the first node is low level;

[0029] In the second timing, the eleventh switch tube is turned on and writes the second write signal, and the level of the first node is a high level;

[0030] A clock cycle includes at least one first timing sequence and at least one second timing sequence, and the first timing sequence and the second timing sequence are cyclical.

[0031] A second aspect of the present application provides a display panel, which includes a substrate and a multi-level driving circuit as described above, wherein the substrate includes a display area, and the multi-level driving circuit array is arranged in the display area of ​​the substrate; wherein the driving output signal of the driving circuit serves as a write signal for the next-level driving circuit.

[0032] Different from the prior art, the present application sets a mixing circuit connected between the boost circuit and the second end of the first switching tube so that the driving output signal finally output by the driving circuit is composed of the superposition of the clock signal and the DC signal, which can improve the pre-charging effect of the driving circuit under low temperature conditions and make the output of the driving output signal more stable.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a schematic structural diagram of a first embodiment of a driving circuit of the present application;

[0036] Figure 2 is a schematic structural diagram of a second embodiment of the driving circuit of the present application;

[0037] Figure 3 It is a waveform diagram of the first node of the present application;

[0038] Figure 4 is a waveform diagram of the second node of the present application;

[0039] Figure 5 It is a schematic structural diagram of an embodiment of a display panel of the present application. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solution of the present application, the driving circuit and the display panel provided by the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It can be understood that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0041] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0042] The present application provides a driving circuit to solve the problems of GDL circuit pre-charge difference and output waveform difference under low temperature conditions in the prior art.

[0043] See also Figure 1 , Figure 1 Schematic diagram of the structure of the first embodiment of the driving circuit of the present application. Figure 1 As shown, the driving circuit 10 of this embodiment includes a signal input circuit 11, a boost circuit 12, a mixing circuit 13 and a first switch tube T1.

[0044] Specifically, the signal input circuit 11 is used to receive a first level signal VDS, a second level signal VSD, a first write signal GN-8, and a second write signal GN+8, so as to write the corresponding first level signal VDS based on the first write signal GN-8 at the corresponding timing, or write the corresponding second level signal VSD based on the second write signal GN+8. The first level signal VDS and the second level signal VSD are clock signals with opposite level states, that is, when the first level signal VDS is at a high level, the second level signal VSD is at a low level; or when the first level signal VDS is at a low level, the second level signal VSD is at a high level. The level states of the first level signal VDS and the second level signal VSD can be changed according to different timing signals of the driving circuit 10.

[0045] The control end of the first switch tube T1 is connected to the output end of the signal input circuit 11 , the first end of the first switch tube T1 receives the clock signal CLK, and the clock signal CLK is output from the second end of the first switch tube T1 .

[0046] Optionally, in this embodiment, the first switch tube T1 is a TFT (Thin Film Transistor), and the control end, the first end and the second end of the first switch tube T1 are respectively the gate, the source and the drain of the first switch tube T1. Optionally, in other embodiments, the first switch tube T1 may also be a triode or other switch element.

[0047] The boost circuit 12 is connected between the output end of the signal input circuit 11 and the control end of the first switch tube T1, and is used to boost the first write signal GN-8 or the second write signal GN+8 to obtain a start voltage, which is used to control the first switch tube T1 to turn on.

[0048] The voltage mixing circuit 13 is connected between the voltage boosting circuit 12 and the second end of the first switch tube T1 , and is used for receiving the DC signal VDC.

[0049] In this embodiment, a first node a is formed between the second end of the first switch tube T1 and the voltage mixing circuit 13 , and the DC signal VDC and the clock signal CLK are superimposed at the first node a to obtain a driving output signal GN output by the driving circuit 10 .

[0050] Specifically, the driving circuit 10 described in this embodiment is a level transmission control system, specifically an 8-level level transmission control system. The driving signal output by the driving circuit 10 in this embodiment is eight-level one-transmission, that is, the driving output signal GN output by the first level can be used as the write signal of the ninth level.

[0051] Optionally, in other embodiments, the driving circuit 10 may also perform 4-stage transmission, and control the corresponding stage to output the corresponding driving output signal GN according to the corresponding timing signal of the driving circuit 10 .

[0052] Combination Figure 1 , see further Figure 2 , Figure 2 Schematic diagram of the structure of the second embodiment of the driving circuit of the present application. Figure 2 As shown, the voltage mixing circuit 13 of this embodiment includes a second switch tube T2, the control end of the second switch tube T2 is connected to the boost circuit 12 to receive the startup voltage, and the second switch tube T2 is turned on based on the startup voltage, the first end of the second switch tube T2 receives the DC signal VDC, and the second end of the second switch tube T2 is connected to the first node a.

[0053] The boost circuit 12 includes a bootstrap capacitor C, a first end of the bootstrap capacitor C is connected to the output end of the signal input circuit 11, the control end of the second switch tube T2 and the control end of the first switch tube T1, and a second end of the bootstrap capacitor C is connected to the second end of the second switch tube T2 and the second end of the first switch tube T1.

[0054] Optionally, in this embodiment, the second switch tube T2 is a TFT, and the control end, the first end and the second end of the second switch tube T2 are respectively the gate, the source and the drain of the second switch tube T2.

[0055] Specifically, a second node b is formed between the first end of the bootstrap capacitor C, the output end of the signal input circuit 11, the control end of the second switch tube T2, and the control end of the first switch tube T1. The bootstrap capacitor C receives the DC signal VDC and charges it, and when the first write signal GN-8 or the second write signal GN+8 is transmitted to the second node b, the voltage of the second node b is adjusted to the start-up voltage. That is, this embodiment realizes the bootstrap of the second node b through the bootstrap function of the bootstrap capacitor C, and raises the voltage value of the second node b so that its voltage value reaches the start-up voltage of the first switch tube T1 and the second switch tube T2.

[0056] like Figure 2 As shown, the driving circuit 10 further includes a reset circuit 14, and the reset circuit 14 includes a third switch tube T3 and a fourth switch tube T4.

[0057] Specifically, the first end of the third switch tube T3 is connected to the first node a, and the control end of the third switch tube T3 receives the first reset signal STV5 to reset the voltage of the first node a to zero level based on the first reset signal STV5.

[0058] A first end of the fourth switch tube T4 is connected to the second node b, and a control end of the fourth switch tube T4 receives the second reset signal STV0 to reset the voltage of the second node b to zero level based on the second reset signal STV0.

[0059] Optionally, in this embodiment, the third switch tube T3 and the fourth switch tube T4 are both TFTs, and the control end, the first end and the second end of the third switch tube T3 and the fourth switch tube T4 are the gate, the source and the drain of the third switch tube T3 and the fourth switch tube T4 respectively.

[0060] like Figure 2 As shown, the driving circuit 10 further includes a voltage clamping circuit 15, and the voltage clamping circuit 15 includes a fifth switch tube T5, a sixth switch tube T6 and a seventh switch tube T7.

[0061] Specifically, a first end of the fifth switch tube T5 is connected to the second end of the third switch tube T3, a second end of the fifth switch tube T5 is connected to the second end of the seventh switch tube T7, a control end of the fifth switch tube T5 is connected to the second node b, a first end of the sixth switch tube T6 is connected to the second end of the fourth switch tube T4, a second end of the sixth switch tube T6 is connected to the control end and the first end of the seventh switch tube T7, a control end of the sixth switch tube T6 is connected to the control end of the fifth switch tube T5, that is, connected to the second node b, and a first end of the seventh switch tube T7 receives the high level signal OCH.

[0062] Among them, a third node c is formed between the second end of the fifth switch tube T5 and the second end of the seventh switch tube T7, and the potentials of the third node c and the second node b are mutually clamped. Specifically, it can be understood that when the second node b is at a low level, the seventh switch tube T7 is not turned on, and at this time the voltage of the third node c is equal to the high-level signal OCH, that is, the third node c is at a high level; when the second node b is at a high level, the seventh switch tube T7 is turned on, and at this time the third node c is suspended, that is, the third node c is at a low level.

[0063] Optionally, in this embodiment, the fifth switch tube T5, the sixth switch tube T6 and the seventh switch tube T7 are all TFTs, the control end, the first end and the second end of the fifth switch tube T5 are respectively the gate, the source and the drain of the fifth switch tube T5, the control end, the first end and the second end of the sixth switch tube T6 are respectively the gate, the source and the drain of the sixth switch tube T6, and the control end, the first end and the second end of the seventh switch tube T7 are respectively the gate, the drain and the source of the seventh switch tube T7.

[0064] like Figure 2 As shown, the driving circuit 10 further includes a noise reduction circuit 16, and the noise reduction circuit 16 includes an eighth switch tube T8 and a ninth switch tube T9.

[0065] Specifically, the first end of the eighth switch tube T8 is connected to the first node a, the second end of the eighth switch tube T8 is connected to the first end of the ninth switch tube T9, the control end of the eighth switch tube T8 is connected to the control end of the ninth switch tube T9 and the third node c, and the second end of the ninth switch tube T9 is connected to the second node b.

[0066] Among them, a fourth node d is formed between the second end of the eighth switch tube T8 and the first end of the ninth switch tube T9, a fifth node e is formed between the first end of the fifth switch tube T5 and the second end of the third switch tube T3, and a sixth node f is formed between the first end of the sixth switch tube T6 and the second end of the fourth switch tube T4. The fourth node d, the fifth node e and the sixth node f respectively receive the noise reduction signal VCL to filter out noise signals in the first write signal GN-8, the second write signal GN+8, the DC signal VDS and / or the clock signal CLK.

[0067] Optionally, in this embodiment, the eighth switch tube T8 and the ninth switch tube T9 are both TFTs, and the control end, the first end and the second end of the eighth switch tube T8 and the ninth switch tube T9 are the gate, the source and the drain of the eighth switch tube T8 and the ninth switch tube T9 respectively.

[0068] like Figure 2As shown, the signal input circuit 11 includes a tenth switch tube T10 and an eleventh switch tube T11. Specifically, a first end of the tenth switch tube T10 receives a first level signal VDS, a control end of the tenth switch tube T10 receives a first write signal GN-8, a first end of the eleventh switch tube T11 receives a second level signal VSD, a control end of the eleventh switch tube T11 receives a second write signal GN+8, and a second end of the tenth switch tube T10 is connected to a second end of the eleventh switch tube T11 and a second node b.

[0069] Optionally, in this embodiment, the tenth switch tube T10 and the eleventh switch tube T11 are both TFTs, and the control end, the first end and the second end of the tenth switch tube T10 and the eleventh switch tube T11 are the gate, the source and the drain of the tenth switch tube T10 and the eleventh switch tube T11 respectively.

[0070] Since the driving circuit 10 described in this embodiment sets the level states of the first level signal VDS and the second level signal VSD based on different timing signals, the level states of the second node b connected to the output end of the signal input circuit 11 are also different at different timings.

[0071] For example, when the first level signal VDS is a high level signal and the second level signal VSD is a low level signal, in the first timing sequence, the tenth switch tube T10 is turned on and writes the first write signal GN-8, and the level of the second node b is a high level; in the second timing sequence, the eleventh switch tube T11 is turned on and writes the second write signal GN+8, and the level of the second node b is a low level.

[0072] Alternatively, when the first level signal VDS is a low level signal and the second level signal VSD is a high level signal, in the first timing sequence, the tenth switch tube T10 is turned on and writes the first write signal GN-8, and the level of the second node b is a low level; in the second timing sequence, the eleventh switch tube T11 is turned on and writes the second write signal GN+8, and the level of the second node b is a high level.

[0073] Optionally, one clock cycle of the timing signal received by the driving circuit 10 of this embodiment includes at least one first timing and at least one second timing, and the first timing and the second timing are cyclical.

[0074] The driving circuit 10 of the present application controls the overall level transmission relationship of the driving circuit 10 through the tenth switch tube T10 and the eleventh switch tube T11 of the signal input circuit 11, and specifically performs switch control through the first level signal VDS and the second level signal VSD; when the signal output by the signal input circuit 11 is at a high level, the second node b is bootstrapped through the bootstrap capacitor C, and the first switch tube T1 and the second switch tube T2 are turned on, so that the driving output signal GN finally output by the driving circuit 10 is formed by the superposition of the clock signal CLK and the DC signal VDS, which can improve the pre-charging effect of the driving circuit 10 under low temperature conditions, and the output of the driving output signal GN is more stable.

[0075] Since the driving circuit 10 of this embodiment is used to solve the problem of GDL circuit pre-charge difference and output waveform difference under low temperature conditions in the prior art, the corresponding waveform diagram of the first node a and the second node b of the driving circuit 10 before and after the mixing circuit 13 is added can be obtained by testing at a low temperature of -20°C. Figure 1 and Figure 2 , see further Figure 3 and Figure 4 , Figure 3 is a waveform diagram of the first node of this application, Figure 4 This is a waveform diagram of the second node of this application.

[0076] like Figure 3 As shown, curve S1 is a waveform diagram of the first node a before the voltage mixing circuit 13 is added to the driving circuit 10, and curve S2 is a waveform diagram of the first node a after the voltage mixing circuit 13 is added to the driving circuit 10. Comparing curve S1 and curve S2, it can be seen that after the voltage mixing circuit 13 is added, the driving output signal output by the original driving circuit 10 is decomposed into a component associated with the output of the DC signal VDS and a component associated with the output of the clock signal CLK, which can make the output driving output signal GN reach the maximum voltage value faster, and its duration at the maximum voltage value is also increased, that is, the output driving output signal GN is closer to the square wave signal, and its output effect is significantly enhanced, and the output stability is also significantly enhanced.

[0077] like Figure 4 As shown, curve S3 is a waveform diagram of the second node b before the driving circuit 10 is not added with the voltage mixing circuit 13, and curve S4 is a waveform diagram of the second node b after the driving circuit 10 is added with the voltage mixing circuit 13. Comparing curve S3 and curve S4, it can be seen that after adding the voltage mixing circuit 13, the second node b can be boosted to a voltage greater than the original pre-charge voltage value in the pre-charge stage, thereby improving the pre-charge effect; and in the bootstrap stage, the waveform of curve S4 is also more stable than that of curve S3, thereby improving the bootstrap effect.

[0078] Optionally, the voltage value of the driving output signal GN can be recorded as Z, the voltage value of the component output by the associated DC signal VDS can be recorded as X, and the voltage value of the component output by the associated clock signal CLK can be recorded as Y. The values ​​of X and Y are limited. The size of the first switch tube T1 of the clock signal CLK needs to ensure that the driving circuit 10 can work normally. The specific value is 1900, and the size of the second switch tube T2 can be 20.

[0079] The present application also provides a display panel, see Figure 5 , Figure 5 Schematic diagram of the structure of a display panel according to an embodiment of the present application. Figure 5 As shown, the display panel 20 of this embodiment includes a substrate 21 and a multi-stage driving circuit 22, wherein the substrate 21 includes a display area 211, and the multi-stage driving circuit 22 is arrayed in the display area 211 of the substrate 21. The driving circuit 22 is the driving circuit 10 described in any of the above embodiments, which will not be described in detail here.

[0080] Specifically, the driving output signal GN of the driving circuit 22 is used as a write signal of the next-stage driving circuit 22. For example, the driving output signal GN output by the first-stage driving circuit 22 can be used as a write signal of the fifth-stage driving circuit 22, the driving output signal GN output by the second-stage driving circuit 22 can be used as a write signal of the sixth-stage driving circuit 22, the driving output signal GN output by the third-stage driving circuit 22 can be used as a write signal of the seventh-stage driving circuit 22, the driving output signal GN output by the fourth-stage driving circuit 22 can be used as a write signal of the eighth-stage driving circuit 22, and so on.

[0081] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving circuit, characterized in that: The driving circuit comprises: A signal input circuit, configured to receive a first level signal, a second level signal, a first write signal, and a second write signal, and to write the first level signal corresponding to the first write signal at a corresponding timing, or to write the second level signal corresponding to the second write signal based on the second write signal; wherein the first level signal and the second level signal are clock signals with opposite level states; A first switch tube, wherein a control end of the first switch tube is connected to an output end of the signal input circuit, and a first end of the first switch tube receives a clock signal; a boost circuit, connected between the output end of the signal input circuit and the control end of the first switch tube, for boosting the first write signal or the second write signal to obtain a start voltage, and the start voltage is used to control the first switch tube to conduct; a voltage mixing circuit, connected between the boost circuit and the second end of the first switch tube, and used to receive a DC signal, wherein a first node is formed between the second end of the first switch tube and the voltage mixing circuit, and the DC signal and the clock signal are superimposed at the first node to obtain a driving output signal output by the driving circuit; The mixing circuit includes a second switch tube, a control end of the second switch tube is connected to the boost circuit to receive the start-up voltage and is turned on based on the start-up voltage, a first end of the second switch tube receives the DC signal, and a second end of the second switch tube is connected to the first node.

2. The driving circuit according to claim 1, characterized in that: The boost circuit includes a bootstrap capacitor, a first end of the bootstrap capacitor is connected to the output end of the signal input circuit, the control end of the second switch tube and the control end of the first switch tube, and a second end of the bootstrap capacitor is connected to the second end of the second switch tube.

3. The driving circuit according to claim 2, characterized in that: A second node is formed between the first end of the bootstrap capacitor, the output end of the signal input circuit, the control end of the second switch tube, and the control end of the first switch tube. The bootstrap capacitor receives the DC signal and charges it, and when the first write signal or the second write signal is transmitted to the second node, the voltage of the second node is adjusted to the start-up voltage.

4. The driving circuit according to claim 3, characterized in that: The driving circuit further includes a reset circuit, and the reset circuit includes a third switch tube and a fourth switch tube; The first end of the third switch tube is connected to the first node, and the control end of the third switch tube receives a first reset signal to reset the voltage of the first node to a zero level based on the first reset signal; The first end of the fourth switch tube is connected to the second node, and the control end of the fourth switch tube receives a second reset signal to reset the voltage of the second node to a zero level based on the second reset signal.

5. The driving circuit according to claim 4, characterized in that: The driving circuit further includes a voltage clamping circuit, and the voltage clamping circuit includes a fifth switch tube, a sixth switch tube and a seventh switch tube; The first end of the fifth switch tube is connected to the second end of the third switch tube, the second end of the fifth switch tube is connected to the second end of the seventh switch tube, the control end of the fifth switch tube is connected to the second node, the first end of the sixth switch tube is connected to the second end of the fourth switch tube, the second end of the sixth switch tube is connected to the control end and the first end of the seventh switch tube, the control end of the sixth switch tube is connected to the control end of the fifth switch tube, and the first end of the seventh switch tube receives a high level signal; A third node is formed between the second end of the fifth switch tube and the second end of the seventh switch tube, and potentials of the third node and the second node are clamped to each other.

6. The driving circuit according to claim 5, characterized in that: The driving circuit further includes a noise reduction circuit, and the noise reduction circuit includes an eighth switch tube and a ninth switch tube. The first end of the eighth switch tube is connected to the first node, the second end of the eighth switch tube is connected to the first end of the ninth switch tube, the control end of the eighth switch tube is connected to the control end of the ninth switch tube and the third node, and the second end of the ninth switch tube is connected to the second node; Among them, a fourth node is formed between the second end of the eighth switch tube and the first end of the ninth switch tube, a fifth node is formed between the first end of the fifth switch tube and the second end of the third switch tube, and a sixth node is formed between the first end of the sixth switch tube and the second end of the fourth switch tube. The fourth node, the fifth node and the sixth node respectively receive noise reduction signals to filter out noise signals in the first write signal, the second write signal, the DC signal and / or the clock signal.

7. The driving circuit according to claim 3, characterized in that: The signal input circuit includes a tenth switch tube and an eleventh switch tube, The first end of the tenth switch tube receives the first level signal, the control end of the tenth switch tube receives the first write signal, the first end of the eleventh switch tube receives the second level signal, the control end of the eleventh switch tube receives the second write signal, and the second end of the tenth switch tube is connected to the second end of the eleventh switch tube and the second node.

8. The driving circuit according to claim 7, characterized in that: The first level signal is a high level signal, and the second level signal is a low level signal; At a first timing, the tenth switch tube is turned on and the first write signal is written, and the level of the second node is a high level; In the second timing, the eleventh switch tube is turned on and the second write signal is written, and the level of the second node is a low level; Alternatively, the first level signal is a low level signal, and the second level signal is a high level signal; At a first timing, the tenth switch tube is turned on and writes the first write signal, and the level of the second node is a low level; In the second timing, the eleventh switch tube is turned on and the second write signal is written, and the level of the second node is a high level; Wherein, one clock cycle includes at least one of the first timing and at least one of the second timing, and the first timing and the second timing are cyclical.

9. A display panel, characterized in that: The display panel includes a substrate and a multi-level driving circuit as described in any one of claims 1 to 8, wherein the substrate includes a display area, and the multi-level driving circuit array is arranged in the display area of ​​the substrate; wherein the driving output signal of the driving circuit serves as a write signal of the driving circuit of the next level.

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