Duplexer and method of manufacturing the same, and multiplexer

Abstract

The application provides a duplexer, comprising: a package substrate and a stack structure arranged on the package substrate; the stack structure comprises a substrate, N device layers and a signal leading-out structure, the N device layers are longitudinally stacked on the substrate, each device layer comprises a device region and a cap structure, N is an integer and N>=2; for the device layer directly formed on the substrate, the device region and the substrate jointly form one or more resonators; for the device layer not directly formed on the substrate, the device region and the cap structure in the adjacent device layer jointly form one or more resonators; a cavity is formed between the cap structure and the device region in each device layer; the resonators in the stack structure are used for constructing a transmitting filter and a receiving filter; and the signal leading-out structure leads out the signals in the stack structure to the outside. The application also provides a manufacturing method of the duplexer and a multiplexer. Implementing the application is beneficial to reducing the module area of the duplexer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a duplexer and its manufacturing method, as well as a multiplexer. Background Technology

[0002] A duplexer is a device that connects the transmit path and the receive path to a single or common antenna without mutual interference. It is currently widely used in many fields such as mobile communication, microwave navigation, microwave communication, satellite communication, telemetry and remote control.

[0003] Please refer to Figure 1 , Figure 1This is a cross-sectional schematic diagram of an existing duplexer. As shown, the duplexer includes a package substrate 3 and a transmitting filter 1 and a receiving filter 2 disposed on the package substrate 3. The transmitting filter 1 and the receiving filter 2 are two independent devices, which are disposed on the package substrate in a tiled manner. For the transmitting filter 1, the resonators are arranged in a tiled manner. Specifically, the transmitting filter 1 includes a filter chip, a cap 15, a first bonding portion 17a, a second bonding portion 17b, a conductive via 16, and solder balls 18. The filter chip includes a substrate 10 and a device region formed on the substrate 10. The device region includes multiple stacked structures (only two stacked structures are schematically shown in the figure, and the connection between the stacked structures is omitted) and acoustic reflection structures corresponding to each stacked structure. In this embodiment, each stacked structure includes a lower electrode 11, a piezoelectric layer 12, and an upper electrode 13. The acoustic reflection structure corresponding to each stacked structure is an air gap 14 formed between the stacked structure and the substrate 10. The lower electrode 11, piezoelectric layer 12, and upper electrode 13 in each stacked structure overlap with their corresponding air gaps 14 in the device thickness direction. Each stacked structure, along with its corresponding air gap 14 and a corresponding portion of the substrate 10, constitutes a resonator (in this embodiment, a bulk acoustic resonator). The cap 15 is connected to the substrate 10 in the filter chip via a first bonding portion 17a and a second bonding portion 17b. The substrate 10, the cap 15, and the first bonding portion 17a form a cavity, sealing the device area on the substrate 10 within this cavity. The second bonding portion 17b is electrically connected to the device area. A conductive via 16 penetrates the cap 15 and connects to the second bonding portion 17b, thereby enabling the signal from the device area in the filter chip to be routed to the outside of the transmitting filter 1. Solder balls 18 are formed on the back of the cap 15 and electrically connected to the conductive via 16, and the transmitting filter 1 is connected to the package substrate 3 through the solder balls 18. The same applies to the receiving filter 2, and for the sake of simplicity, the structure of the receiving filter 2 will not be described again here. In order to protect the transmitting filter 1 and the receiving filter 2, conventional duplexers typically also include a plastic encapsulation (not shown) that covers the transmitting filter 1 and the receiving filter 2.

[0004] The main shortcomings of the existing duplexers are: (1) Since the transmitting and receiving filters are independent devices and are laid flat on the packaging substrate, and the resonators in both are also laid flat, the integration of the existing duplexers is low, resulting in a large module area, which is not conducive to the miniaturization of the duplexers. This disadvantage is more obvious when there are many resonators in the duplexer. (2) In the prior art, the transmitting and receiving filters are usually fabricated on different substrates, which requires different wafers, which leads to an increase in the number of wafers used, and thus an increase in manufacturing costs. Summary of the Invention

[0005] To overcome the above-mentioned defects in the prior art, the present invention provides a duplexer, which includes:

[0006] A packaging substrate and a stacked structure disposed on the packaging substrate;

[0007] The stacked structure includes a substrate, N device layers and a signal lead-out structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure. N is an integer and N≥2.

[0008] For a device layer directly formed on the substrate, the device region and cap structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators; for a device layer not directly formed on the substrate, the device region and cap structure are formed on the cap structure of an adjacent device layer, and the device region and the cap structure of the adjacent device layer together constitute one or more resonators; a cavity is formed between the cap structure and the device region in each device layer; the resonators in the stacked structure are used to construct a transmit filter and a receive filter.

[0009] The signal extraction structure extracts the signals from the stacked structure to the outside of the stacked structure.

[0010] According to one aspect of the invention, in the duplexer, the N device layers are stacked longitudinally on a first surface of the substrate, and are arranged sequentially from the direction closest to the substrate to the direction furthest from the substrate, with the Nth device layer being the top device layer among the N device layers; wherein, the resonator formed by the device region in the i-th device layer and the substrate in which it is located or the cap structure in the adjacent device layer in which it is located is the i-th resonator, and the cavity formed between the cap structure in the i-th device layer and the device region is the i-th cavity, where i is an integer and 1≤i≤N.

[0011] According to another aspect of the invention, in this duplexer, N1 device layers are stacked longitudinally on a first surface of the substrate, and are arranged sequentially from the first device layer to the N1th device layer in the direction from the substrate to the distance from the substrate. The N1th device layer is the top device layer among the N1 device layers, and N1 is a positive integer and N1 < N. The N-N1 device layers are stacked longitudinally on a second surface of the substrate, and are arranged sequentially from the N1+1th device layer to the Nth device layer in the direction from the substrate to the distance from the substrate. The Nth device layer is the top device layer among the N-N1 device layers. The resonator formed by the device region in the i-th device layer and the substrate or the cap structure in the adjacent device layer is the i-th resonator, and the cavity formed between the cap structure and the device region in the i-th device layer is the i-th cavity, where i is an integer and 1 ≤ i ≤ N.

[0012] According to another aspect of the invention, in the duplexer, if the i-th device layer is a non-top device layer; the cap structure in the i-th device layer includes M i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Capping layer; the first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M i The first cap layer has a through hole communicating with the i-th cavity, and the second cap layer fills the through hole on the first cap layer; or the cap structure in the i-th device layer includes M. i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Capping layer; the first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M i The M iA through-hole is formed on the capping layer, penetrating its own thickness and communicating with the i-th cavity; or the capping structure in the i-th device layer is formed on the substrate or on the capping structure in the adjacent device layer by deposition, and an i-th opening is formed at a position corresponding to the device area in the i-th device layer, penetrating its own thickness; the device area in the (i+1)-th device layer is formed above the i-th opening, thereby forming the i-th cavity between the capping structure and the device area in the i-th device layer.

[0013] According to another aspect of the invention, in the duplexer, if the i-th device layer is the top device layer, the cap structure in the i-th device layer includes M. i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Capping layer; the first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M i The first cap layer has a through hole communicating with the Nth cavity, and the second cap layer fills the through hole on the first cap layer.

[0014] According to another aspect of the invention, in this duplexer, the cap structure for the i-th device layer includes M. i In the case of a cap layer, the M i In a capping layer, the stresses of any two adjacent capping layers are opposite.

[0015] According to another aspect of the invention, in this duplexer, M i =3; the materials of the first capping layer and the third capping layer are both silicon dioxide, and the material of the second capping layer is silicon nitride.

[0016] According to another aspect of the invention, in this duplexer, for a device layer directly formed on the substrate, the device region includes one or more stacked structures and an acoustic reflection structure corresponding to each of the stacked structures; wherein each of the stacked structures is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode in a direction from near the substrate to far from the substrate; the acoustic reflection structure is formed on the substrate or within the substrate, and the acoustic reflection structure and the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure have an overlapping region in the device thickness direction.

[0017] According to another aspect of the invention, in this duplexer, for the i-th device layer being a non-top device layer and wherein the cap structure includes M i In the case of a capping layer, the device region in the (i+1)th device layer includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure; wherein each stacked structure is formed on the capping structure of the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode from the direction near the substrate to the direction away from the substrate; the acoustic reflection structure is formed on or within the capping structure of the i-th device layer, and the acoustic reflection structure and the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure have an overlapping area in the device thickness direction.

[0018] According to another aspect of the invention, in the duplexer, for the case where the i-th device layer is not the top device layer and the cap structure therein has an i-th opening, the device region in the (i+1)-th device layer includes one or more stacked structures; wherein each of the stacked structures is formed on the i-th opening of the cap structure in the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer and an upper electrode in a direction from near the substrate to far from the substrate, and the lower electrode, the piezoelectric layer and the upper electrode have an overlapping area with the i-th cavity in the device thickness direction.

[0019] According to another aspect of the invention, in the duplexer, the first to the N2nd resonators are used to construct one of the transmit filter and the receive filter, and the N2+1 to the Nth resonators are used to construct the other of the transmit filter and the receive filter, where N2 is a positive integer and N2 is less than N; the signal extraction structure includes a first extraction portion and a second extraction portion, wherein the first extraction portion penetrates the substrate and is used to extract the signals of the first to the N2nd resonators to the outside of the stacked structure, and the second extraction portion penetrates the cap structure in the Nth device layer and is used to extract the signals of the N2+1 to the Nth resonator to the outside of the stacked structure.

[0020] According to another aspect of the invention, in the duplexer, the first resonator to the N1th resonator are used to construct the transmit filter, and the N1+1th resonator to the Nth resonator are used to construct the receive filter; the signal extraction structure includes a first extraction portion and a second extraction portion, wherein the first extraction portion penetrates the cap structure in the N1th device layer and is used to extract the signals from the first resonator to the N1th resonator to the outside of the stacked structure, and the second extraction portion penetrates the cap structure in the Nth device layer and is used to extract the signals from the N1+1th resonator to the Nth resonator to the outside of the stacked structure.

[0021] According to another aspect of the invention, in the duplexer, the stacked structure further includes an interlayer conductive structure that penetrates at least one of the N device layers through a cap structure for connecting resonators in different layers.

[0022] The present invention also provides a method for manufacturing a duplexer, the method comprising:

[0023] A stacked structure is formed, comprising a substrate, N device layers, and a signal extraction structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure, where N is an integer and N≥2. For device layers directly formed on the substrate, the device region and cap structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators. For device layers not directly formed on the substrate, the device region and cap structure are formed on the cap structure of an adjacent device layer, and the device region and the cap structure of the adjacent device layer together constitute one or more resonators. A cavity is formed between the cap structure and the device region in each device layer. The resonators in the stacked structure are used to construct transmit filters and receive filters. The signal extraction structure extracts the signal from the stacked structure to the outside of the stacked structure.

[0024] A packaging substrate is provided and the stacked structure is mounted onto the packaging substrate.

[0025] According to one aspect of the present invention, in the manufacturing method, the step of forming N vertically stacked device layers on a substrate includes: sequentially forming vertically stacked device layers 1 to N on a first surface of the substrate, wherein a resonator formed by a device region in the i-th device layer and the substrate in which it is located or a cap structure in the adjacent device layer in which it is located is the i-th resonator, and the cavity formed between the cap structure in the i-th device layer and the device region is the i-th cavity, where i is an integer and 1≤i≤N.

[0026] According to another aspect of the present invention, in the manufacturing method, the step of forming N vertically stacked device layers on a substrate includes: sequentially forming a first vertically stacked device layer to an N1th device layer on a first surface of the substrate, and sequentially forming a N1+1th vertically stacked device layer to an Nth device layer on a second surface of the substrate, where N1 is a positive integer and N1 < N; wherein, the resonator formed by the device region in the i-th device layer and the substrate in which it is located or the cap structure in the adjacent device layer in which it is located is the i-th resonator, and the cavity formed between the cap structure in the i-th device layer and the device region is the i-th cavity, where i is an integer and 1 ≤ i ≤ N.

[0027] According to another aspect of the present invention, in the manufacturing method, the step of forming the i-th device layer includes: a1, forming a device region in the i-th device layer on the substrate or on a capping structure in the (i-1)-th device layer; a2, depositing and patterning an i-th sacrificial material covering the device region on the substrate or on the capping structure in the (i-1)-th device layer, retaining only the portion above the device region; a3, depositing a first capping layer covering the i-th sacrificial material on the substrate or on the capping structure in the (i-1)-th device layer, forming a through-hole in the first capping layer and removing the i-th sacrificial material through the through-hole, thereby forming an i-th cavity between the first capping layer and the device region of the i-th device layer; a4, sequentially depositing a second capping layer to the M-th capping layer on the first capping layer. i Cap layer, M i It is an integer and M i ≥2, wherein the first capping layer to the Mth layer i The cap layers together constitute the cap structure in the i-th device layer, and the second cap layer fills the through-holes on the first cap layer.

[0028] According to another aspect of the invention, in the manufacturing method, the step of sequentially forming longitudinally stacked first to Nth device layers on a first surface of the substrate includes: b1, forming a device region in the i-th device layer on the substrate or on a capping structure in the (i-1)th device layer; depositing and patterning an i-th sacrificial material covering the device region on the substrate or on the capping structure in the (i-1)th device layer, retaining only the portion above the device region; depositing a first capping layer covering the i-th sacrificial material on the substrate or on the capping structure in the (i-1)th device layer; and sequentially depositing second to Mth capping layers on the first capping layer. i Cap layers, wherein the first cap layer to the Mth cap layer i The cap layers together constitute the cap structure in the i-th device layer; where i ≠ N, M i It is an integer and M i≥2; b2, Form the device region in the Nth device layer on the cap structure in the (N-1)th device layer; Deposit and pattern the Nth sacrificial material covering the device region on the cap structure in the (N-1)th device layer, retaining only the portion above the device region; Deposit the first cap layer covering the Nth sacrificial material on the cap structure in the (N-1)th device layer; b3, Etch downwards from the first cap layer covering the Nth sacrificial material until a through-hole is formed through the Nth sacrificial material to the first sacrificial material, and remove the Nth sacrificial material to the first sacrificial material through the through-hole, thereby forming the corresponding Nth cavity to the first cavity; b4, Sequentially deposit the second cap layer to the Mth cap layer on the first cap layer in the Nth device layer. N Cap layer, M N It is an integer and M N ≥2, wherein the first capping layer to the Mth layer N The cap layers together constitute the cap structure in the Nth device layer, and the second cap layer fills the vias on the first cap layer.

[0029] According to another aspect of the present invention, in the manufacturing method, the step of sequentially forming longitudinally stacked first to Nth device layers on a first surface of the substrate includes: c1, forming a device region in the first device layer on the substrate; c2, depositing and patterning an i-th sacrificial material covering the device region on the substrate or on a cap structure in the (i-1)th device layer, retaining only the portion above the device region; depositing an i-th cap material covering the i-th sacrificial material on the substrate or on the cap structure in the (i-1)th device layer, and planarizing the i-th cap material until the i-th sacrificial material is exposed, the planarized i-th cap material constituting the cap structure in the i-th device layer; forming a (i+1)th device layer on the cap structure in the i-th device layer. Device region, wherein the device region in the (i+1)th device layer is located on the i-th sacrificial material; the i-th sacrificial material is removed to form an i-th cavity between the device region in the (i+1)th device layer and the device region in the i-th device layer; wherein i ≠ N; c3, deposit the N-th sacrificial material covering the device region in the N-th device layer on the cap structure in the N-1th device layer and pattern it, retaining only the portion above the device region; deposit a first cap layer covering the N-th sacrificial material on the cap structure in the N-1th device layer, open a through hole in the first cap layer and remove the N-th sacrificial material through the through hole, thereby forming an N-th cavity between the first cap layer and the device region in the N-th device layer; sequentially deposit a second cap layer to the M-th cap layer on the first cap layer. N Cap layer, M N It is an integer and M N≥2, wherein the first capping layer to the Mth layer N The cap layers together constitute the cap structure in the Nth device layer, and the second cap layer fills the vias on the first cap layer.

[0030] According to another aspect of the invention, in this manufacturing method, the M i In a capping layer, the stresses of any two adjacent capping layers are opposite.

[0031] According to another aspect of the invention, in this manufacturing method, M i =3; the materials of the first capping layer and the third capping layer are both silicon dioxide, and the material of the second capping layer is silicon nitride.

[0032] According to another aspect of the invention, in this manufacturing method, for a device layer directly formed on the substrate, the device region includes one or more stacked structures and an acoustic reflection structure corresponding to each of the stacked structures; wherein each of the stacked structures is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode in a direction from near the substrate to far from the substrate; the acoustic reflection structure is formed on the substrate or within the substrate, and the acoustic reflection structure and the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure have an overlapping region in the device thickness direction.

[0033] According to another aspect of the invention, in the manufacturing method, when i≠N, the device region in the (i+1)th device layer includes one or more stacked structures and an acoustic reflection structure corresponding to each of the stacked structures; wherein each of the stacked structures is formed on the cap structure of the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode in a direction from near the substrate to far from the substrate; the acoustic reflection structure is formed on or within the cap structure of the i-th device layer, and the acoustic reflection structure has an overlapping region with the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure in the device thickness direction.

[0034] According to another aspect of the invention, in the manufacturing method, when i≠N, the device region in the (i+1)th device layer includes one or more stacked structures; wherein each of the stacked structures is formed on a cap structure in the i-th device layer and located above the i-th cavity, and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode in a direction from near the substrate to far from the substrate, wherein the lower electrode, the piezoelectric layer, and the upper electrode have an overlapping region with the i-th cavity in the device thickness direction.

[0035] According to another aspect of the invention, in this manufacturing method, the first to the N2nd resonators are used to construct one of the transmit filter and the receive filter, and the N2+1 to the Nth resonators are used to construct the other of the transmit filter and the receive filter, where N2 is a positive integer and N2 is less than N; the step of forming the signal lead-out structure includes: forming a first lead-out portion through the substrate, the first lead-out portion being used to lead the signals of the first to the N2nd resonators to the outside of the stacked structure; and forming a second lead-out portion through the cap structure in the Nth device layer, the second lead-out portion being used to lead the signals of the N2+1 to the Nth resonators to the outside of the stacked structure.

[0036] According to another aspect of the invention, in this manufacturing method, the first resonator to the N1th resonator are used to construct the transmit filter, and the N1+1th resonator to the Nth resonator are used to construct the receive filter; the step of forming the signal lead-out structure includes: forming a first lead-out portion penetrating the cap structure in the N1th device layer, the first lead-out portion being used to lead the signals from the first resonator to the N1th resonator to the outside of the stacked structure; and forming a second lead-out portion penetrating the cap structure in the Nth device layer, the second lead-out portion being used to lead the signals from the N1+1th resonator to the Nth resonator to the outside of the stacked structure.

[0037] According to another aspect of the invention, the manufacturing method further includes forming an interlayer conductive structure that penetrates at least one of the N device layers through a cap structure for connecting resonators in different layers.

[0038] The present invention also provides a multiplexer comprising at least one duplexer, the duplexer being implemented using the aforementioned duplexer or formed using the aforementioned manufacturing method.

[0039] The duplexer and its manufacturing method provided by this invention effectively improve the integration density of the duplexer by fully utilizing the vertical space to integrate the transmitting and receiving filters into a single stacked structure, thereby significantly reducing the module area of ​​the duplexer and facilitating its miniaturization. Furthermore, since the transmitting and receiving filters are integrated into a single stacked structure, compared to existing duplexers where the transmitting and receiving filters are formed on different substrates, implementing this invention can reduce the number of wafers used, thus lowering the manufacturing cost of the duplexer. Attached Figure Description

[0040] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0041] Figure 1 This is a cross-sectional schematic diagram of an existing duplexer;

[0042] Figure 2 This is a flowchart of a method for manufacturing a duplexer according to a specific embodiment of the present invention;

[0043] Figures 3(a) to 3(j) According to a preferred embodiment of the present invention Figure 2 The diagram shows cross-sectional schematics of each stage in the process of manufacturing a duplexer.

[0044] Figures 4(a) to 4(e) According to another preferred embodiment of the present invention Figure 2 The diagram shows cross-sectional schematics of each stage in the process of manufacturing a duplexer.

[0045] Figures 5(a) to 5(g) According to yet another preferred embodiment of the present invention Figure 2 The diagram shows cross-sectional schematics of each stage in the process of manufacturing a duplexer.

[0046] Figures 6(a) to 6(c) According to yet another preferred embodiment of the present invention Figure 2 The diagram shows cross-sectional schematics of each stage in the process of manufacturing a duplexer.

[0047] The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0048] To better understand and explain the present invention, a further detailed description of the invention will be provided below in conjunction with the accompanying drawings.

[0049] This invention provides a duplexer, which includes:

[0050] A packaging substrate and a stacked structure disposed on the packaging substrate;

[0051] The stacked structure includes a substrate, N device layers and a signal lead-out structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure. N is an integer and N≥2.

[0052] For a device layer directly formed on the substrate, the device region and cap structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators; for a device layer not directly formed on the substrate, the device region and cap structure are formed on the cap structure of an adjacent device layer, and the device region and the cap structure of the adjacent device layer together constitute one or more resonators; a cavity is formed between the cap structure and the device region in each device layer; the resonators in the stacked structure are used to construct a transmit filter and a receive filter.

[0053] The signal extraction structure extracts the signals from the stacked structure to the outside of the stacked structure.

[0054] The following section will provide a detailed explanation of each of the above-mentioned components of a duplexer.

[0055] Specifically, the duplexer provided by the present invention includes a packaging substrate and a stacked structure disposed on the packaging substrate. The stacked structure further includes a substrate, N device layers, and a signal lead-out structure, where N is an integer and N≥2. The present invention does not impose any limitation on the specific value of N, which is determined by the specific design requirements of the duplexer. For example, it can be equal to 2, 3, 4, etc.

[0056] In this embodiment, the substrate is fabricated using a conventional wafer, and its materials include, but are not limited to, semiconductor materials such as silicon, germanium, germanium-silicon, GaAs, and SiC. All existing and future materials suitable for substrates in resonators are applicable to this invention. For the sake of simplicity, not all possible substrate materials will be listed here. The substrate comprises two opposing surfaces, hereinafter referred to as the first surface and the second surface.

[0057] In this embodiment, N device layers are stacked longitudinally (i.e., along the substrate thickness direction) on the substrate. It should be noted that this invention does not limit whether the N device layers are stacked on one surface or both surfaces of the substrate. That is, the longitudinal stacking of the N device layers includes two cases: the first case is that all N device layers are stacked longitudinally on the first surface of the substrate; the second case is that a portion of the N device layers are stacked longitudinally on the first surface of the substrate, while another portion is stacked longitudinally on the second surface of the substrate. For the first case, for ease of description, the N device layers are defined sequentially from the direction closest to the substrate to the direction furthest from the substrate as device layer 1 to device layer N. For example, the stacked structure includes three device layers (i.e., N=3) stacked sequentially on the first surface of the substrate. When the first surface of the substrate is placed upwards, these three device layers are, from bottom to top, device layer 1, device layer 2, and device layer 3. For the second scenario, the number of device layers stacked on the first surface of the substrate is denoted as N1, and the corresponding number of device layers stacked on the second surface of the substrate is equal to N-N1, where N1 is a positive integer and N1 < N. Based on this, the N1 device layers stacked on the first surface of the substrate are defined sequentially from the direction closest to the substrate to the direction furthest from the substrate as device layer 1 to device layer N1, and the N-N1 device layers stacked on the second surface of the substrate are defined sequentially from the direction closest to the substrate to the direction furthest from the substrate as device layer N1+1 to device layer N. For example, the stacked structure includes 5 device layers (i.e., N = 5), with 3 device layers stacked sequentially on the first surface of the substrate (i.e., N1 = 3), and 2 device layers stacked sequentially on the second surface of the substrate. When the first surface of the substrate is placed upwards, the three device layers stacked on the first surface of the substrate are, from bottom to top (i.e., from the direction closest to the substrate to the direction furthest from the substrate on the first surface side), the first device layer, the second device layer, and the third device layer, respectively; when the second surface of the substrate is placed upwards, the two device layers stacked on the second surface of the substrate are, from bottom to top (i.e., from the direction closest to the substrate to the direction furthest from the substrate on the second surface side), the fourth device layer and the fifth device layer, respectively.

[0058] In this embodiment, each device layer includes a device region and a cap structure. For device layers directly formed on the substrate, both the device region and the cap structure are formed on the substrate. For device layers not directly formed on the substrate, the device region and the cap structure are formed on the cap structure of the adjacent device layer. Taking the case where N device layers are all stacked on the first surface of the substrate as an example, the device region and cap structure of the first device layer are formed on the first surface of the substrate, the device region and cap structure of the second device layer are formed on the cap structure of the first device layer, and so on, with the device region and cap structure of the Nth device layer formed on the cap structure of the (N-1)th device layer. Taking the case of N device layers stacked on two surfaces of a substrate as an example, the device region and cap structure in the first device layer are formed on the first surface of the substrate, the device region and cap structure in the second device layer are formed on the cap structure in the first device layer, and so on, the device region and cap structure in the N1 device layer are formed on the cap structure in the N1-1 device layer; the device region and cap structure in the N1+1 device layer are formed on the second surface of the substrate, the device region and cap structure in the N1+2 device layer are formed on the cap structure in the N1+1 device layer, and so on, the device region and cap structure in the N device layer are formed on the cap structure in the N-1 device layer.

[0059] In this embodiment, for a device layer directly formed on the substrate surface, the device region in the device layer and the substrate together constitute one or more resonators. For a device layer formed on a cap structure in an adjacent device layer, the device region in the device layer and the cap structure in the adjacent device layer together constitute one or more resonators. Taking the case of 3 (i.e., N=3) device layers stacked on the first surface of the substrate as an example, the device region in the first device layer and the substrate together constitute one or more resonators, the device region in the second device layer and the cap structure in the first device layer together constitute one or more resonators, and the device region in the third device layer and the cap structure in the second device layer together constitute one or more resonators. Taking the case of three device layers stacked on the first surface of the substrate and two device layers stacked on the second surface of the substrate (i.e., N=5, N1=3) as an example, the device region in the first device layer and the substrate constitute one or more resonators; the device region in the fourth device layer and the substrate constitute one or more resonators; the device region in the second device layer and the cap structure in the first device layer constitute one or more resonators; the device region in the third device layer and the cap structure in the second device layer constitute one or more resonators; and the device region in the fifth device layer and the cap structure in the fourth device layer constitute one or more resonators. Furthermore, a cavity is formed between the cap structure and the device region in each device layer. It should be noted that this invention does not limit the specific type of resonator in the stacked structure, including but not limited to bulk acoustic wave resonators and surface acoustic wave resonators. All resonators in the stacked structure can be of the same type or different types, and this invention does not limit this in any way.

[0060] For ease of description, the device region in the i-th device layer is referred to as the i-th device region, the cap structure in the i-th device layer is referred to as the i-th cap structure, the cavity between the cap structure and the device region in the i-th device layer is referred to as the i-th cavity, and the resonator formed by the device region in the i-th device layer and the substrate (for the case where the i-th device layer is directly formed on the substrate) or the cap structure in the adjacent device layer (for the case where the i-th device layer is not directly formed on the substrate) is referred to as the i-th resonator, where i = 1, 2, ..., N.

[0061] In this embodiment, a portion of the resonators in the stacked structure are used to construct the transmit filter, and the remaining resonators are used to construct the receive filter. That is, all resonators used to construct the transmit and receive filters are integrated into a single stacked structure. It should be noted that this invention does not limit the specific distribution of the resonators used to construct the transmit and receive filters. For the case where all N device layers are stacked on the first surface of the substrate, preferably, the 1st to N2nd resonators are used to construct the transmit filter (or receive filter), and the N2+1th to Nth resonators are used to construct the receive filter (or transmit filter), where N2 is a positive integer less than N. For example, when N=2 and N2=1, the 1st resonator is used to construct the transmit filter (or receive filter), and the 2nd resonator is used to construct the receive filter (or transmit filter); or, for example, when N=4 and N2=2, the 1st and 2nd resonators are used to construct the transmit filter (or receive filter), and the 3rd and 4th resonators are used to construct the receive filter (or transmit filter); and so on. For the case where N device layers are stacked on the two surfaces of a substrate, preferably, all resonators on the first surface of the substrate (i.e., the 1st to the N1st resonators) are used to construct the transmit filter (or receive filter), and all resonators on the second surface of the substrate (i.e., the N1+1st to the Nth resonators) are used to construct the receive filter (or transmit filter). Those skilled in the art will understand that the above examples should not be construed as limiting the distribution of resonators used to construct the transmit and receive filters. The resonators used to construct the transmit and receive filters can be distributed in any feasible manner according to the actual design. Taking the case where all N device layers are stacked on the first surface of the substrate as an example, the 1st to the N2-1st resonators and some of the N2nd resonators can be used to construct the transmit filter (or receive filter), while the remaining N2nd resonators and the N2+1st to the Nth resonators can be used to construct the receive filter (or transmit filter); and so on.

[0062] It should be noted that when a device region in a device layer, together with the substrate or the cap structure in an adjacent device layer, forms two or more resonators, these two or more resonators are considered to be located in the same layer. In some applications, resonators located between different layers need to be electrically connected. In this case, resonators located between different layers are vertically connected through an interlayer conductive structure. This interlayer conductive structure penetrates at least one cap structure in N device layers to achieve electrical connection to the device regions in different device layers, thereby achieving electrical connection to the resonators located in different layers. For example, if three device layers are vertically stacked on the first surface of a substrate, and the first resonator (i.e., the resonator formed by the first device region in the first device layer and the substrate) and the second resonator (i.e., the resonator formed by the second device region in the second device layer and the first cap structure in the first device layer) need to be electrically connected, in this case, the interlayer conductive structure penetrates the first cap structure in the first device layer to connect the first resonator and the second resonator. It should be noted that, for cases where resonators are formed on both sides of the substrate, the interlayer conductive structure may need to penetrate the substrate to achieve electrical connection between the resonators located on both sides of the substrate. For example, three device layers and two device layers are stacked on the first and second surfaces of the substrate, respectively. When an electrical connection is required between the first resonator (the resonator formed by the first device region in the first device layer and the substrate) and the fourth resonator (the resonator formed by the fourth device region in the fourth device layer and the substrate), the interlayer conductive structure penetrates the substrate to connect the first and fourth resonators. Furthermore, for cases where resonators located between different layers do not require electrical connection, such as when two device layers are stacked on the first surface of a substrate, a first device region in the first device layer and the substrate together form a first resonator used to construct a transmit filter, and a second device region in the second device layer and the first cap structure in the first device layer together form a second resonator used to construct a receive filter, and no electrical connection is required between the first and second resonators, this case only involves the connection between resonators located within the same layer, which can be achieved using conventional connection methods between resonators within the same layer. Typically, interlayer conductive structures can be implemented using conductive vias, metal wires, etc. Those skilled in the art will understand that the aforementioned conductive vias and metal wires are merely illustrative examples and should not be construed as limitations on interlayer conductive structures. Any structure that can achieve electrical connection between resonators in different layers is applicable to the interlayer conductive structures of this invention. For the sake of simplicity, not all possible interlayer conductive structures will be listed here.

[0063] In this embodiment, the stacked structure further includes a signal extraction structure for extracting signals from the resonators in the stacked structure to the outside of the stacked structure. The signal extraction structure further includes a first extraction portion and a second extraction portion, wherein one of the first and second extraction portions is used to extract signals from the resonators forming the transmit filter to the outside of the stacked structure, and the other of the first and second extraction portions is used to extract signals from the resonators forming the receive filter to the outside of the stacked structure. The positions of the first and second extraction portions are related to the layout of the resonators from which they extract signals. For example, in the case where all N device layers are stacked on the first surface of the substrate, when the first to N2 resonators are used to construct a transmit filter (or receive filter) and the N2+1 to N resonators are used to construct a receive filter (or transmit filter), preferably, the first lead-out portion is disposed on the substrate side (e.g., implemented by a conductive via penetrating the substrate) to lead the signals of the first to N2 resonators to the outside of the stacked structure; the second lead-out portion is disposed on the Nth cap structure side (e.g., implemented by a conductive via penetrating the Nth cap structure) to lead the signals of the N2+1 to Nth resonators to the outside of the stacked structure. For example, in the case of N device layers stacked on two surfaces of a substrate, when the first to N1 resonators are used to construct a transmit filter (or receive filter) and the N1+1 to N resonators are used to construct a receive filter (or transmit filter), preferably, a first lead-out is disposed on the Nth cap structure side (e.g., implemented using a conductive via penetrating the Nth cap structure) to lead the signals of the N1+1 to Nth resonators to the outside of the stacked structure; a second lead-out is disposed on the N1 cap structure side (e.g., implemented using a conductive via penetrating the N1 cap structure) to lead the signals of the first to N1 resonators to the outside of the stacked structure. Those skilled in the art will understand that the above-described positions of the first and second lead-outs are merely preferred embodiments and should not be construed as limiting the positions of the first and second lead-outs. In other embodiments, when all N device layers are stacked on the first surface of the substrate, the first lead-out portion can also be disposed on the Nth cap structure side, or simultaneously on the substrate side and the Nth cap structure side; when N device layers are stacked on both surfaces of the substrate, the first lead-out portion can also be disposed on the N1st cap structure side, or simultaneously on the N1st cap structure side and the Nth cap structure side. The same applies to the second lead-out portion, which will not be elaborated further for simplicity. It should also be noted that the specific number of the first and second lead-out portions is determined by the actual circuit design. For example, in one application scenario, the first lead-out portion, in addition to serving as an input and output terminal, also needs to connect to electronic components (such as inductors) in the package substrate; in this case, the number of first lead-out portions is three.The same applies to the second introduction; for the sake of brevity, I will not elaborate further here.

[0064] In this embodiment, contact points are also formed on the surface of the signal lead-out structure exposed outside the stacked structure for connection between the signal lead-out structure and the packaging substrate. Hereinafter, the contact points formed on the first lead-out portion exposed outside the stacked structure are referred to as first contact points, and the contact points formed on the second lead-out portion exposed outside the stacked structure are referred to as second contact points. It should be noted that the specific number of first contact points depends on the number of first leads, and the specific number of second contact points depends on the number of second leads; no limitation is made here. The materials of the first and second contact points include, but are not limited to, gold, silver, copper, aluminum, titanium, tungsten, nickel, and alloys. When the signal lead-out structure is formed on the same side of the stacked structure, the stacked structure is mounted on the packaging substrate by directly soldering the first and second contact points to the packaging substrate. For example, in the case where N device layers are all stacked on the first surface of the substrate, if both the first and second leads are formed on the substrate side, the stacked structure can be directly soldered with the substrate facing the packaging substrate. When signal lead-out structures are formed on both sides of the stacked structure, the contact points on one side can be directly soldered to the packaging substrate, and the contact points on the other side can be connected to the packaging substrate via conductors (e.g., metal wires, metal sheets, etc.) to achieve the mounting of the stacked structure on the packaging substrate. Taking the case where all N device layers are stacked on the first surface of the substrate as an example, if the first lead-out portion is formed on the substrate side and the second lead-out portion is formed on the Nth cap structure side, the first contact point (or the second contact point) can be directly soldered to the packaging substrate, and the second contact point (or the first contact point) can be connected to the packaging substrate via metal wires. It should be noted that in this embodiment, the resonators used to construct the transmit and receive filters in the duplexer are formed in the stacked structure, while other electronic components in the duplexer, such as capacitors and inductors, are disposed in the packaging substrate. Those skilled in the art will understand that in other embodiments, through reasonable design, other electronic components besides the resonator can be integrated into the stacked structure, and this invention does not limit this in any way.

[0065] Typically, the duplexer provided by this invention also includes a molding compound (not shown) formed on a packaging substrate to cover the stacked structure. The molding compound can be made using existing conventional molding compound materials, and this invention does not impose any limitations on it.

[0066] The duplexer provided by this invention effectively improves the integration density of the duplexer by fully utilizing the vertical space to integrate the transmitting and receiving filters into a single stacked structure, thereby significantly reducing the module area and facilitating miniaturization. Furthermore, since the transmitting and receiving filters are integrated into a single stacked structure, compared to existing duplexers where the transmitting and receiving filters are formed on different substrates, implementing this invention can reduce the number of wafers used, thus lowering the manufacturing cost of the duplexer.

[0067] There are multiple ways to implement the cap structure in the device layer. The following describes three preferred embodiments.

[0068] In a preferred embodiment, the cap structure in each device layer is a multi-layer structure. For ease of description, the i-th cap structure in the i-th device layer is defined as including M. i One cap layer, M i It is an integer and M i ≥2, and the M i The capping layers are named sequentially from the first capping layer to the Mth capping layer in the direction from closest to farthest from the substrate. i Capping layer. For the i-th capping structure in the i-th device layer, the first capping layer is formed on the substrate or on the capping structure in the adjacent device layer (i.e., the (i-1)-th device layer) by deposition. (For the case where all N device layers are stacked on the first surface of the substrate, the first capping layer of the first capping structure in the first device layer is formed on the substrate, and the first capping layer of the capping structure in other device layers is formed on the capping structure in the adjacent device layer; for the case where N device layers are stacked on both surfaces of the substrate, the first capping layer of the first capping structure in the first device layer is formed on the first surface of the substrate, the first capping layer of the N1+1-th capping structure in the N1+1-th device layer is formed on the second surface of the substrate, and the first capping layer of the capping structure in other device layers is formed on the capping structure in the adjacent device layer.) An i-th cavity is formed between the first capping layer and the device region (i.e., the i-th device region) located in the same device layer. The second cap layer to the Mth cap layer of the i-th cap structure in the i-th device layer iThe capping layers are sequentially formed on the first capping layer of the i-th capping structure by deposition. In this embodiment, a through hole communicating with the i-th cavity is formed on the first capping layer of the i-th capping structure in the i-th device layer, and the second capping layer of the i-th capping structure in the i-th device layer fills the through hole in the first capping layer. It should be noted that (1) the i-th cavity is formed by releasing the sacrificial material originally filled in the space through the through hole on the first capping layer in the i-th capping structure; the second capping layer filling the through hole in the first capping layer is beneficial to sealing the i-th cavity after its formation, thereby effectively avoiding contamination from subsequent processes. (2) The multi-layer structure of the capping structure can achieve better water and oxygen barrier effect. (3) The materials of any two adjacent capping layers in the capping structure preferably have opposite stresses. In this case, the capping structure can be in a low stress state, thereby effectively preventing the capping structure from warping, which is beneficial to improving the yield of the duplexer. This invention does not limit the number of cap layers; the specific number depends on the actual design requirements of the duplexer. Furthermore, this invention does not limit the specific material of each cap layer; any material with opposite stress and suitable for deposition is applicable. In one specific embodiment, each cap structure includes three cap layers: the first and third cap layers are made of silicon dioxide, and the second cap layer is made of silicon nitride. Moreover, those skilled in the art will understand that in other embodiments, all cap layers in the cap structure may also use the same material, in which case the cap structure presents a single-layer integral structure.

[0069] In another preferred embodiment, the cap structure in each device layer is also a multi-layer structure, but the difference from the aforementioned preferred embodiment lies in the via configuration of the cap structure in the non-top-layer device layers. Specifically, when all N device layers are stacked on the first surface of the substrate, the Nth device layer is the top-layer device layer, and the 1st to N-1th device layers are non-top-layer device layers. When N device layers are stacked on both surfaces of the substrate, the N1st and Nth device layers are the top-layer device layers, and the 1st to N1-1th and N1+1th to Nth device layers are all non-top-layer device layers. Specifically, when the i-th device layer is a non-top-layer device layer, a via is formed in the cap structure of the i-th device layer, penetrating its own thickness and communicating with the i-th cavity. More preferably, the through holes on the cap structure in all device layers (including through holes on the cap structure in non-top device layers and through holes on the first cap layer of the cap structure in the top device layer) are projected in the horizontal direction and coincide. That is, the through holes are formed by etching from the first cap layer downwards in one go after the first cap layer of the cap structure in the top device layer is formed, so as to remove all the sacrificial material originally filled in the Nth cavity to the first cavity in one go, thereby improving the manufacturing efficiency of the duplexer.

[0070] In another preferred embodiment, the cap structure in the top device layer still adopts the aforementioned multilayer structure, which will not be described again here for the sake of simplicity. The cap structure in the non-top device layer has an opening extending through its own thickness. This opening is located above the device region in the same device layer and is used to construct a cavity above the device region. The case is illustrated with N device layers stacked on the first surface of the substrate. Device layers 1 to N-1 are non-top device layers. For the i-th device layer (i = 1, 2, ..., N-1), the i-th cap structure has an opening extending through its own thickness (hereinafter referred to as the i-th opening). The device region in the (i+1)-th device layer is formed on the i-th opening. Thus, the inner wall of the i-th opening and the lower surface of the device region in the (i+1)-th device layer enclose a space, thereby forming the i-th cavity between the i-th cap structure and the i-th device region.

[0071] It should be noted that (1) in the aforementioned preferred embodiments, the cap structures in the non-top-level device layers of the stacked structure are the same, for example, all are multi-layer structures or all are open structures. Those skilled in the art will understand that in other embodiments, the cap structures in the non-top-level device layers may also be different. For example, some cap structures in the non-top-level device layers are implemented using multi-layer structures, while other cap structures in the non-top-level device layers are implemented using open structures. This invention does not limit this in any way. (2) In the prior art, caps are usually implemented using wafers, and the caps and substrates are connected by, for example, Au-Au bonding. In this invention, the cap structure in the top-level device layer is formed by deposition. In this way, the number of wafers used can be effectively reduced, and the bonding process is not required, thereby effectively reducing the manufacturing cost of the device. Those skilled in the art will understand that, depending on the actual design requirements, the cap structure in the top-level device layer can also be formed by bonding using conventional caps. For example, after forming the device region in the top-level device layer, a conventional cap is provided and bonded to the cap structure where the device region is located.

[0072] There are multiple ways to implement the device region in the device layer. The following example illustrates how all resonators in the stacked structure are bulk acoustic resonators.

[0073] For the device region formed on the substrate, it includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure. Each stacked structure is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer, and a upper electrode from the direction closest to the substrate to the direction furthest from the substrate. Those skilled in the art will understand that in other embodiments, the stacked structure may also include conventional seed layers, passivation layers, etc. The acoustic reflection structure is formed on or within the substrate. For example, the acoustic reflection structure may be a groove formed on the substrate and an air gap formed with the stacked structure formed on the groove, or it may be a Bragg reflector layer formed on the substrate surface, or even an opening penetrating the substrate. Regardless of the form of the acoustic reflection structure, to ensure the resonator can function properly, the acoustic reflection structure and its corresponding lower electrode, piezoelectric layer, and upper electrode in the stacked structure have an overlapping region in the device thickness direction.

[0074] For device layers formed on cap structures within adjacent device layers, the device region varies depending on the cap structure in which it resides. In the case where the cap structure containing the device region is the aforementioned multilayer structure, the device region includes one or more stacked structures and a corresponding acoustic reflection structure for each stacked structure. For each stacked structure, it is formed on the cap structure within the adjacent device layer and sequentially includes a lower electrode, a piezoelectric layer, and a upper electrode from the direction closest to the substrate to the direction furthest from the substrate. The acoustic reflection structure is formed on or within the cap structure within the adjacent device layer. For example, the acoustic reflection structure can be an air gap formed by a groove formed on the cap structure within the adjacent device layer and the stacked structure formed on the groove, or it can be a Bragg reflector layer formed on the surface of the cap structure within the adjacent device layer. Regardless of the form of the acoustic reflection structure, to ensure the resonator functions properly, the acoustic reflection structure overlaps with the lower electrode, piezoelectric layer, and upper electrode in its corresponding stacked structure in the device thickness direction. For cases where the cap structure containing the device region has an opening, the device region includes only one or more stacked structures. Each stacked structure is formed on the opening of the cap structure in an adjacent device layer and sequentially includes a lower electrode, a piezoelectric layer, and a upper electrode from the direction closest to the substrate to the direction furthest from the substrate. The lower electrode, piezoelectric layer, and upper electrode overlap with the corresponding opening in the device thickness direction. In this way, the opening on the cap structure in the adjacent device layer can serve as a sound wave reflection function without the need to form an additional sound reflection structure. Since no additional sound reflection structure is needed, it simplifies the manufacturing process of the duplexer and saves space used to form the sound reflection structure, thereby reducing the thickness of the stacked structure and further miniaturizing the device.

[0075] The duplexer provided by the present invention will now be described with reference to Figures 3(j), 4(e), 5(g), and 6(c) through four preferred embodiments. In these four preferred embodiments, the stacked structure includes four device layers (i.e., N=4), and all resonators in the stacked structure are bulk acoustic wave resonators.

[0076] As shown in Figure 3(j), the duplexer includes a packaging substrate 400 and a stacked structure disposed on the packaging substrate 400. The stacked structure includes a substrate 100, four device layers, and a signal lead-out structure. The four device layers are stacked on the first surface of the substrate 100. The first device region in the first device layer includes a stacked structure and an acoustic reflection structure. Each stacked structure includes a lower electrode 104-1, a piezoelectric layer 105-1, and an upper electrode 106-1. The acoustic reflection structure is an air gap 103-1 formed between the substrate 100 and the stacked structure. Each stacked structure, its underlying air gap 103-1, and the portion of the substrate 100 located below the stacked structure together constitute an air gap type bulk acoustic resonator (i.e., the first resonator). It should be noted that only two stacked structures are shown in the cross-sectional view for illustrative purposes, and the connection methods between air gap type bulk acoustic resonators in the same layer are omitted. The same treatment method is used for similar situations in this embodiment and subsequent embodiments, and will not be repeated. The first cap structure in the first device layer includes a first cap layer 108-1-1 deposited on the substrate 100 and a second cap layer 108-1-2 deposited on the first cap layer 108-1-1. A first cavity 109-1 is formed between the first cap layer 108-1-1 and the stacked structure. A through-hole communicating with the first cavity 109-1 is formed on the first cap layer 108-1-1, and the second cap layer 108-1-2 fills the through-hole. The i-th device region in the i-th (i = 2, 3, 4) device layer includes a stacked structure and an acoustic reflection structure. Each stacked structure includes a lower electrode 104-i, a piezoelectric layer 105-i, and an upper electrode 106-i. The acoustic reflection structure is an air gap 103-i formed between the cap structure and the stacked structure in the (i-1)-th device layer. Each stacked structure, together with the air gap 103-i below it and the portion of the cap structure in the (i-1)th device layer located below the stacked structure, constitutes an air gap type bulk acoustic resonator (i.e., the i-th resonator). The i-th cap structure in the i-th device layer includes a first cap layer 108-i-1 deposited on the cap structure in the (i-1)th device layer and a second cap layer 108-i-2 deposited on the first cap layer 108-i-1. An i-th cavity 109-i is formed between the first cap layer 108-i-1 and the stacked structure. A through hole communicating with the i-th cavity 109-i is formed on the first cap layer 108-i-1, and the second cap layer 108-i-2 fills the through hole. In this embodiment, the first resonator and the second resonator are used to construct a transmitting filter (or a receiving filter), and the third resonator and the fourth resonator are used to construct a receiving filter (or a transmitting filter). The first resonator and the second resonator are electrically connected through an interlayer conductive structure 110-1 that penetrates the first cap structure, and the third resonator and the fourth resonator are electrically connected through an interlayer conductive structure 110-3 that penetrates the third cap structure.It should be noted that the interlayer conductive structure shown in Figure 3(j) is used to connect the lower electrodes of two adjacent resonators to achieve parallel connection. Those skilled in the art will understand that the connection method achieved by the above-mentioned interlayer conductive structure should not be a limitation on the connection method between different resonators in this invention. Depending on actual design requirements, the interlayer conductive structure can also achieve parallel connection by connecting the upper electrodes of different resonators, or series connection by connecting the upper and lower electrodes of different resonators. This invention does not impose any limitations on this. In this embodiment, the signal extraction structure includes a first extraction part 101 and a second extraction part 111. The first extraction part 101 penetrates the substrate 100 to extract the signals of the first and second resonators, and the second extraction part 111 penetrates the fourth cap structure to extract the signals of the third and fourth resonators. In this embodiment, the stacked structure is mounted on the packaging substrate 400 with the substrate 100 facing the packaging substrate 400. The first lead-out portion 101 is directly soldered to the packaging substrate 400 through the first contact point 301, and the second lead-out portion 111 is connected to the packaging substrate 400 through the second contact point 302 and the metal wire 500.

[0077] The duplexer shown in Figure 4(e) differs from the duplexer shown in Figure 3(j) in that the i-th cap structure in the i-th (i = 1, 2, 3) device layer of the duplexer shown in Figure 4(e) has a through hole 112-i that penetrates its own thickness and communicates with the i-th cavity 109-i.

[0078] The duplexer shown in Figure 5(g) differs from the duplexer shown in Figure 3(j) in that the i-th cap structure 108-i in the i-th (i = 1, 2, 3) device layer of the duplexer shown in Figure 5(g) has openings that correspond one-to-one with the stacked structures in the i-th device region. Each opening penetrates the i-th cap structure 108-i and is located above the corresponding stacked structure. In addition, the i+1 device region in the i+1 device layer includes stacked structures that correspond one-to-one with the openings in the i-th cap structure 108-i, and each stacked structure in the i+1 device region is formed above its corresponding opening and forms the i-th cavity 109-i with the opening.

[0079] The duplexer shown in Figure 6(c) differs from the duplexer shown in Figure 3(j) in that the first and second device layers are stacked on the first surface of the substrate 100, and the third and fourth device layers are stacked on the second surface of the substrate 100. The first device region in the first device layer includes a stacked structure and an acoustic reflection structure. Each stacked structure includes a lower electrode 104-1, a piezoelectric layer 105-1, and an upper electrode 106-1. The acoustic reflection structure is an air gap 103-1 formed between the first surface of the substrate 100 and the stacked structure. Each stacked structure, together with the air gap 103-1 below it and the portion of the substrate 100 located below the stacked structure, constitutes an air gap type bulk acoustic resonator (i.e., the first resonator). The first capping structure in the first device layer includes a first capping layer 108-1-1 deposited on the substrate 100 and a second capping layer 108-1-2 deposited on the first capping layer 108-1-1. A first cavity 109-1 is formed between the first capping layer 108-1-1 and the stacked structure. A through-hole communicating with the first cavity 109-1 is formed on the first capping layer 108-1-1, and the second capping layer 108-1-2 fills the through-hole. The second device region in the second device layer includes a stacked structure and an acoustic reflection structure. Each stacked structure includes a lower electrode 104-2, a piezoelectric layer 105-2, and an upper electrode 106-2. The acoustic reflection structure is an air gap 103-2 formed between the first capping structure and the stacked structure in the first device layer. Each stacked structure, together with the air gap 103-2 below it and the portion of the first cap structure in the first device layer located below the stacked structure, constitutes an air gap type bulk acoustic resonator (i.e., the second resonator). The second cap structure in the second device layer includes a first cap layer 108-2-1 deposited on the first cap structure in the first device layer and a second cap layer 108-2-2 deposited on the first cap layer 108-2-1. A second cavity 109-2 is formed between the first cap layer 108-2-1 and the stacked structure. A through hole is formed on the first cap layer 108-2-1 that communicates with the second cavity 109-2. The second cap layer 108-2-2 fills the through hole. The third and fourth device layers are implemented in the same manner as the first and second device layers, except that they are formed on different surfaces of the substrate 100. For the sake of simplicity, the structures of the third and fourth device layers will not be described here. In this embodiment, the first and second resonators are used to construct a transmit filter (or receive filter), and the third and fourth resonators are used to construct a receive filter (or transmit filter). The first and second resonators are electrically connected through an interlayer conductive structure 110-1 that penetrates the first cap structure, and the third and fourth resonators are electrically connected through an interlayer conductive structure 110-3 that penetrates the third cap structure.In this embodiment, the signal extraction structure includes a first extraction portion 101 and a second extraction portion 111. The first extraction portion 101 penetrates the fourth cap structure in the fourth device layer to extract the signals of the third and fourth resonators. The second extraction portion 111 penetrates the second cap structure to extract the signals of the first and second resonators. In this embodiment, the stacked structure is mounted on the packaging substrate 400 with the second surface of the substrate 100 facing the packaging substrate 400. The first extraction portion 101 is directly soldered to the packaging substrate 400 through a first contact point 301, and the second extraction portion 111 is connected to the packaging substrate 400 through a second contact point 302 and a metal wire 500.

[0080] Accordingly, the present invention also provides a method for manufacturing a duplexer. Please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart of a method for manufacturing a duplexer according to a specific embodiment of the present invention. As shown in the figure, the manufacturing method includes:

[0081] In step S100, a stacked structure is formed, comprising a substrate, N device layers, and a signal extraction structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure. N is an integer and N≥2. For device layers directly formed on the substrate, the device region and cap structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators. For device layers not directly formed on the substrate, the device region and cap structure are formed on the cap structure of an adjacent device layer, and the device region and the cap structure of the adjacent device layer together constitute one or more resonators. A cavity is formed between the cap structure and the device region in each device layer. The resonators in the stacked structure are used to construct a transmit filter and a receive filter. The signal extraction structure extracts the signal from the stacked structure to the outside of the stacked structure.

[0082] In step S101, a packaging substrate is provided and the stacked structure is mounted onto the packaging substrate.

[0083] The steps S100 to S101 described above will be explained in detail below.

[0084] In step S100, a substrate is first provided. In this embodiment, the substrate is fabricated using a conventional wafer, and its material includes, but is not limited to, semiconductor materials such as silicon, germanium, germanium-silicon, GaAs, and SiC. All existing and future materials suitable for substrates in resonators are applicable to this invention. For the sake of simplicity, not all possible substrate materials will be listed here. The substrate includes two opposing surfaces, hereinafter referred to as the first surface and the second surface.

[0085] Next, N vertically stacked device layers are formed on the substrate, where N is an integer and N≥2. This invention does not impose any limitation on the specific value of N; it is determined by the specific design requirements of the duplexer, for example, it can be equal to 2, 3, 4, etc.

[0086] In one specific embodiment, the step of forming N vertically stacked device layers on a substrate includes: sequentially forming N vertically stacked device layers on a first surface of the substrate. The N device layers are defined sequentially as device layer 1 to device layer N from the direction closest to the substrate to the direction furthest from the substrate.

[0087] In another specific embodiment, the step of forming N vertically stacked device layers on a substrate includes: firstly, sequentially forming N1 vertically stacked device layers on a first surface of the substrate, where N1 is a positive integer and N1 < N. These N1 device layers are defined as device layer 1 to device layer N1 from the direction closest to the substrate to the direction furthest from the substrate. Then, sequentially forming N-N1 vertically stacked device layers on a second surface of the substrate, these N-N1 device layers are defined as device layer N1+1 to device layer N from the direction closest to the substrate to the direction furthest from the substrate. Preferably, after forming the N1 device layers on the first surface of the substrate and before forming the N-N1 device layers on the second surface of the substrate, a protective layer covering the N1 device layers is formed on the first surface of the substrate. The protective layer is then removed after the N-N1 device layers are formed on the second surface of the substrate.

[0088] In this embodiment, each device layer includes a device region and a cap structure. For device layers directly formed on the substrate, both the device region and the cap structure are formed on the substrate. For device layers not directly formed on the substrate, the device region and the cap structure are formed on the cap structure of the adjacent device layer. Taking the case where N device layers are all stacked on the first surface of the substrate as an example, the device region and cap structure of the first device layer are formed on the first surface of the substrate, the device region and cap structure of the second device layer are formed on the cap structure of the first device layer, and so on, with the device region and cap structure of the Nth device layer formed on the cap structure of the (N-1)th device layer. Taking the case of N device layers stacked on two surfaces of a substrate as an example, the device region and cap structure in the first device layer are formed on the first surface of the substrate, the device region and cap structure in the second device layer are formed on the cap structure in the first device layer, and so on, the device region and cap structure in the N1 device layer are formed on the cap structure in the N1-1 device layer; the device region and cap structure in the N1+1 device layer are formed on the second surface of the substrate, the device region and cap structure in the N1+2 device layer are formed on the cap structure in the N1+1 device layer, and so on, the device region and cap structure in the N device layer are formed on the cap structure in the N-1 device layer.

[0089] In this embodiment, for a device layer directly formed on the substrate surface, the device region in the device layer and the substrate together constitute one or more resonators. For a device layer formed on a cap structure in an adjacent device layer, the device region in the device layer and the cap structure in the adjacent device layer together constitute one or more resonators. Taking the case of 3 (i.e., N=3) device layers stacked on the first surface of the substrate as an example, the device region in the first device layer and the substrate together constitute one or more resonators, the device region in the second device layer and the cap structure in the first device layer together constitute one or more resonators, and the device region in the third device layer and the cap structure in the second device layer together constitute one or more resonators. Taking the case of three device layers stacked on the first surface of the substrate and two device layers stacked on the second surface of the substrate (i.e., N=5, N1=3) as an example, the device region in the first device layer and the substrate constitute one or more resonators; the device region in the fourth device layer and the substrate constitute one or more resonators; the device region in the second device layer and the cap structure in the first device layer constitute one or more resonators; the device region in the third device layer and the cap structure in the second device layer constitute one or more resonators; and the device region in the fifth device layer and the cap structure in the fourth device layer constitute one or more resonators. Furthermore, a cavity is formed between the cap structure and the device region in each device layer. It should be noted that this invention does not limit the specific type of resonator in the stacked structure, including but not limited to bulk acoustic wave resonators and surface acoustic wave resonators. All resonators in the stacked structure can be of the same type or different types, and this invention does not limit this in any way.

[0090] For ease of description, the device region in the i-th device layer is referred to as the i-th device region, the cap structure in the i-th device layer is referred to as the i-th cap structure, the cavity between the cap structure and the device region in the i-th device layer is referred to as the i-th cavity, and the resonator formed by the device region in the i-th device layer and the substrate (for the case where the i-th device layer is directly formed on the substrate) or the cap structure in the adjacent device layer (for the case where the i-th device layer is not directly formed on the substrate) is referred to as the i-th resonator, where i = 1, 2, ..., N.

[0091] In this embodiment, a portion of the resonators in the stacked structure are used to construct the transmit filter, and the remaining resonators are used to construct the receive filter. That is, all resonators used to construct the transmit and receive filters are integrated into a single stacked structure. It should be noted that this invention does not limit the specific distribution of the resonators used to construct the transmit and receive filters. For the case where all N device layers are stacked on the first surface of the substrate, preferably, the 1st to N2nd resonators are used to construct the transmit filter (or receive filter), and the N2+1th to Nth resonators are used to construct the receive filter (or transmit filter), where N2 is a positive integer less than N. For example, when N=2 and N2=1, the 1st resonator is used to construct the transmit filter (or receive filter), and the 2nd resonator is used to construct the receive filter (or transmit filter); or, for example, when N=4 and N2=2, the 1st and 2nd resonators are used to construct the transmit filter (or receive filter), and the 3rd and 4th resonators are used to construct the receive filter (or transmit filter); and so on. For the case where N device layers are stacked on the two surfaces of a substrate, preferably, all resonators on the first surface of the substrate (i.e., the 1st to the N1st resonators) are used to construct the transmit filter (or receive filter), and all resonators on the second surface of the substrate (i.e., the N1+1st to the Nth resonators) are used to construct the receive filter (or transmit filter). Those skilled in the art will understand that the above examples should not be construed as limiting the distribution of resonators used to construct the transmit and receive filters. The resonators used to construct the transmit and receive filters can be distributed in any feasible manner according to the actual design. Taking the case where all N device layers are stacked on the first surface of the substrate as an example, the 1st to the N2-1st resonators and some of the N2nd resonators can be used to construct the transmit filter (or receive filter), while the remaining N2nd resonators and the N2+1st to the Nth resonators can be used to construct the receive filter (or transmit filter); and so on.

[0092] It should be noted that when a device region in a device layer, together with the substrate or the cap structure in an adjacent device layer, forms two or more resonators, these two or more resonators are considered to be located in the same layer. In some applications, resonators located between different layers need to be electrically connected. In this case, forming a stacked structure also requires the step of forming an interlayer conductive structure, which is used to achieve the longitudinal connection of resonators located between different layers. The interlayer conductive structure penetrates at least one cap structure of N device layers to achieve electrical connection to the device regions in different device layers, thereby achieving electrical connection to the resonators located in different layers. It should be noted that, for cases where resonators are formed on both sides of the substrate, the interlayer conductive structure may also need to penetrate the substrate to achieve electrical connection between the resonators located on both sides of the substrate. Furthermore, for cases where resonators located between different layers do not need electrical connection, only the connection between resonators located in the same layer is involved, which can be achieved using existing conventional connection methods between resonators in the same layer. Typically, the interlayer conductive structure can be implemented through conductive vias, metal wires, etc.

[0093] In this embodiment, in addition to providing a substrate and forming N vertically stacked device layers on the substrate, forming the stacked structure also includes the step of forming a signal extraction structure, wherein the signal extraction structure is used to extract the signal of the resonator in the stacked structure to the outside of the stacked structure. The signal extraction structure further includes a first extraction portion and a second extraction portion, wherein one of the first extraction portion and the second extraction portion is used to extract the signal of the resonator forming the transmit filter to the outside of the stacked structure, and the other of the first extraction portion and the second extraction portion is used to extract the signal of the resonator forming the receive filter to the outside of the stacked structure. The positions of the first extraction portion and the second extraction portion are related to the layout of the resonators from which they extract signals. For example, in the case where all N device layers are stacked on the first surface of the substrate, when the first to N2 resonators are used to construct a transmit filter (or receive filter) and the N2+1 to N resonators are used to construct a receive filter (or transmit filter), preferably, a first lead-out is formed on the substrate side (e.g., using a conductive via penetrating the substrate) to lead the signals of the first to N2 resonators to the outside of the stacked structure; a second lead-out is disposed on the Nth cap structure side (e.g., using a conductive via penetrating the Nth cap structure) to lead the signals of the N2+1 to Nth resonators to the outside of the stacked structure. For example, in the case of N device layers stacked on two surfaces of a substrate, when the first to N1 resonators are used to construct a transmit filter (or receive filter) and the N1+1 to N resonators are used to construct a receive filter (or transmit filter), preferably, a first lead-out is formed on the Nth cap structure side (e.g., using a conductive via penetrating the Nth cap structure) to lead the signals of the N1+1 to Nth resonators to the outside of the stacked structure; a second lead-out is formed on the N1 cap structure side (e.g., using a conductive via penetrating the N1 cap structure) to lead the signals of the first to N1 resonators to the outside of the stacked structure. Those skilled in the art will understand that the formation positions of the first and second lead-outs described above are merely preferred embodiments and should not be construed as limiting the positional settings of the first and second lead-outs. In other embodiments, when all N device layers are stacked on the first surface of the substrate, the first lead-out may be disposed on the Nth cap structure side, or simultaneously on both the substrate side and the Nth cap structure side; when N device layers are stacked on both surfaces of the substrate, the first lead-out may be disposed on the N1st cap structure side, or simultaneously on both the N1st cap structure side and the Nth cap structure side. The same applies to the second lead-out; for simplicity, it will not be elaborated further here. It should also be noted that the specific number of the first and second leads is determined by the actual circuit design.For example, in one application scenario, the first lead-out needs to serve not only as an input and output terminal but also to connect to electronic components (such as inductors) in the package substrate. In this case, there are three first leads. The same applies to the second lead-out; for the sake of simplicity, it will not be elaborated upon here.

[0094] Preferably, after forming the signal lead-out structure, contact points are formed on the surface of the signal lead-out structure exposed outside the stacked structure for connection between the signal lead-out structure and the packaging substrate. Hereinafter, the contact points formed on the first lead-out portion exposed outside the stacked structure are referred to as first contact points, and the contact points formed on the second lead-out portion exposed outside the stacked structure are referred to as second contact points. It should be noted that the specific number of first contact points depends on the number of first leads, and the specific number of second contact points depends on the number of second leads; no limitation is made here. The materials of the first and second contact points include, but are not limited to, gold, silver, copper, aluminum, titanium, tungsten, nickel, and alloys.

[0095] In step S101, the stacked structure is mounted onto the packaging substrate. When the signal lead-out structure is formed on the same side of the stacked structure, the stacked structure is mounted on the packaging substrate by directly soldering the first contact point and the second contact point to the packaging substrate. When the signal lead-out structure is formed on both sides of the stacked structure, the contact point on one side can be directly soldered to the packaging substrate, and the contact point on the other side can be connected to the packaging substrate through a conductor (e.g., metal wire, metal sheet, etc.) to achieve the mounting of the stacked structure on the packaging substrate.

[0096] Typically, the method for manufacturing a duplexer provided by the present invention further includes forming a molding compound (not shown) on a packaging substrate to cover the stacked structure. The molding compound can be made using existing conventional molding compound materials, and the present invention does not impose any limitations on this.

[0097] The duplexer manufacturing method provided by this invention effectively improves the integration density of the duplexer by fully utilizing the vertical space to integrate the transmitting and receiving filters into a single stacked structure, thereby significantly reducing the module area of ​​the duplexer and facilitating its miniaturization. Furthermore, since the transmitting and receiving filters are integrated into a single stacked structure, compared to existing duplexers where the transmitting and receiving filters are formed on different substrates, implementing this invention can reduce the number of wafers used, thereby lowering the manufacturing cost of the duplexer.

[0098] There are multiple ways to form N device layers. The following description uses three preferred embodiments to illustrate the formation of N vertically stacked device layers on the first surface of a substrate. Those skilled in the art will understand that forming vertically stacked device layers on both sides of the substrate is equivalent to performing two separate vertically stacked device layers on one side of the substrate; therefore, the formation of N vertically stacked device layers on both surfaces of the substrate will not be described here.

[0099] In a preferred embodiment, the steps for vertically stacking N device layers are as follows:

[0100] First, the first device layer is formed as follows: First, a first device region is formed on a first surface of the substrate. Next, a first sacrificial material covering the first device region is deposited and patterned on the substrate, retaining only the portion above the first device region. Then, a first capping layer covering the first sacrificial material is deposited on the substrate. After the first capping layer is formed, vias exposing the first sacrificial material are formed on it, and the first sacrificial material is removed through these vias, thereby forming a first cavity between the first capping layer and the first device region. Next, a second capping layer to a M1 capping layer are sequentially deposited on the first capping layer, wherein the second capping layer fills the vias on the first capping layer, and M1 is an integer and M1≥2. The first capping layer to the M1 capping layer together constitute a first capping structure, which, together with the first device region, constitutes the first device layer.

[0101] Next, device layers 2 through N are formed sequentially. The process of forming the i-th (2≤i≤N) device layer is as follows: First, the i-th device region is formed on the i-1-th cap structure in the i-1-th device layer. Then, the i-th sacrificial material covering the i-th device region is deposited on the i-1-th cap structure and patterned, retaining only the portion above the i-th device region. Next, a first cap layer covering the i-th sacrificial material is deposited on the i-1-th cap structure. After the first cap layer is formed, a via is formed on it to expose the i-th sacrificial material, and the i-th sacrificial material is removed through the via, thereby forming the i-th cavity between the first cap layer and the i-th device region. Then, the second cap layer through the M-th device layer is deposited sequentially on the first cap layer. i Cap layer, M i It is an integer and M i ≥2, wherein the second capping layer fills the through-holes in the first capping layer. The first capping layer to the Mth... i The cap layers together constitute the i-th cap structure, and the i-th cap structure and the i-th device region together constitute the i-th device layer.

[0102] It should be noted that (1) in this embodiment, the i-th (i = 1, 2, ... N) cap structure is a multi-layer structure and the second cap layer fills the through holes on the first cap layer. In this way, it is beneficial to seal the i-th cavity after it is formed, thereby effectively avoiding contamination from subsequent processes. (2) The multi-layer structure of the cap structure can achieve better water and oxygen barrier effect. (3) The materials of any two adjacent cap layers in the cap structure preferably have opposite stresses. In this case, the cap structure can be in a low-stress state, thereby effectively preventing the cap structure from warping, which is beneficial to improving the yield of the duplexer. The present invention does not limit the number of cap layers. The specific number of cap layers depends on the actual design requirements of the duplexer. In addition, the present invention does not limit the specific materials of each cap layer. Any material with opposite stress and suitable for deposition is applicable to the present invention. In a specific embodiment, each cap structure includes 3 cap layers. The first and third cap layers are made of silicon dioxide, and the second cap layer is made of silicon nitride. Furthermore, those skilled in the art will understand that in other embodiments, all cap layers in the cap structure may also be made of the same material, in which case the cap structure presents a single-layer integral structure.

[0103] In another preferred embodiment, the steps for vertically stacking N device layers are as follows:

[0104] First, the first device layer is formed as follows: First, a first device region is formed on the first surface of the substrate. Next, a first sacrificial material covering the first device region is deposited on the substrate and patterned, retaining only the portion above the first device region. Then, a first capping layer covering the first sacrificial material is deposited on the substrate. Next, a second capping layer to a M1 capping layer are sequentially deposited on the first capping layer, where M1 is an integer and M1≥2. The first to M1 capping layers together constitute the first capping structure, which, together with the first device region, constitutes the first device layer.

[0105] For the case where N≥3, the second to N-1 device layers are then formed sequentially. The process of forming the i-th (2≤i≤N-1) device layer is as follows: First, the i-th device region is formed on the i-1-th cap structure in the i-1-th device layer. Next, the i-th sacrificial material covering the i-th device region is deposited on the i-1-th cap structure and patterned, retaining only the portion above the i-th device region. Then, the first cap layer covering the i-th sacrificial material is deposited on the i-1-th cap structure. Finally, the second to M-th device layers are sequentially deposited on the first cap layer. i Cap layer, M i It is an integer and M i ≥2, where the first capping layer to the Mth layer iThe cap layers together constitute the i-th cap structure, and the i-th cap structure and the i-th device region together constitute the i-th device layer. For the case where N equals 2, proceed directly to the next steps.

[0106] Next, an Nth device region is formed on the N-1th cap structure in the N-1th device layer; an Nth sacrificial material covering the Nth device region is deposited on the N-1 cap structure and patterned thereon, retaining only the portion above the Nth device region; and a first cap layer covering the Nth sacrificial material is deposited on the N-1 cap structure.

[0107] Next, the first capping layer covering the Nth sacrificial material is etched downwards until a through hole is formed through the Nth sacrificial material to the first sacrificial material, and the Nth sacrificial material to the first sacrificial material is removed in one go through the through hole, thereby forming the corresponding Nth cavity to the first cavity.

[0108] Finally, a second capping layer is sequentially deposited on the first capping layer in the Nth device layer, up to the Mth layer. N Cap layer, wherein the second cap layer fills the through-holes in the first cap layer, M N It is an integer and M N ≥2. From the first cap layer to the Mth layer N The cap layers together constitute the Nth cap structure, and the Nth cap structure and the Nth device region together constitute the Nth device layer.

[0109] In yet another preferred embodiment, the steps for vertically stacking N device layers are as follows:

[0110] First, the first device region is formed on the substrate.

[0111] Next, a first sacrificial material covering the first device region is deposited and patterned on the substrate, retaining only the portion above the first device region; a first capping material covering the first sacrificial material is deposited on the substrate, and the first capping material is planarized until the first sacrificial material is exposed. The planarized first capping material constitutes a first capping structure, which, together with the first device region, constitutes the first device layer; a second device region is formed on the first capping structure, wherein the second device region is located on the first sacrificial material; the first sacrificial material is removed, for example, by forming vias (i.e., release holes), to form a first cavity between the second device region and the first device region;

[0112] For the case where N≥3, repeat the above steps: deposit the (i+1)th sacrificial material covering the (i+1)th device region on the (i)th (1≤i≤N-2)th cap structure and pattern it, retaining only the portion above the (i+1)th device region; deposit the (i+1)th cap material covering the (i+1)th sacrificial material on the (i)th cap structure, and planarize the (i+1)th cap material until the (i+1)th sacrificial material is exposed. The planarized (i+1)th cap material constitutes the (i+1)th cap structure, which, together with the (i+1)th device region, constitutes the (i+1)th device layer; form the (i+2)th device region on the (i+1)th cap structure, wherein the (i+2)th device region is located on the (i+1)th sacrificial material; remove the (i+1)th sacrificial material by, for example, forming vias (i.e., release holes) to form the (i+1)th cavity between the (i+2)th device region and the (i+1)th device region. For the case where N=2, directly perform the subsequent steps.

[0113] Finally, the Nth sacrificial material covering the Nth device region is deposited and patterned on the N-1th cap structure in the N-1th device layer, retaining only the portion above the Nth device region; a first cap layer covering the Nth sacrificial material is deposited on the N-1th cap structure, and a through-hole is formed in the first cap layer to remove the Nth sacrificial material, thereby forming the Nth cavity between the first cap layer and the Nth device region; a second cap layer to the Mth cap layer are sequentially deposited on the first cap layer. N Cap layer, M N It is an integer and M N ≥2, where the first capping layer to the Mth layer N The cap layers together constitute the Nth cap structure, and the second cap layer fills the vias on the first cap layer. The Nth device region and the Nth cap structure together constitute the Nth device layer.

[0114] It should be noted that (1) in the aforementioned preferred embodiments, the cap structures in the non-top device layers (i.e., the first device layer to the (N-1)th device layers) of the stacked structure are the same. Those skilled in the art will understand that in other embodiments, the cap structures in the non-top device layers may also be different. For example, some cap structures in the non-top device layers may be implemented using the methods in the first two embodiments, while other cap structures in the non-top device layers may be implemented using the methods in the third embodiment. This invention does not limit this in any way. (2) In the prior art, caps are usually implemented using wafers, and the caps and substrates are connected by, for example, Au-Au bonding. In this invention, the cap structure in the top device layer (i.e., the Nth device layer) is formed by deposition. In this way, the number of wafers used can be effectively reduced, and the bonding process is not required, thereby effectively reducing the manufacturing cost of the device. Those skilled in the art will understand that, depending on the actual design requirements, the cap structure in the top device layer may also be formed by bonding using conventional caps. For example, after forming the device region in the top device layer, a conventional cap is provided and bonded to the cap structure where the device region is located.

[0115] For the device region formed on the substrate, it includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure. Each stacked structure is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer, and a upper electrode from the direction closest to the substrate to the direction furthest from the substrate. Those skilled in the art will understand that in other embodiments, the stacked structure may also include conventional seed layers, passivation layers, etc. The acoustic reflection structure is formed on or within the substrate. For example, the acoustic reflection structure may be a groove formed on the substrate and an air gap formed with the stacked structure formed on the groove, or it may be a Bragg reflector layer formed on the substrate surface, or even an opening penetrating the substrate. Regardless of the form of the acoustic reflection structure, to ensure the resonator can function properly, the acoustic reflection structure and its corresponding lower electrode, piezoelectric layer, and upper electrode in the stacked structure have an overlapping region in the device thickness direction.

[0116] For device layers formed on cap structures within adjacent device layers, the device regions vary depending on the cap structure they occupy. Let's continue with the example of N vertically stacked device layers formed on the first surface of a substrate. The i-th (1≤i≤N-1) cap structure is a multilayer structure deposited using the aforementioned method (i.e., the i-th cap structure includes M...). iIn the case of a capping layer, the (i+1)th device region includes one or more stacked structures and a corresponding acoustic reflection structure for each stacked structure. For each stacked structure, it is formed on the i-th capping structure and sequentially includes a lower electrode, a piezoelectric layer, and a upper electrode from the direction closest to the substrate to the direction furthest from the substrate. The acoustic reflection structure is formed on or within the i-th capping structure. For example, the acoustic reflection structure can be an air gap formed by a groove formed on the i-th capping structure and the stacked structure formed on the groove, or it can be a Bragg reflector layer formed on the surface of the i-th capping structure. Regardless of the form of the acoustic reflection structure, to ensure the resonator functions properly, the acoustic reflection structure overlaps with the lower electrode, piezoelectric layer, and upper electrode in its corresponding stacked structure in the device thickness direction. For the case where the i-th (1≤i≤N-1) cap structure is formed by planarization using the aforementioned method, the i+1-th device region includes only one or more stacked structures. Each stacked structure is formed on the i-th cap structure and located above the i-th cavity. It includes a lower electrode, a piezoelectric layer, and an upper electrode in sequence from the direction closest to the substrate to the direction furthest from the substrate. The lower electrode, piezoelectric layer, and upper electrode overlap with the i-th cavity in the device thickness direction. In this way, the i-th cavity can play the role of sound wave reflection without the need to form an additional sound reflection structure.

[0117] The following will combine Figures 3(a) to 3(j) , Figures 4(a) to 4(e) , Figures 5(a) to 5(g) as well as Figures 6(a) to 6(c) The manufacturing method of the duplexer provided by the present invention will be described with reference to four preferred embodiments.

[0118] In a preferred embodiment, the method for manufacturing a duplexer includes the following steps: First, as shown in FIG3(a), a substrate 100 is provided, and one or more grooves are etched on a first surface of the substrate 100 and a sacrificial layer 102-1 is filled in the grooves. In addition, conductive blind vias 101 are formed on the substrate 100 for subsequent implementation of the first lead-out portion. Next, as shown in FIG3(b), a stacked structure corresponding to each groove location is formed on the substrate 100, each stacked structure including, from bottom to top, a lower electrode 104-1, a piezoelectric layer 105-1, and an upper electrode 106-1; the stacked structure is etched to form a via (not shown) exposing the sacrificial layer 102-1, and the sacrificial layer 102-1 is removed through the via to form an air gap 103-1 as an acoustic reflection structure. The stacked structure and the air gap 103-1 constitute a first device region. Next, as shown in FIG3(c), a first sacrificial material 107-1 is formed above the stacked structure, and a first capping layer 108-1-1 covering the first sacrificial material 107-1 is formed. The first capping layer 108-1-1 is etched to form a through-hole 108-1-1' exposing the first sacrificial material. Next, as shown in FIG3(d), the first sacrificial material is removed through the through-hole 108-1-1' to form a first cavity 109-1 between the first capping layer 108-1-1 and the stacked structure in the first device region. Next, as shown in FIG3(e), a second capping layer 108-1-2 is formed on the first capping layer 108-1-1. The second capping layer 108-1-2 together with the first capping layer 108-1-1 constitutes a first capping structure. The first capping structure together with the first device region constitutes a first device layer. Next, as shown in Figure 3(f), one or more grooves are etched on the first cap structure, and a sacrificial layer 102-2 is filled in the grooves, forming an interlayer conductive structure 110-1 that penetrates the first cap structure. Next, as shown in Figure 3(g), a stacked structure corresponding to each groove is formed on the first cap structure. Each stacked structure, from bottom to top, includes a lower electrode 104-2, a piezoelectric layer 105-2, and an upper electrode 106-2. The stacked structure is etched to form a via (not shown) exposing the sacrificial layer 102-2, and the sacrificial layer 102-2 is removed through this via to form an air gap 103-2. The stacked structure and the air gap 103-2 formed on the first cap structure constitute the second device region. A second sacrificial material (not shown) is formed above the stacked structure, and a first cap layer 108-2-1 covering the second sacrificial material is formed. The first cap layer 108-2-1 is etched to form a via exposing the second sacrificial material. The second sacrificial material is removed through a through-hole to form a second cavity 109-2 between the stacked structure in the first capping layer 108-2-1 and the second device region.A second cap layer 108-2-2 is formed on the first cap layer 108-2-1. The first cap layer 108-2-1 and the second cap layer 108-2-2 together constitute the second cap structure. The second cap structure and the second device region together constitute the second device layer. Then, as shown in FIG3(h), the third device layer and the fourth device layer are formed in the aforementioned manner. For the i-th device region in the i-th device layer (i=3, 4), the air gap as the acoustic reflection structure is indicated by reference numeral 103-i. The lower electrode, piezoelectric layer and upper electrode in the stacked structure are indicated by reference numerals 104-i, 105-i and 106-i, respectively. For the i-th cap structure in the i-th device layer (i = 3, 4), the first cap layer and the second cap layer are represented by reference numerals 108-i-1 and 108-i-2, respectively, and the i-th cavity between the i-th cap structure and the i-th device region is represented by reference numeral 109-i. Furthermore, after forming the third cap structure, an interlayer conductive structure 110-3 is formed penetrating the third cap structure. Next, as shown in FIG3(i), a second lead-out portion 111 penetrating the fourth cap structure is formed, and the second surface of the substrate 100 is thinned until a conductive blind via is exposed to form the first lead-out portion 101. Finally, as shown in FIG3(j), a first contact point 301 is formed on the first lead-out portion 101, and a second contact point 302 is formed on the second lead-out portion 111. The first contact point 301 is soldered to the packaging substrate 400, and the second contact point 302 is connected to the packaging substrate 400 via a metal wire 500. This completes the installation of the stacked structure on the packaging substrate 400.

[0119] In another preferred embodiment, compared with the foregoing embodiments (i.e. Figures 3(a) to 3(j)The manufacturing method provided in the illustrated embodiment differs from that in this embodiment, all air gaps (i.e., acoustic reflection structures) and cavities in all device layers are formed in a single step after the formation of the first cap layer in the fourth cap structure. From providing the substrate 100 to the formation of the first cap layer in the fourth cap structure, this embodiment differs from the previous embodiments in that no through-holes are formed to remove the sacrificial material originally filling the air gaps and cavities. For simplicity, as shown in FIG. 4(a), the structure after the formation of the first cap layer in the fourth cap structure is directly drawn. In FIG. 4(a), the same reference numerals as in FIG. 3(j) represent the same components; FIG. 3(j) can be directly referred to and will not be repeated here. In Figure 4(a), reference numerals 102-3 and 102-4 represent the sacrificial layers filled in the grooves of the third and fourth cap structures, respectively. Reference numerals 107-2, 107-3, and 107-4 represent the second sacrificial material originally filling the second cavity, the third sacrificial material originally filling the third cavity, and the fourth sacrificial material originally filling the fourth cavity, respectively. Next, as shown in Figure 4(b), a through-hole 200 is etched downwards from the first cap layer of the fourth cap structure, penetrating all four device layers to expose the sacrificial material 107-i and the sacrificial layer 102-i (i = 1, 2, 3, 4). Then, as shown in Figure 4(c), the sacrificial material 107-i and the sacrificial layer 102-i (i = 1, 2, 3, 4) are removed through the through-hole 200, thereby forming all the air gaps and cavities in the corresponding spaces at once. Next, as shown in Figure 4(d), a second cap layer is formed in the fourth cap structure, and the through-holes in the first cap layer of the fourth cap structure are filled. It should be noted that the through-holes 200 penetrate the third cap structure, the second cap structure, and the first cap structure. The portion of the through-hole 200 penetrating the i-th cap structure is indicated by reference numeral 112-i in Figure 4(d) (i = 1, 2, 3). Furthermore, a second lead-out portion 111 penetrating the fourth cap structure is formed, and the second surface of the substrate 100 is thinned until a conductive blind via is exposed, thereby forming a first lead-out portion 101. Finally, as shown in Figure 4(e), a first contact point 301 is formed on the first lead-out portion 101, and a second contact point 302 is formed on the second lead-out portion 111. The first contact point 301 is soldered to the packaging substrate 400, and the second contact point 302 is connected to the packaging substrate 400 via a metal wire 500. This completes the mounting of the stacked structure on the packaging substrate 400.

[0120] In another preferred embodiment, the method for manufacturing the duplexer includes the following steps: First, as shown in FIG5(a), a first device region is formed on a first surface of a substrate 100. The first device region includes one or more stacked structures and air gaps 103-1 corresponding to each stacked structure. Each stacked structure includes, from bottom to top, a lower electrode 104-1, a piezoelectric layer 105-1, and an upper electrode 106-1. Furthermore, a conductive blind via 101 is formed on the substrate 100 for the subsequent implementation of the first lead-out portion. Next, as shown in FIG5(b), a first sacrificial material 107-1 is formed above the stacked structure, and a first capping material 108-1' covering the first sacrificial material 107-1 is formed. Next, as shown in FIG5(c), the first capping material 108-1' is planarized until the first sacrificial material 107-1 is exposed. The remaining portion of the first capping material 108-1' after the planarization operation constitutes the first capping structure 108-1. Furthermore, after forming the first cap structure, an interlayer conductive structure 110-1 is formed through the first cap structure. Next, as shown in FIG5(d), a stacked structure covering the first sacrificial material 107-1 is formed on the first cap structure 108-1. This stacked structure, from bottom to top, includes a lower electrode 104-2, a piezoelectric layer 105-2, and an upper electrode 106-2. Next, as shown in FIG5(e), the stacked structure above the first sacrificial material 107-1 is etched to form a via (not shown) exposing the first sacrificial material 107-1, and the first sacrificial material 107-1 is removed through this via to form a first cavity 109-1 between the upper and lower stacked structures. At this point, the first device layer is formed, and simultaneously, the second device region is formed. Next, as shown in FIG5(f), the second device layer and the third device region, and the third device layer and the fourth device region, are formed in the same manner, and after the fourth device region is formed, the fourth cap structure is formed according to the aforementioned method. In this design, the second cap structure is indicated by reference numeral 108-2, and the second cavity is indicated by reference numeral 109-2; the lower electrode, piezoelectric layer, and upper electrode in the stacked structure of the i-th (i=3, 4) device region are indicated by reference numerals 104-i, 105-i, and 106-i, respectively; the i-th (i=3, 4) cap structures are indicated by reference numeral 108-i; and the i-th (i=3, 4) cavities are indicated by reference numeral 109-i. Furthermore, an interlayer conductive structure 110-3 penetrating the third cap structure and a second lead-out portion 111 penetrating the fourth cap structure are formed, and the second surface of the substrate 100 is thinned until a conductive blind via is exposed to form the first lead-out portion 101. Finally, as shown in Figure 5(g), a first contact point 301 is formed on the first lead-out portion 101, and a second contact point 302 is formed on the second lead-out portion 111. The first contact point 301 is soldered to the packaging substrate 400, and the second contact point 302 is connected to the packaging substrate 400 via a metal wire 500. This completes the mounting of the stacked structure on the packaging substrate 400.

[0121] In another preferred embodiment, the method for manufacturing a duplexer includes the following steps: First, as shown in FIG6(a), a first device layer and a second device layer are sequentially stacked on the first surface of a substrate 100, wherein, after the formation of a first cap structure, an interlayer conductive structure 110-1 penetrating the first cap structure is formed, and a second lead-out portion 111 penetrating the second cap structure is formed. Next, as shown in FIG6(b), a third device layer and a fourth device layer are sequentially stacked on the second surface of a substrate 100, wherein, after the formation of a third cap structure, an interlayer conductive structure 110-3 penetrating the third cap structure is formed, and a first lead-out portion 101 penetrating the fourth cap structure is formed. It should be noted that, for the i-th device region in the i-th device layer (i = 1, 2, 3, 4), the air gap as an acoustic reflection structure is indicated by reference numeral 103-i, and the lower electrode, piezoelectric layer, and upper electrode in the stacked structure are indicated by reference numerals 104-i, 105-i, and 106-i, respectively. For the i-th cap structure in the i-th device layer (i = 1, 2, 3, 4), the first cap layer and the second cap layer are represented by reference numerals 108-i-1 and 108-i-2, respectively, and the i-th cavity between the i-th cap structure and the i-th device region is represented by reference numeral 109-i. Finally, as shown in FIG6(c), a first contact point 301 is formed on the first lead-out portion 101, and a second contact point 302 is formed on the second lead-out portion 111. The first contact point 301 is soldered to the packaging substrate 400, and the second contact point 302 is connected to the packaging substrate 400 through a metal wire 500. This completes the mounting of the stacked structure on the packaging substrate 400.

[0122] This invention also provides a multiplexer, which includes at least one duplexer, wherein the duplexer is implemented using the aforementioned duplexer of this invention or formed using the aforementioned manufacturing method of this invention. The specific structure of the aforementioned duplexer and the specific steps of the aforementioned duplexer manufacturing method can be found in the relevant sections above, and for the sake of brevity, they will not be repeated here. This invention does not limit the specific type of multiplexer; for example, it can be a triplexer, a quadruplexer, etc. The multiplexer formed based on the duplexer and its manufacturing method provided by this invention also has the advantages of high integration, small module area, and low cost.

[0123] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other components, units, or steps, and the singular does not exclude the plural. Multiple components, units, or devices recited in the system claims may also be implemented by a single component, unit, or device in software or hardware.

[0124] The above-disclosed embodiments are merely some preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A duplexer, characterized in that, The duplexer includes: A packaging substrate and a stacked structure disposed on the packaging substrate; The stacked structure includes a substrate, N device layers and a signal lead-out structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure. N is an integer and N≥2. For a device layer directly formed on the substrate, the device region and capping structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators; for a device layer not directly formed on the substrate, the device region and capping structure are formed on the capping structure of an adjacent device layer, and the device region and the capping structure of the adjacent device layer together constitute one or more resonators; an independent cavity is formed between the capping structure and the device region in each device layer; the resonators in the stacked structure are used to construct a transmit filter and a receive filter: The first resonator to the N2nd resonator are used to construct one of the transmitting filter and the receiving filter, and the N2+1th resonator to the Nth resonator are used to construct the other of the transmitting filter and the receiving filter, where N2 is a positive integer and N2 is less than N; The signal extraction structure extracts the signal from the stacked structure to the outside of the stacked structure; The signal extraction structure includes a first extraction part and a second extraction part, wherein the first extraction part penetrates the substrate and is used to extract the signals from the first resonator to the N2 resonator to the outside of the stacked structure; The second lead-out portion penetrates the cap structure in the Nth device layer and is used to lead the signal from the N2+1th resonator to the outside of the stacked structure.

2. The duplexer according to claim 1, characterized in that, in: The N device layers are stacked longitudinally on the first surface of the substrate, and are arranged sequentially from the closest to the substrate to the furthest from the substrate, from the 1st device layer to the Nth device layer, wherein the Nth device layer is the top device layer among the N device layers; Wherein, the resonator formed by the device region in the i-th device layer and the substrate or the cap structure in the adjacent device layer is the i-th resonator, and the cavity formed between the cap structure and the device region in the i-th device layer is the i-th cavity, where i is an integer and 1≤i≤N.

3. The duplexer according to claim 1, characterized in that, in: N1 device layers are stacked longitudinally on the first surface of the substrate, and are arranged sequentially from the closest to the substrate to the furthest from the substrate, from the 1st device layer to the N1th device layer. The N1th device layer is the top device layer among the N1 device layers, and N1 is a positive integer and N1 < N. N-N1 device layers are stacked longitudinally on the second surface of the substrate, and are arranged sequentially from the N1+1th device layer to the Nth device layer from the direction closest to the substrate to the direction furthest from the substrate. The Nth device layer is the top device layer among the N-N1 device layers. Wherein, the resonator formed by the device region in the i-th device layer and the substrate or the cap structure in the adjacent device layer is the i-th resonator, and the cavity formed between the cap structure and the device region in the i-th device layer is the i-th cavity, where i is an integer and 1≤i≤N.

4. The duplexer according to claim 2 or 3, characterized in that, in: If the i-th device layer is not the top-level device layer; The cap structure in the i-th device layer includes M i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Cap layer; The first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M. i The first cap layer has a through hole communicating with the i-th cavity, and the second cap layer fills the through hole on the first cap layer; or The cap structure in the i-th device layer includes M i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Cap layer; The first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M. i The M i Each cap layer has a through hole that penetrates its own thickness and communicates with the i-th cavity; or The cap structure in the i-th device layer is formed on the substrate or on the cap structure in the adjacent device layer by deposition, and an i-th opening through its own thickness is opened at a position corresponding to the device area in the i-th device layer; the device area in the (i+1)-th device layer is formed above the i-th opening, thereby forming the i-th cavity between the cap structure and the device area in the i-th device layer.

5. The duplexer according to claim 4, characterized in that, in: If the i-th device layer is the top device layer, the cap structure in the i-th device layer includes M. i One cap layer, M i It is an integer and M i ≥2; the M i The capping layers are from the 1st capping layer to the Mth capping layer. i Cap layer; The first capping layer is formed on the substrate or on a capping structure in the adjacent device layer by deposition, and forms the i-th cavity between it and the device region in the device layer; the k-th capping layer is formed on the (k-1)-th capping layer by deposition, where k is an integer and 2≤k≤M. i The first cap layer has a through hole communicating with the Nth cavity, and the second cap layer fills the through hole on the first cap layer.

6. The duplexer according to claim 5, characterized in that, in: The cap structure in the i-th device layer includes M i In the case of a cap layer, the M i In a capping layer, the stresses of any two adjacent capping layers are opposite.

7. The duplexer according to claim 6, characterized in that, in: M i =3； The first capping layer and the third capping layer are both made of silicon dioxide, and the second capping layer is made of silicon nitride.

8. The duplexer according to claim 5, characterized in that, in: For a device layer directly formed on the substrate, the device region includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure; wherein each stacked structure is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer and an upper electrode in the direction from near the substrate to far from the substrate; the acoustic reflection structure is formed on the substrate or within the substrate, and the acoustic reflection structure and the lower electrode, piezoelectric layer and upper electrode in the corresponding stacked structure have an overlapping area in the device thickness direction.

9. The duplexer according to claim 5, characterized in that, in: For the i-th device layer, which is not the top device layer and whose cap structure includes M i In the case of a capping layer, the device region in the (i+1)th device layer includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure; wherein each stacked structure is formed on the capping structure of the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode from the direction near the substrate to the direction away from the substrate; the acoustic reflection structure is formed on or within the capping structure of the i-th device layer, and the acoustic reflection structure and the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure have an overlapping area in the device thickness direction.

10. The duplexer according to claim 5, characterized in that, in: In the case where the i-th device layer is not the top device layer and the cap structure therein has an i-th opening, the device region in the (i+1)-th device layer includes one or more stacked structures; wherein each stacked structure is formed on the i-th opening of the cap structure in the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer and an upper electrode from the direction closer to the substrate to the direction farther from the substrate, and the lower electrode, the piezoelectric layer and the upper electrode have an overlapping area with the i-th cavity in the device thickness direction.

11. The duplexer according to claim 3, characterized in that, in: The first resonator to the N1st resonator are used to construct the transmitting filter, and the N1+1th resonator to the Nth resonator are used to construct the receiving filter; The signal output structure includes a first output portion and a second output portion, wherein the first output portion penetrates the cap structure in the N1th device layer and is used to output the signals from the 1st resonator to the N1th resonator to the outside of the stacked structure, and the second output portion penetrates the cap structure in the Nth device layer and is used to output the signals from the N1+1th resonator to the Nth resonator to the outside of the stacked structure.

12. The duplexer according to any one of claims 1 to 3, characterized in that, in: The stacked structure also includes an interlayer conductive structure that extends through at least one of the N device layers through a cap structure, for connecting resonators in different layers.

13. A method for manufacturing a duplexer, characterized in that, The manufacturing method includes: A stacked structure is formed, which includes a substrate, N device layers and a signal lead-out structure. The N device layers are stacked vertically on the substrate, and each device layer includes a device region and a cap structure. N is an integer and N≥2. For a device layer directly formed on the substrate, the device region and cap structure are formed on the substrate, and the device region and the substrate together constitute one or more resonators; for a device layer not directly formed on the substrate, the device region and cap structure are formed on the cap structure of an adjacent device layer, and the device region and the cap structure of the adjacent device layer together constitute one or more resonators; a cavity is formed between the cap structure and the device region in each device layer; the resonators in the stacked structure are used to construct a transmit filter and a receive filter; the 1st to N2nd resonators are used to construct one of the transmit filter and the receive filter, and the N2+1st to Nth resonators are used to construct the other of the transmit filter and the receive filter, where N2 is a positive integer and N2 is less than N; The signal extraction structure extracts the signal from the stacked structure to the outside of the stacked structure; The step of forming the signal take-out structure includes: forming a first take-out portion through the substrate, the first take-out portion being used to take out signals from the first resonator to the N2 resonator to the outside of the stacked structure; and forming a second take-out portion through the cap structure in the Nth device layer, the second take-out portion being used to take out signals from the N2+1 resonator to the Nth resonator to the outside of the stacked structure; A packaging substrate is provided and the stacked structure is mounted onto the packaging substrate.

14. The manufacturing method according to claim 13, characterized in that, in, The steps for forming N vertically stacked device layers on a substrate include: A first to Nth device layer are formed sequentially on the first surface of the substrate in a longitudinally stacked manner. The resonator formed by the device region in the i-th device layer and the cap structure in the substrate or the adjacent device layer is the i-th resonator. The cavity formed between the cap structure and the device region in the i-th device layer is the i-th cavity. i is an integer and 1≤i≤N.

15. The manufacturing method according to claim 13, characterized in that, in, The steps for forming N vertically stacked device layers on a substrate include: A first device layer to an N1 device layer are formed sequentially on the first surface of the substrate, and a N1+1 device layer to an N device layer are formed sequentially on the second surface of the substrate, where N1 is a positive integer and N1 < N; wherein, the resonator formed by the device region in the i-th device layer and the cap structure in the substrate or the adjacent device layer is the i-th resonator, and the cavity formed between the cap structure and the device region in the i-th device layer is the i-th cavity, where i is an integer and 1 ≤ i ≤ N.

16. The manufacturing method according to claim 14, characterized in that, in, The steps for forming the i-th device layer include: a1. A device region in the i-th device layer is formed on the substrate or on the cap structure in the i-1th device layer; a2. Deposit and pattern the i-th sacrificial material covering the device region on the substrate or on the cap structure in the (i-1)-th device layer, retaining only the portion above the device region; a3. A first capping layer covering the i-th sacrificial material is deposited on the substrate or on the capping structure in the i-1th device layer. A through-hole is formed in the first capping layer and the i-th sacrificial material is removed through the through-hole, thereby forming an i-th cavity between the first capping layer and the device region of the i-th device layer. a4. Sequentially deposit the second capping layer to the Mth capping layer on the first capping layer. i Cap layer, M i It is an integer and M i ≥2, wherein the first capping layer to the Mth layer i The cap layers together constitute the cap structure in the i-th device layer, and the second cap layer fills the through-holes on the first cap layer.

17. The manufacturing method according to claim 14, characterized in that, in, The step of sequentially forming longitudinally stacked device layers 1 to N on the first surface of the substrate includes: b1. Form a device region in the i-th device layer on the substrate or on the capping structure in the (i-1)-th device layer; deposit and pattern an i-th sacrificial material covering the device region on the substrate or on the capping structure in the (i-1)-th device layer, retaining only the portion above the device region; deposit a first capping layer covering the i-th sacrificial material on the substrate or on the capping structure in the (i-1)-th device layer, and sequentially deposit a second capping layer to the M-th capping layer on the first capping layer. i Cap layers, wherein the first cap layer to the Mth cap layer i The cap layers together constitute the cap structure in the i-th device layer; where i ≠ N, M i It is an integer and M i ≥2; b2. Form a device region in the Nth device layer on the cap structure in the N-1th device layer; deposit and pattern the Nth sacrificial material covering the device region on the cap structure in the N-1th device layer, retaining only the portion above the device region; deposit a first cap layer covering the Nth sacrificial material on the cap structure in the N-1th device layer. b3. Etch downwards from the first capping layer covering the Nth sacrificial material until a through hole is formed through the Nth sacrificial material to the first sacrificial material, and remove the Nth sacrificial material to the first sacrificial material through the through hole, thereby forming the corresponding Nth cavity to the first cavity; b4. Sequentially deposit a second capping layer up to the Mth capping layer on the first capping layer in the Nth device layer. N Cap layer, M N It is an integer and M N ≥2, wherein the first capping layer to the Mth layer N The cap layers together constitute the cap structure in the Nth device layer, and the second cap layer fills the vias on the first cap layer.

18. The manufacturing method according to claim 15, characterized in that, in, The step of sequentially forming longitudinally stacked device layers 1 to N on the first surface of the substrate includes: c1. A device region in the first device layer is formed on the substrate; c2. Deposit and pattern the i-th sacrificial material covering the device region on the substrate or on the cap structure in the (i-1)-th device layer, retaining only the portion above the device region; deposit the i-th cap material covering the i-th sacrificial material on the substrate or on the cap structure in the (i-1)-th device layer, and planarize the i-th cap material until the i-th sacrificial material is exposed, the planarized i-th cap material forming the cap structure in the i-th device layer; form the device region in the (i+1)-th device layer on the cap structure in the i-th device layer, wherein the device region in the (i+1)-th device layer is located on the i-th sacrificial material; remove the i-th sacrificial material to form the i-th cavity between the device region in the (i+1)-th device layer and the device region in the i-th device layer; wherein, i ≠ N; c3. Deposit and pattern the Nth sacrificial material covering the device region in the Nth device layer on the capping structure in the (N-1)th device layer, retaining only the portion above the device region; deposit a first capping layer covering the Nth sacrificial material on the capping structure in the (N-1)th device layer, create a through-hole in the first capping layer and remove the Nth sacrificial material through the through-hole, thereby forming the Nth cavity between the first capping layer and the device region of the Nth device layer; sequentially deposit the second capping layer to the Mth capping layer on the first capping layer. N Cap layer, M N It is an integer and M N ≥2, wherein the first capping layer to the Mth layer N The cap layers together constitute the cap structure in the Nth device layer, and the second cap layer fills the vias on the first cap layer.

19. The manufacturing method according to claim 17 or 18, characterized in that, in: The M i In a capping layer, the stresses of any two adjacent capping layers are opposite.

20. The manufacturing method according to claim 19, characterized in that, in: M i =3； The first capping layer and the third capping layer are both made of silicon dioxide, and the second capping layer is made of silicon nitride.

21. The manufacturing method according to any one of claims 17 or 18, characterized in that, in: For a device layer directly formed on the substrate, the device region includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure; wherein each stacked structure is formed on the substrate and sequentially includes a lower electrode, a piezoelectric layer and an upper electrode in the direction from near the substrate to far from the substrate; the acoustic reflection structure is formed on the substrate or within the substrate, and the acoustic reflection structure and the lower electrode, piezoelectric layer and upper electrode in the corresponding stacked structure have an overlapping area in the device thickness direction.

22. The manufacturing method according to claim 17 or 18, characterized in that, in: When i≠N, the device region in the (i+1)th device layer includes one or more stacked structures and an acoustic reflection structure corresponding to each stacked structure; wherein each stacked structure is formed on the capping structure of the i-th device layer and sequentially includes a lower electrode, a piezoelectric layer, and an upper electrode from the direction near the substrate to the direction away from the substrate; the acoustic reflection structure is formed on or within the capping structure of the i-th device layer, and the acoustic reflection structure and the lower electrode, piezoelectric layer, and upper electrode in the corresponding stacked structure have an overlapping area in the device thickness direction.

23. The manufacturing method according to claim 19, characterized in that, in: When i≠N, the device region in the (i+1)th device layer includes more than one stacked structure; wherein each of the stacked structures is formed on the cap structure in the i-th device layer and located above the i-th cavity, and sequentially includes a lower electrode, a piezoelectric layer and an upper electrode in the direction from near the substrate to far from the substrate, and the lower electrode, the piezoelectric layer and the upper electrode have an overlapping area with the i-th cavity in the device thickness direction.

24. The manufacturing method according to claim 16, characterized in that, in: The first resonator to the N1st resonator are used to construct the transmitting filter, and the N1+1th resonator to the Nth resonator are used to construct the receiving filter; The step of forming the signal lead-out structure includes: forming a first lead-out portion through the cap structure in the N1st device layer, the first lead-out portion being used to lead the signals from the first resonator to the N1st resonator to the outside of the stacked structure; And forming a second lead-out portion through the cap structure in the Nth device layer, the second lead-out portion being used to lead the signal from the N1+1 resonator to the Nth resonator to the outside of the stacked structure.

25. The manufacturing method according to any one of claims 14 to 16, characterized in that, in: The manufacturing method further includes forming an interlayer conductive structure that penetrates at least one of the N device layers through a cap structure for connecting resonators in different layers.

26. A multiplexer, characterized in that, The multiplexer includes: At least one duplexer, which is implemented using a duplexer as described in any one of claims 1 to 12, or formed using a manufacturing method as described in any one of claims 13 to 25.

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