Convolution operation circuit and operation method

Abstract

The application provides a convolution operation circuit and an operation method thereof. The convolution operation circuit comprises control logic, a data buffer module connected with the control logic, and a multiplier. The multiplier comprises at least two parallel operation modules. Each operation module comprises a signal input end, at least two parallel memristors, and a signal output end. The multiplier is used for performing convolution operation on the data to be processed entering the operation module through the signal input end to obtain corresponding operation results. The control logic is used for reading the operation results output by the signal output end into the data buffer module for data storage. The application can flexibly realize the setting of multiple convolution weights.

Description

Technical Field

[0001] This invention relates to the field of operational circuit technology, and more specifically, to a convolution operation circuit and a convolution operation method thereof. Background Technology

[0002] Currently, the circuit structure for convolution operations using ReRAM memristors typically uses a multiply-add operation with a primary resistor, such as... Figure 1 As shown in the structure of the existing convolution operation circuit, for example, if the conductance G of the ReRAM is taken as the weight of the convolution kernel, and the input data is converted into voltage by the DAC circuit, then the current of each parallel ReRAM circuit is I = V*G. If a series of ReRAMs are connected in parallel, then the corresponding current output is the result of multiplying and adding all the weights and the data: that is, I = I1 + I2 + I3 = V1*G1 + V2*G2 + V3*G3. I is finally converted back into data output by the ADC conversion circuit.

[0003] However, to achieve the goal of allowing users to set arbitrary weights using the above circuit structure, the conductance of the ReRAM needs to be precisely controlled. Generally, the weights after quantization need to be 6 to 8 bits, or even more. However, due to the complexity of the ReRAM process itself, it is not possible to achieve precise adjustment of multi-bit weights, which affects the flexibility of the convolution circuit. In addition, when there are many weights, it will also occupy a lot of memory space, which is not conducive to the widespread application of convolution circuits. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a convolution operation circuit and operation method to solve the problems that existing convolution circuits cannot achieve arbitrary adjustment of convolution weights, resulting in poor circuit flexibility and low accuracy.

[0005] The convolution operation circuit provided by this invention includes: control logic, a data buffer module connected to the control logic, and a multiplier-accumulator; wherein, the multiplier-accumulator includes at least two parallel operation modules, each operation module including a signal input terminal, at least two parallel memristors, and a signal output terminal; the multiplier-accumulator is used to perform convolution operation on the data to be processed entering the operation module through the signal input terminal to obtain the corresponding operation result; the control logic is used to read the operation result output by the signal output terminal into the data buffer module for data storage.

[0006] Alternatively, an alternative technical solution is that the memristor includes a resistor section and a selector connected in series with the resistor section.

[0007] Alternatively, an optional technical solution is to set up a DAC module between the signal input terminal and the arithmetic module, and an ADC module between the signal output terminal and the control logic; the DAC module is used to perform digital-to-analog conversion on the data to be processed, and the ADC module is used to perform analog-to-digital conversion on the calculation result.

[0008] Alternatively, an alternative technical solution is to set up one DAC module, and connect one DAC module in parallel with all the memristors; or, set up the same number of DAC modules as the number of memristors, and connect each DAC module in series with the corresponding memristor.

[0009] In addition, an optional technical solution is that when there is one DAC module, the convolution operation circuit also includes a multiplexer and a BL bit line corresponding to the memristor; wherein, the multiplexer is connected to the corresponding BL bit line; the multiplexer is used to select the output voltage of the DAC module.

[0010] In addition, an optional technical solution includes a gating device connected to the memristor; wherein the gating device is connected to the data to be processed and the BL bit line; the gating device is used to control the operating mode of the memristor, the operating mode including convolution weight configuration, convolution operation, and convolution weight storage.

[0011] In addition, an alternative technical solution is to have the number of memristors connected in parallel correspond to the number of bits in the convolution weights.

[0012] Alternatively, an alternative technical solution is to express the resistance of all memristors connected in parallel within the same operational module as follows:

[0013]

[0014] The output current of the arithmetic module is expressed as:

[0015]

[0016] The formula for expressing convolution weights is as follows:

[0017]

[0018] Among them, R0~R n-1 This represents the resistance value of the memristors connected in parallel, where n represents the number of resistance values, and R... H R represents the highest resistance among n resistance values, m represents the number of high-resistance values, and R represents the highest resistance among n resistance values. L This represents the lowest resistance among n resistance values, nm represents the number of low-resistance values, and G represents the conductance.

[0019] Alternatively, the convolution operation circuit can be a 1TnR circuit or an nTnR circuit.

[0020] According to another aspect of the present invention, a convolution operation method is provided, which performs convolution operation using the convolution operation circuit described above. The method includes: setting the operating mode of a memristor to a convolution weight configuration based on control logic; setting the resistance value of the memristor based on the configured convolution weight and determining the input matrix of the data to be processed; selecting the operating mode of the memristor as convolution operation based on control logic; performing digital-to-analog conversion on the input matrix through a DAC module and starting the convolution operation to obtain the corresponding operation result; performing analog-to-digital conversion on the operation result through an ADC module and caching it to a data cache module; determining whether the convolution operation is completed based on control logic, and outputting the analog-to-digital converted operation result when the convolution operation is completed.

[0021] Using the above-mentioned convolution operation circuit and operation method, the working mode of the memristor can be adjusted based on the control logic, and the resistance value of the memristor can be set according to the pre-configured convolution weight. Then, the corresponding operation result can be obtained through convolution operation and cached in the data cache module. It can not only be compatible with the effects of convolution cloud and data storage, but also achieve precise adjustment of convolution weight. It has fast operation speed, low power consumption and high accuracy.

[0022] To achieve the foregoing and related objectives, one or more aspects of the invention include the features that will be described in detail below. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to encompass all such aspects and their equivalents. Attached Figure Description

[0023] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings:

[0024] Figure 1 This is a schematic diagram of the structure of an existing convolution operation circuit;

[0025] Figure 2 This is a schematic diagram of the convolution operation circuit according to an embodiment of the present invention;

[0026] Figure 3 This is a partial structural schematic diagram of the convolution operation circuit according to an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the convolution operation circuit according to another embodiment of the present invention;

[0028] Figure 5 This is a flowchart of a convolution operation method according to an embodiment of the present invention;

[0029] Figure 6This is a detailed flowchart of the convolution operation method according to an embodiment of the present invention.

[0030] In all the accompanying drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed Implementation

[0031] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0032] To describe in detail the convolution operation circuit and operation method of the present invention, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figure 2 A schematic structure of a convolution operation circuit according to an embodiment of the present invention is shown.

[0034] like Figure 2 As shown, the convolution operation circuit of this embodiment includes: control logic, a data buffer module connected to the control logic, and a multiplier-accumulator. The multiplier-accumulator includes at least two parallel operation modules, each including a signal input terminal, at least two parallel memristors, and a signal output terminal. The multiplier-accumulator performs convolution operations on the data to be processed (or input data, hereinafter the same) entering the operation module through the signal input terminal to obtain the corresponding operation result. The control logic reads the operation result output from the signal output terminal into the data buffer module for data storage or retrieval. The multiplier-accumulator is composed of multiple parallel operation modules, and by setting the resistance value of the memristors within the corresponding operation module, the convolution weights can be flexibly adjusted.

[0035] The memristor may include its own resistor and a selector connected in series with the resistor. In addition, each memristor is connected to a gating device. The gating signal of the gating device is the operating mode selection signal, which can be used to indicate whether the memristor is used for convolution weight configuration, convolution operation or convolution weight storage. During the operation, the operating mode of the memristor can be flexibly selected through the control logic, thereby realizing the corresponding function.

[0036] Specifically, in one embodiment of the present invention, a DAC module is provided between the signal input terminal and the arithmetic module, and an ADC module is provided between the signal output terminal and the control logic; wherein, the DAC module is used to perform digital-to-analog conversion on the data to be processed, and the ADC module is used to perform analog-to-digital conversion on the arithmetic result, wherein the setting of the DAC module can be set according to specific circuit requirements or requirements.

[0037] For example, in the convolution operation circuit of this embodiment of the invention, one DAC module is set, and one DAC module is connected in parallel with all the memristors respectively; wherein, each operation module of the multiply-accumulator is provided with one DAC module, and each operation module represents one input data multiplied by one weight. When there are n weights and n input data, n operation modules are set accordingly. Each operation module can be individually set with spacing weights and configured with corresponding input data voltages.

[0038] In the above embodiments, when only one DAC module is provided in each operation module, the convolution operation circuit also includes a multiplexer (MUX) and a BL bit line corresponding to the memristor; wherein, the multiplexer is connected to the corresponding BL bit line and is used to select the output voltage of the DAC module.

[0039] Figure 3 A partial schematic structure of a convolution operation circuit according to another embodiment of the present invention is shown.

[0040] like Figure 3 As shown, in this embodiment, the number of DAC modules is the same as the number of memristors, and each DAC module is connected in series with the corresponding memristor. That is, the input of each memristor is adjusted to the data converted by the DAC module. Under this circuit structure, the mux and BL circuits can be omitted. The voltage provided by the DAC module can serve two purposes: one is to set the resistance value of the memristor, and the other is to serve as the input for convolution operation.

[0041] In addition, the signal output from the memristor can be input to the ADC module after the diode is turned on, so as to obtain the data output result. The diode of WL is mainly to prevent voltage crosstalk between different WL, so as to ensure the accuracy and precision of the calculation.

[0042] In another specific embodiment of the present invention, the convolution operation circuit may further include a gating device connected to the memristor; wherein, the gating device is connected to the data to be processed and the BL bit line, and the gating device is used to control the operating mode of the memristor. The operating mode includes convolution weight configuration, convolution operation, and convolution weight storage. Through the control logic, the operating mode of the memristor can be flexibly selected during the operation, thereby realizing different functions.

[0043] It can be seen that for each arithmetic module, the number of memristors connected in parallel corresponds to the number of bits in the convolution weights. The number of memristors depends on the number of bits in the convolution weights. For example, if the convolution weights are 6 bits, the minimum number of effective resistor levels in the memristors within the arithmetic module is 2^6 - 1. Therefore, the number of resistors can be represented by setting the resistor to 0 or 1. 6 The value of .

[0044] Specifically, the resistance of all memristors connected in parallel within the same operational module is expressed as:

[0045]

[0046] The output current of the arithmetic module is expressed as:

[0047]

[0048] The formula for expressing convolution weights is as follows:

[0049]

[0050] Among them, R0~R n-1 This represents the resistance value of the memristors connected in parallel, where n represents the number of resistance values, and R... H R represents the highest resistance among n resistance values, m represents the number of high-resistance values, and R represents the highest resistance among n resistance values. L This represents the lowest resistance among n resistance values, nm represents the number of low-resistance values, and G represents the conductance.

[0051] Figure 4 The structure of a convolution operation circuit according to another specific embodiment of the present invention is shown.

[0052] like Figure 4 As shown, in this embodiment, the 1TnR circuit of the convolution operation circuit can be switched to an nTnR circuit. That is, the convolution operation circuit can be either a 1TnR circuit or an nTnR circuit. In this case, the diode of WL0 does not need to be set. The specific circuit structure can be set or adjusted according to the requirements.

[0053] According to the convolution operation circuit of the present invention, memristors are used for convolution operations. The convolution weights can be flexibly set by connecting memristors in parallel, which can be compatible with the circuit results of convolution operations and data storage, and has high operation accuracy and strong flexibility.

[0054] Corresponding to the above-described convolution operation circuit, the present invention also provides a convolution operation method.

[0055] Specifically, Figure 5 A schematic flowchart of the operation method of the convolution operation circuit according to an embodiment of the present invention is shown.

[0056] like Figure 5 As shown, the operation method of the convolution operation circuit in this embodiment of the invention includes:

[0057] S110: Sets the memristor's operating mode to the convolution weight configuration based on control logic;

[0058] S120: Set the resistance value of the memristor based on the configured convolution weights and determine the input matrix of the data to be processed;

[0059] S130: Based on the control logic, the operating mode of the memristor is selected as convolution operation;

[0060] S140: The input matrix is ​​converted from digital to analog using the DAC module, and the convolution operation is started to obtain the corresponding operation result;

[0061] S150: The ADC module performs analog-to-digital conversion on the calculation results and caches them in the data cache module;

[0062] S160: Determine whether the convolution operation is complete based on the control logic, and when the convolution operation is complete, output the operation result after analog-to-digital conversion.

[0063] Specifically, Figure 6 The detailed flow of the operation method of the convolution operation circuit according to an embodiment of the present invention is shown.

[0064] like Figure 6 As shown, in the convolution operation method of this embodiment of the invention, after starting, the working mode of the memristor is first selected as weight configuration, and then the matrix weights are configured through control logic, that is, the process of setting the resistance value. Then, the input matrix is ​​selected as the data to be processed or the output data. Then, the working mode of the memristor is selected as convolution operation again. Then, the input data is input to the DAC module for digital-to-analog conversion. Then, the convolution operation of the memristor is started, the corresponding operation result is obtained, and output to the ADC module. Then, the result of the ADC module is read into the data buffer module, and it is determined whether the matrix operation is completed. If it is not completed, it continues to return to the data input interface; otherwise, it returns the final calculation result and ends.

[0065] It should be noted that the embodiments of the above convolution operation method can be referred to the description in the embodiments of the convolution operation circuit, and will not be repeated here.

[0066] The convolution operation circuit and operation method provided by the present invention can select multiple working modes of the memristor based on control logic, and set the resistance value of the memristor according to the pre-configured convolution weights. Then, the corresponding operation results are obtained through convolution operation and cached in the data cache module. It can not only be compatible with the effects of convolution cloud and data storage, but also switch between multiple states through voltage settings to realize the setting of arbitrary bit width and precision weights, so as to achieve the effect of precise adjustment of convolution weights. It has fast operation speed, low power consumption and high precision.

[0067] The convolution operation circuit and method according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various modifications can be made to the convolution operation circuit and method proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the content of the appended claims.

Claims

1. A convolution operation circuit, characterized in that, It includes: control logic, a data cache module connected to the control logic, and a multiply-accumulator; wherein, The multiply-accumulator includes at least two parallel arithmetic modules, each arithmetic module including a signal input terminal, at least two parallel memristors, and a signal output terminal; The multiply-accumulator is used to perform convolution operations on the data to be processed that enters the processing module through the signal input terminal, so as to obtain the corresponding operation result; The control logic is used to read the calculation result output by the signal output terminal into the data cache module for data storage; The at least two memristors connected in parallel are used to set the convolution weights. The number of memristors connected in parallel corresponds to the number of bits in the convolution weights, so as to adjust the convolution weights by the number of memristors connected in parallel and their resistance values. The resistance of all memristors connected in parallel within the same operational module is expressed as: Among them, R0~R n-1 This represents the resistance value of the memristors connected in parallel, where n represents the number of resistance values. It also includes a gating device connected to the memristor, the gating device being used to control the operating mode of the memristor, the operating mode including convolution weight configuration, convolution operation, and convolution weight storage.

2. The convolution operation circuit as described in claim 1, characterized in that, The memristor includes a resistive portion and a selector connected in series with the resistive portion.

3. The convolution operation circuit as described in claim 1, characterized in that, A DAC module is provided between the signal input terminal and the arithmetic module, and an ADC module is provided between the signal output terminal and the control logic; The DAC module is used to perform digital-to-analog conversion on the data to be processed, and the ADC module is used to perform analog-to-digital conversion on the calculation result.

4. The convolution operation circuit as described in claim 3, characterized in that, The DAC module is configured as one, and each DAC module is connected in parallel with all the memristors; or, The number of DAC modules is the same as the number of memristors, and each DAC module is connected in series with its corresponding memristor.

5. The convolution operation circuit as described in claim 3, characterized in that, When one DAC module is provided, the convolution operation circuit further includes a multiplexer and a BL bit line corresponding to the memristor; wherein... The multiplexer is connected to the corresponding BL bit line; The multiplexer is used to select the output voltage of the DAC module.

6. The convolution operation circuit as described in claim 5, characterized in that, The gating device is connected to the data to be processed and the BL bit line.

7. The convolution operation circuit as described in claim 6, characterized in that, The output current of the computing module is expressed as: The formula for expressing the convolution weights is as follows: Among them, R0~R n-1 This represents the resistance value of the memristors connected in parallel, where n represents the number of resistance values, and R... H R represents the highest resistance among n resistance values, m represents the number of such high resistance values, and R L The value represents the lowest resistance among the n resistance values, nm represents the number of the lowest resistance values, and G represents the conductance.

8. The convolution operation circuit as described in claim 1, characterized in that, The convolution operation circuit is a 1TnR circuit or an nTnR circuit.

9. A convolution operation method, characterized in that, The method of performing convolution operation using the convolution operation circuit as described in any one of claims 1-8 includes: The operating mode of the memristor is set to the convolution weight configuration based on the control logic. The resistance value of the memristor is set based on the configured convolution weights, and the input matrix of the data to be processed is determined. Based on the control logic, the operating mode of the memristor is selected as convolution operation; The input matrix is ​​converted from digital to analog using the DAC module, and convolution operation is initiated to obtain the corresponding operation result; The calculation results are converted from analog to digital by the ADC module and cached in the data cache module; The control logic determines whether the convolution operation is complete, and when the convolution operation is complete, the result after analog-to-digital conversion is output.

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