Vertical suspended two-dimensional field effect device and method of manufacturing the same

Abstract

The application provides a vertical suspended two-dimensional field effect device and a manufacturing method thereof. The device comprises a plurality of field effect transistors which are arranged in parallel and spaced apart perpendicularly to a substrate, and the periphery of each field effect transistor is filled with a first insulating material to realize isolation from adjacent field effect transistors, and a connecting layer is arranged between the root of the adjacent field effect transistors and the substrate. The method comprises the following steps: processing a plurality of field effect transistor prototypes which are arranged in parallel and spaced apart perpendicularly to the substrate on the substrate, and the two ends of the field effect transistor prototypes are reserved with a skeleton connection; performing a deposition process, then performing a first etching to reserve a deposit on the surface of the field effect transistor prototype to form a protective layer; arranging a first etching mask on the skeleton, and adopting an oxidation etching process to disconnect the connection between the root of the field effect transistor prototype and the substrate; arranging a connecting layer on the disconnected root, and then performing a patterning process to form a source electrode, a gate electrode and a drain electrode of the field effect transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their fabrication technology, and in particular to a vertically suspended two-dimensional field-effect device and its manufacturing method. Background Technology

[0002] Traditional field-effect devices are horizontally mounted on a substrate, meaning that the source, gate, and drain of the field-effect device are all horizontally laid on the silicon substrate. They have mature manufacturing processes to produce. During the manufacturing process, due to the large area of ​​support provided by the silicon substrate, the device height is small, resulting in good structural stability during the process and preventing instability and deformation that could affect quality and yield.

[0003] In addition, multiple field-effect devices on the same substrate often require additional wiring connections. These connections occupy space, which reduces the number and density of devices per unit area, thus affecting the integration level of the semiconductor and hindering miniaturization. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a vertically suspended two-dimensional field-effect device, comprising a substrate and a plurality of field-effect transistor (FET) units arranged perpendicular to the substrate and spaced parallel to each other. Each FET unit is surrounded by a first insulating material to isolate it from adjacent FET units. Each FET unit includes a source, a gate, and a drain. The source / drain is located at the upper end of a vertical plane perpendicular to the substrate, the gate is located at the middle portion of the vertical plane, and the drain / source is located at the lower end of the vertical plane.

[0005] The field-effect transistor unit further includes a root portion located at the lower end of the vertical plane of the field-effect transistor unit perpendicular to the substrate, and located between the drain / source and the substrate. A connection layer is provided between the root portion and the substrate, and at least two field-effect transistor units are interconnected through the connection layer.

[0006] Optionally, the field-effect transistor unit includes a P-type field-effect transistor and / or an N-type field-effect transistor.

[0007] Optionally, the field-effect transistor unit includes opposing P-type field-effect transistors and N-type field-effect transistors, the spacing between the P-type field-effect transistors and the N-type field-effect transistors is smaller than the spacing between two adjacent field-effect transistor units, the substrate includes a plurality of spaced protrusions, the P-type field-effect transistors and the N-type field-effect transistors are located on the protrusions, and a second insulating material is filled between adjacent protrusions.

[0008] Optionally, the first insulating material is different from the second insulating material.

[0009] Optionally, the first insulating material is silicon nitride, and the second insulating material is silicon oxide.

[0010] Optionally, the first insulating material is the same as the second insulating material.

[0011] Optionally, the P-type field-effect transistor and the N-type field-effect transistor are connected through the connection layer.

[0012] Optionally, the connection layer connects two adjacent field-effect transistor units.

[0013] Optionally, the connection layer is a conductive connection layer.

[0014] Optionally, the connecting layer includes at least one of a metal, a semiconductor, and a titanium nitride material.

[0015] This invention also provides a method for manufacturing a vertically suspended two-dimensional field-effect device, comprising the following steps:

[0016] Using a patterning process, multiple prototype field-effect transistor units are formed on a substrate, arranged perpendicularly to the substrate and spaced parallel to each other. The two ends of the prototype field-effect transistor units are connected.

[0017] The source, gate, and drain of a field-effect transistor are formed in the prototype of the field-effect transistor unit through a patterning process.

[0018] A protective layer is formed on the surface of the prototype field-effect transistor unit through a deposition process.

[0019] A first etching mask is provided on the connection end;

[0020] The root of the prototype field-effect transistor is disconnected from the substrate by an oxidation etching process;

[0021] A connecting layer is filled at the break using a filling process.

[0022] Optionally, the prototype field-effect transistor unit is formed through the following process:

[0023] S1 According to the spacing of the parallel field-effect transistor units, a plurality of first molding line film layers with a width equal to the thickness of the field-effect transistor units are disposed parallel to each other on the substrate.

[0024] S2 sets first etching masks at intervals on the substrate surface that intersect with the first forming line film layer according to a set distance;

[0025] S3 performs pre-etching to the total depth of the source, gate, and drain segments of the field-effect transistor unit.

[0026] Multiple prototype field-effect transistor units are formed below the first molding line film layer, arranged perpendicularly to the substrate and spaced parallel to each other, and a portion is retained below the first etching mask to form a skeleton.

[0027] Optionally, the patterning process for forming the source, gate, and drain of the field-effect transistor unit includes:

[0028] S21 Fill the space between the prototype field-effect transistor units with a first insulating material and perform a flattening process, remove the first etching mask, set a second etching mask in the area other than the first etching mask, and perform a second etching to form a first groove of a first depth, the first depth reaching the bottom of the gate of the field-effect transistor unit;

[0029] S22 After the first groove is filled with the second insulating material and leveled, a third etching is performed to remove the second insulating material to form a second groove of a second depth, the second depth reaching the top of the gate of the field-effect transistor unit;

[0030] S23 A first insulating material film layer is formed on the sidewall of the second groove, a gate groove is formed by etching the gate segment through the second groove, the sidewall of the gate groove is oxidized to form a second insulating material layer, a metal layer is formed by filling the gate groove with metal, and the second groove is filled with the first insulating material.

[0031] Optionally, if the field-effect transistor unit prototype includes a P-type field-effect transistor prototype and an N-type field-effect transistor prototype, the P-type field-effect transistor prototype and the N-type field-effect transistor prototype are arranged opposite to each other, and the spacing between the P-type field-effect transistor prototype and the N-type field-effect transistor prototype is smaller than the spacing between two adjacent field-effect transistor unit prototypes.

[0032] Optionally, the prototype of the field-effect transistor unit includes multiple protrusions, and the P-type field-effect transistor prototype and the N-type field-effect transistor prototype are disposed on the same protrusion. A second insulating material is retained between the protrusions by pre-etching.

[0033] The present invention discloses a vertically suspended two-dimensional field-effect device and its manufacturing method. During manufacturing, a framework is provided at both ends of multiple parallel and spaced field-effect transistor prototypes arranged vertically to a substrate. A protective layer is retained on the surface of the field-effect transistor prototypes. Then, under the protection of a first etching mask, an oxidation etching process is performed on the framework to disconnect the connection between the root of the field-effect transistor prototype and the substrate and fill the connection layer. A post-processing process is then performed to form the source, gate, and drain of the field-effect transistor. The resulting vertically suspended two-dimensional field-effect device has a connection layer between the root of the field-effect transistor and the substrate. Each field-effect transistor is interconnected through this connection layer. Therefore, additional wiring connections are needed for each field-effect transistor, avoiding the space occupied by the wiring and thus further improving the integration density of the vertical two-dimensional field-effect device.

[0034] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0035] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0037] Figure 1 This is a three-dimensional schematic diagram of a vertically suspended two-dimensional field-effect device according to an embodiment of the present invention;

[0038] Figure 2 This is a flowchart illustrating a method for manufacturing a vertically suspended two-dimensional field-effect device according to an embodiment of the present invention.

[0039] Figure 3 This is a process flow diagram of the formation process of a prototype field-effect transistor in an embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention;

[0040] Figure 4 This is a post-processing flow chart in an embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention;

[0041] Figure 5 This is a plan view of a prototype field-effect transistor in an embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention;

[0042] Figure 6This is a-a' cross-sectional view of the prototype field-effect transistor after the protective layer is formed in an embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention;

[0043] Figure 7 A cross-sectional view (a-a') showing the root of a prototype field-effect transistor disconnected from the substrate after oxidation etching, in an embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention.

[0044] Figure 8 This is a-a' cross-sectional view of the prototype field-effect transistor in the embodiment of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention after the conductor is filled at the point where the root is disconnected from the substrate.

[0045] Figure 9 The field-effect transistor prototypes in the embodiments of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention include planar views of a P-type field-effect transistor prototype and an N-type field-effect transistor prototype;

[0046] Figure 10 The field-effect transistor prototypes in the embodiments of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention include P-type field-effect transistor prototypes and N-type field-effect transistor prototypes after forming a protective layer, are shown in cross-sectional view a-a'.

[0047] Figure 11 The field-effect transistor prototypes in the embodiments of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention include P-type field-effect transistor prototypes and N-type field-effect transistor prototypes, and the root of the prototypes is disconnected from the substrate after oxidation etching; a-a' cross-sectional view.

[0048] Figure 12 The field-effect transistor prototypes in the embodiments of the manufacturing method of the vertically suspended two-dimensional field-effect device of the present invention include P-type field-effect transistor prototypes and N-type field-effect transistor prototypes, and the a-a' cross-sectional view of the root of the prototype after the conductor is filled at the point where it is disconnected from the substrate. Detailed Implementation

[0049] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0050] like Figure 1As shown, this embodiment of the invention provides a vertically suspended two-dimensional field-effect device, including a substrate 2 and a plurality of field-effect transistor units 1 arranged perpendicular to the substrate and parallel to each other. The periphery of each field-effect transistor unit 1 is filled with a first insulating material 3 to isolate it from adjacent field-effect transistor units. Each field-effect transistor unit 1 includes a source, a gate, and a drain. The source / drain is located at the upper end of the vertical plane of the field-effect transistor unit perpendicular to the substrate. The gate is located at the middle part of the vertical plane of the field-effect transistor unit perpendicular to the substrate. The drain / source is located at the lower end of the vertical plane of the field-effect transistor unit perpendicular to the substrate. Each field-effect transistor unit also includes a root, which is located at the lower end of the vertical plane of the field-effect transistor unit perpendicular to the substrate and is located between the drain / source and the substrate. A connection layer 4 is disposed between the root and the substrate. At least two field-effect transistor units are interconnected through the connection layer 4. The connection layer 4 is a conductive connection layer and can be made of a conductive material, such as a metal or titanium nitride.

[0051] The working principle and beneficial effects of the above technical solution are as follows: The field-effect transistors (FETs) in this solution are vertically arranged with the substrate, and a connection layer is provided between the root of the FET and the substrate. Each FET is interconnected through the connection layer. Supported by the connection layer, the vertical two-dimensional FET is positioned in a near-floating manner with the substrate. Therefore, it is unnecessary to add wiring connections to each FET, avoiding the space occupied by connection lines and thus further improving the integration density of the vertical two-dimensional FET. The first insulating material can generally be silicon nitride, and the connection layer can be made of metal or titanium nitride depending on the process requirements. The FETs in this solution include a source, a gate, and a drain, arranged vertically with the substrate. The upper and lower ends are the source and drain, respectively, and the gate is located between the source and drain. Because the FET is vertically arranged, it occupies a very small substrate area, allowing for a greater number of devices to be arranged per unit area, increasing the integration density and performance of the device.

[0052] In one embodiment, the field-effect transistor is a P-type field-effect transistor or an N-type field-effect transistor, or

[0053] The field-effect transistor includes a P-type field-effect transistor and an N-type field-effect transistor. The P-type field-effect transistor and the N-type field-effect transistor are arranged in pairs, and adjacent pairs of P-type field-effect transistors and N-type field-effect transistors are arranged symmetrically. The chip spacing of the same pair of P-type field-effect transistors and N-type field-effect transistors is smaller than the distance between adjacent pairs. There are multiple spaced protrusions 21 on the substrate. The same pair of P-type field-effect transistors and N-type field-effect transistors are arranged on the same protrusion 21, and adjacent protrusions 21 are filled with a second insulating material 6.

[0054] The working principle and beneficial effects of the above technical solution are as follows: The field-effect transistors in this solution can all be single-type field-effect transistors, either P-type or N-type, or they can be complementary field-effect transistors that simultaneously include both P-type and N-type field-effect transistors. In the complementary field-effect transistors, the P-type and N-type field-effect transistors are arranged in pairs, and adjacent pairs of P-type and N-type field-effect transistors are symmetrically arranged. The chip spacing of the same pair of P-type and N-type field-effect transistors is smaller than the distance between adjacent pairs. Multiple protrusions are formed on the substrate, and the same pair of P-type and N-type field-effect transistors are arranged on the same protrusion. Adjacent protrusions are filled with a second insulating material, thereby ensuring the function of the corresponding vertical two-dimensional field-effect device.

[0055] In one embodiment, multiple field-effect transistors 1 connected by the same connection layer 4 are grouped together, and multiple field-effect transistor groups are provided on the same substrate.

[0056] Adjacent field-effect transistor groups are symmetrically spaced apart, and the gaps are filled with a first insulating material 3.

[0057] The working principle and beneficial effects of the above technical solution are as follows: This solution uses multiple field-effect transistors connected by the same conductor as a group, and multiple field-effect transistor groups are provided on the same substrate; adjacent field-effect transistor groups are symmetrically spaced, which ensures the structural compactness of the field-effect devices on the substrate, thereby improving the overall integration.

[0058] like Figure 2 and Figure 5-12 As shown, this embodiment of the invention provides a method for manufacturing a vertically suspended two-dimensional field-effect device, including the following steps:

[0059] S10 uses a patterning process to form multiple field-effect transistor unit prototypes 11 on a substrate, which are perpendicular to the substrate and arranged in parallel intervals. The two ends of the field-effect transistor unit prototypes 11 are connected by connection terminals 5.

[0060] S20 forms the source, gate, and drain of a field-effect transistor in the prototype field-effect transistor unit 11 through a patterning process;

[0061] S30 forms a protective layer 14 on the surface of the prototype field-effect transistor unit 11 by a deposition process;

[0062] S40 provides a first etching mask on the connecting end 5;

[0063] S50 uses an oxidation etching process to disconnect the root of the prototype field-effect transistor 11 from the substrate;

[0064] S60 uses a filling process to fill the break with a connecting layer 4.

[0065] The working principle and beneficial effects of the above technical solution are as follows: During manufacturing, multiple field-effect transistor (FET) prototypes are fabricated on a substrate, arranged perpendicularly to the substrate and spaced parallel to each other. The two ends of each FET prototype have connection points. A deposition process is performed, followed by a first etching process to leave a protective layer on the surface of the FET prototype. A first etching mask is provided on the connection points, and an oxidation etching process is used to disconnect the root of the FET prototype from the substrate. The disconnection point at the root of the FET prototype is filled with a connection layer, followed by post-processing to form the source, gate, and drain of the FET. A connecting framework is provided at both ends of the multiple FET prototypes arranged parallel to each other perpendicular to the substrate, and a protective layer is left on the surface of the FET prototype. Under the protection of the first etching mask, the framework is subjected to an oxidation etching process. Because the FET prototypes are protected by the framework at both ends, a tensioned framework structure is formed at both ends of the perpendicular FET prototypes, serving as the connection points.

[0066] The connection is made so that the root of the MOSFET prototype will not fall over even after being etched and hollowed out by oxidation. Then, the connection between the root of the MOSFET prototype and the substrate is broken and a connection layer is filled. After post-processing, the source, gate and drain of the MOSFET are formed. The resulting vertically suspended two-dimensional field-effect device has a connection layer between the root of the MOSFET and the substrate. All MOSFETs are interconnected through the connection layer. Therefore, it is not necessary to add circuit connections to each MOSFET, avoiding the space occupied by connection lines, thereby further improving the integration density of the vertical two-dimensional field-effect device. The first insulating material can generally be silicon nitride, etc.

[0067] In one embodiment, such as Figure 3 As shown, the prototype field-effect transistor in step S10 is formed through the following process:

[0068] S1 According to the spacing of the parallel field-effect transistors 1, a plurality of first molding line film layers with a width equal to the thickness of the field-effect transistors are set on the substrate 2 in parallel at intervals.

[0069] S2 sets first etching masks at intervals on the substrate surface that intersect with the first forming line film layer according to a set distance;

[0070] S3 performs pre-etching to the total depth of the source, gate, and drain of the field-effect transistor, forming multiple prototype field-effect transistors arranged perpendicularly to the substrate and spaced parallel to each other below the first molding line film layer. A portion is retained below the first etching mask to form a skeleton, which is the connection terminal.

[0071] The working principle and beneficial effects of the above technical solution are as follows: Based on the spacing of the parallel field-effect transistors, this solution sets multiple first forming line film layers with a width equal to the thickness of the field-effect transistors on the substrate in parallel intervals. According to a set distance, first etching masks intersecting with the first forming line film layers are set on the substrate surface at intervals. Under the joint protection of the first forming line film layers and the first etching mask, pre-etching is performed to the total depth of the source, gate, and drain of the field-effect transistors. This forms multiple field-effect transistor prototypes that are perpendicular to the substrate and arranged in parallel intervals below the first forming line film layers. A portion is retained below the first etching mask to form a skeleton. Due to the first etching mask, the two ends of the formed field-effect transistor prototypes are protected by the skeleton, forming a tension skeleton structure at both ends of the vertical field-effect device prototypes. This ensures that even if the height and thickness of the vertical field-effect device prototypes are relatively large, they can maintain an upright planar shape and will not fall over before filling.

[0072] In one embodiment, such as Figure 4 As shown, in step S30, the post-processing technology includes:

[0073] S21 fills the space between the prototype field-effect transistors with a first insulating material and performs a flattening process, removes the first etching mask, sets a second etching mask in the area other than the first etching mask, and performs a second etching to form a first groove of a first depth, the first depth reaching the bottom of the gate of the field-effect transistor.

[0074] S22 After the first groove is filled with the second insulating material and leveled, a third etching is performed to remove the second insulating material to form a second groove with a second depth, the second depth reaching the top of the gate of the field-effect transistor;

[0075] S23 A first insulating material film layer is formed on the sidewall of the second groove, a gate groove is formed by etching the gate segment through the second groove, the sidewall of the gate groove is oxidized to form a second insulating material layer, a metal layer is formed by filling the gate groove with metal, and the second groove is filled with the first insulating material.

[0076] The working principle and beneficial effects of the above technical solution are as follows: In the post-processing of this solution, after filling the space between the field-effect transistor prototypes with the first insulating material, the gate of the field-effect transistor is shaped by etching the skeleton part. Since the space between the field-effect transistor prototypes has been filled with the first insulating material, the etching of the skeleton part will not cause the field-effect transistor prototypes to fall over, thus ensuring product quality and yield. The second insulating material can generally be silicon oxide.

[0077] In one embodiment, such as Figure 3 and Figure 9-12As shown, if the field-effect transistor prototype includes a P-type field-effect transistor prototype and an N-type field-effect transistor prototype, then the P-type field-effect transistor prototype and the N-type field-effect transistor prototype are arranged in pairs, and the adjacent pairs of P-type field-effect transistor prototypes and N-type field-effect transistor prototypes are arranged symmetrically. The chip spacing of the same pair of P-type field-effect transistor prototypes and N-type field-effect transistor prototypes is smaller than the distance between adjacent pairs.

[0078] In step S2, the spacing of the parallel field-effect transistors includes the wafer spacing and the pair spacing, and the first molding line film layer is set according to the wafer spacing and the pair spacing.

[0079] In step S3, after pre-etching, protrusions 21 and pairs of P-type and N-type field-effect transistor prototypes on the top of protrusions 21 are formed; a second insulating material is filled, and a second pre-etching is performed, leaving the second insulating material between the protrusions 21.

[0080] The working principle and beneficial effects of the above technical solution are as follows: For the manufacturing of complementary field-effect devices including P-type field-effect transistors and N-type field-effect transistors, the setting of the first forming line film layer is set according to the wafer spacing and the inter-pair distance. Since the inter-pair distance is greater than the wafer spacing, after pre-etching, the etching depth at the inter-pair distance is greater than the depth between the wafer spacing, so that protrusions are formed on the substrate under the P-type field-effect transistors and N-type field-effect transistors. On this basis, a second insulating material is filled, and then a second pre-etching is performed to remove the second insulating material between the wafer spacing, but the second insulating material will remain between the protrusions 21, thereby ensuring the formation of complementary field-effect devices.

[0081] In one embodiment, in step S10, before the deposition process, the field-effect transistor is divided into three vertical height segments and doped with different densities. The doping density of the upper and lower height segments is higher than that of the middle height segment. The middle height segment forms the gate prototype, while the upper and lower height segments form the source prototype or the drain prototype, respectively.

[0082] The working principle and beneficial effects of the above technical solution are as follows: This solution arranges the doping process before the deposition process. At this time, the prototype of the vertical field-effect device is fully exposed, and the doping can be carried out simultaneously on both sides of the prototype of the vertical field-effect device, which increases the doping area and improves the doping efficiency. During doping, the first depth is divided into three height segments along the vertical direction for different density doping treatments. The doping density of the upper and lower height segments is higher than that of the middle height segment, which ensures the quality and performance requirements of each part of the device. The gate prototype is formed in the middle height segment, and the source prototype or drain prototype is formed in the upper and lower height segments, respectively.

[0083] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A vertically suspended two-dimensional field effect device, characterized by, The field effect transistor unit is filled with a first insulating material around the periphery of the field effect transistor unit to isolate the field effect transistor unit from adjacent field effect transistor units, the field effect transistor unit includes a source, a gate and a drain, the source / drain is located at the upper end of the vertical plane of the field effect transistor unit perpendicular to the substrate, the gate is located at the middle part of the vertical plane of the field effect transistor unit perpendicular to the substrate, and the drain / source is located at the lower end of the vertical plane of the field effect transistor unit perpendicular to the substrate, The field effect transistor unit further includes a root located at the lower end of the vertical plane of the field effect transistor unit perpendicular to the substrate and between the drain / source and the substrate, a connecting layer is provided between the root and the substrate, each field effect transistor unit is connected to each other through the connecting layer, and the connecting layer includes at least one of metal, semiconductor and titanium nitride material; The field effect transistor unit includes oppositely arranged P-type field effect transistors and N-type field effect transistors, the substrate includes a plurality of spaced protrusions, the P-type field effect transistors and the N-type field effect transistors are located on the protrusions, and the second insulating material is filled between adjacent protrusions.

2. The vertical suspended two-dimensional field effect device of claim 1, wherein, The field effect transistor unit includes P-type field effect transistors and / or N-type field effect transistors.

3. The vertical suspended two-dimensional field effect device of claim 1, wherein, The spacing between the P-type field effect transistor and the N-type field effect transistor is smaller than the spacing between two adjacent field effect transistor units.

4. The vertical suspended two-dimensional field effect device of claim 3, wherein, The first insulating material is different from the second insulating material.

5. The vertical suspended two-dimensional field effect device of claim 4, wherein, The first insulating material is silicon nitride material, and the second insulating material is silicon oxide material.

6. The vertical suspended two-dimensional field effect device of claim 3, wherein, The first insulating material is the same as the second insulating material.

7. The vertical suspended two-dimensional field effect device of claim 3, wherein, The P-type field effect transistor and the N-type field effect transistor are connected through the connecting layer.

8. The vertical suspended two-dimensional field effect device of claim 1, wherein, The connecting layer connects two adjacent field effect transistor units.

9. The vertical suspended two-dimensional field effect device of claim 1, wherein, The connecting layer is a conductive connecting layer.

10. A method of fabricating a vertical suspended two-dimensional field effect device, comprising: The method includes the following steps: A plurality of field effect transistor unit prototypes are formed on the substrate by a patterning process, the field effect transistor unit prototypes are arranged vertically to the substrate and parallel to each other, and the two ends of the field effect transistor unit prototypes are connected by connecting ends; the field effect transistor unit prototypes are formed by the following processes: S1, a plurality of first forming line film layers with a width equal to the thickness of the field effect transistor unit are arranged on the substrate in parallel and at intervals according to the spacing of the field effect transistor units; S2, a first etching mask intersecting the first forming line film layer is arranged on the substrate surface at intervals according to a set distance; and S3, a preliminary etching is performed to a total size depth of the source, gate and drain of the field effect transistor unit, a plurality of field effect transistor unit prototypes are formed below the first forming line film layer and arranged vertically to the substrate and parallel to each other, and a skeleton is formed below the first etching mask; The source, gate and drain of the field effect transistor are formed in the field effect transistor unit prototype by a patterning process. forming a protective layer on the surface of the field effect transistor unit embryo through a deposition process; setting a first etching mask on the connecting end; breaking the root of the field effect transistor embryo from the substrate through an oxidation etching process; filling a connecting layer at the breaking point through a filling process.

11. The method of fabricating a vertical suspended two-dimensional field effect device according to claim 10, wherein The patterning process of forming the source, gate and drain of the field effect transistor unit comprises: S21 filling a first insulating material between the field effect transistor unit embryos and performing a planarization process, removing the first etching mask, setting a second etching mask on the part other than the first etching mask, performing a second etching to form a first recess with a first depth, the first depth reaching the bottom of the gate of the field effect transistor unit; S22 after filling a second insulating material in the first recess and performing a planarization process, performing a third etching to remove the second insulating material to form a second recess with a second depth, the second depth reaching the top of the gate of the field effect transistor unit; S23 setting a first insulating material film layer on the sidewall of the second recess, etching the gate segment through the second recess to form a gate trench, performing an oxidation treatment on the sidewall of the gate trench to form a second insulating material layer, filling the gate trench with a metal layer, and filling the second recess with a first insulating material.

12. The method of fabricating a vertical suspended two-dimensional field effect device of claim 10, wherein, If the field effect transistor unit embryo comprises a P-type field effect transistor embryo and an N-type field effect transistor embryo, the P-type field effect transistor embryo and the N-type field effect transistor embryo are oppositely arranged, and the spacing between the P-type field effect transistor embryo and the N-type field effect transistor embryo is smaller than the spacing between two adjacent field effect transistor unit embryos.

13. The method of claim 12, wherein the vertical suspended two-dimensional field effect device is formed by the steps of: The field effect transistor unit embryo comprises a plurality of protruding parts, the P-type field effect transistor embryo and the N-type field effect transistor embryo are arranged on the same protruding part, and a second insulating material is reserved between the protruding parts through a pre-etching.

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