A method of fabricating a semiconductor device

Abstract

The application discloses a semiconductor device preparation method. The semiconductor device preparation method comprises the following steps: providing a substrate; forming a field oxide layer on the front surface of the substrate; performing pre-diffusion treatment and push joint of a first preset material on the back surface of the substrate; etching a plurality of array-arranged hole grooves in the direction of the interior of the substrate on the back surface of the substrate; wherein the depth of the hole grooves is less than the depth of the push joint; and filling each hole groove with a second preset material to obtain a substrate structure with hole groove filling on the back surface to replace an epitaxial wafer. The technical scheme of the embodiment of the application reduces the process complexity and preparation cost, and has a lower requirement on process precision.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor device. Background Technology

[0002] Currently, when excessive voltage spikes occur at the collector of bipolar devices, a resistor of a certain resistance value is often connected in series to solve the problem. However, this leads to a slower frequency response of the bipolar device and a larger power consumption.

[0003] In existing technologies, the slow response and high power consumption of bipolar devices are often addressed by fabricating high-resistivity epitaxial layers on low-resistivity substrates. This reduces the parasitic capacitance of the depletion layers in the heavily doped N-type regions of the source and drain in MOS transistors or IGBTs, improves the device's immunity to stray charge noise from the substrate, and increases response speed. However, existing methods for fabricating epitaxial wafers using epitaxial processes are costly and complex, requiring high precision in each step of the process. Summary of the Invention

[0004] This invention provides a method for fabricating semiconductor devices to reduce process complexity and the requirements for process precision, and to reduce fabrication costs.

[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:

[0006] Provide a substrate;

[0007] A field oxide layer is formed on the front side of the substrate;

[0008] The back side of the substrate is subjected to a pre-diffusion treatment and bonding of a first preset material;

[0009] Multiple arrayed holes are etched on the back side of the substrate toward the interior of the substrate; wherein the depth of the holes is less than the push-bond depth.

[0010] The second preset material is used to fill each of the holes and grooves to obtain a substrate structure with filled holes and grooves on the back side, which replaces the epitaxial wafer.

[0011] Optionally, forming a field oxide layer on the front side of the substrate includes:

[0012] The field oxide layer is prepared on both the front and back sides of the substrate using a hydrogen-oxygen synthesis method;

[0013] Remove the field oxide layer on the back side of the substrate.

[0014] Optionally, removing the field oxide layer on the back side of the substrate includes:

[0015] A photoresist layer is coated on the surface of the field oxide layer on the front side of the substrate to form a protective layer;

[0016] The field oxide layer on the back side of the substrate is completely etched using hydrofluoric acid.

[0017] Optionally, the thickness of the field oxide layer on the front side of the substrate is 10,000 to 13,000 angstroms.

[0018] Optionally, the pre-diffusion treatment and bonding of the back side of the substrate with a first preset material includes:

[0019] The first preset material is pre-diffusion treated and bonded using a diffusion furnace with silicon carbide furnace tubes.

[0020] Optionally, when performing the pre-diffusion treatment and bonding of the first preset material using a diffusion furnace with silicon carbide furnace tubes, the method further includes:

[0021] A passivation layer is formed on the back side of the substrate.

[0022] Optionally, the etching of a plurality of arrayed slots on the back side of the substrate toward the interior of the substrate includes:

[0023] A femtosecond laser is used to etch the back side of the substrate in the passivation layer to sequentially obtain a plurality of the aforementioned holes.

[0024] Optionally, the etching rate of the femtosecond laser is 3000-3500 mm / s, and the etching spacing is 0.01-0.03 mm.

[0025] Optionally, the etching of a plurality of arrayed slots on the back side of the substrate toward the interior of the substrate includes:

[0026] A photoresist layer is formed by coating the surface of the passivation layer with photoresist.

[0027] The photoresist layer is exposed by exposure, development and dry etching to expose part of the substrate region corresponding to the passivation layer;

[0028] The holes are obtained by etching the exposed substrate regions using a deep trench etching machine.

[0029] Optionally, the longitudinal cross-sectional shape of the slot is a trapezoid with an angle of 80 to 88°.

[0030] The push-bonding depth is 180±5μm, the depth of the hole groove is 165±5μm, and the spacing between two adjacent holes grooves is 20~25μm.

[0031] Optionally, filling each of the holes and grooves with a second preset material includes:

[0032] The second preset material is evaporated using low-pressure chemical vapor deposition and deposited into the pores.

[0033] Optionally, the first preset material includes phosphorus oxychloride; the second preset material includes phosphorus-doped polycrystalline silicon.

[0034] Optionally, obtaining a substrate structure with filled vias on the back side includes:

[0035] The passivation layer on the back side of the substrate is removed using a chemical mechanical polishing process to obtain the substrate structure.

[0036] This invention provides a technical solution that replaces epitaxial wafers by creating deep trenches on the back side and filling them with a corresponding material. A field oxide layer is formed on the front side of the substrate, and a pre-diffusion treatment and push-bonding of a first preset material are performed on the back side of the substrate to form a heavily doped region with a certain carrier concentration gradient. Multiple trenches are etched from the back side of the substrate into the substrate interior, and the trenches are filled with a second preset material to form a substrate structure with a certain carrier concentration gradient from the front side to the back side. Compared to preparing epitaxial wafers using epitaxial processes, the preparation method provided by this invention does not require parameter settings considering various influencing factors of epitaxial layer growth, has lower process complexity, lower requirements for process precision compared to parameter control, and reduces preparation costs.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic flowchart of a semiconductor device fabrication method according to an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of various structures in a semiconductor device fabrication method provided according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic flowchart of another semiconductor device fabrication method provided according to an embodiment of the present invention;

[0042] Figure 4 These are schematic diagrams of various structures in another semiconductor device fabrication method provided according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the specific structure of step S140 in a semiconductor device fabrication method according to an embodiment of the present invention;

[0044] Figure 6 This is a schematic flowchart of another semiconductor device fabrication method provided according to an embodiment of the present invention;

[0045] Figure 7 These are schematic diagrams of various structures in another semiconductor device fabrication method provided according to an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of various structures in another semiconductor device fabrication method provided according to an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] This invention provides a method for fabricating a semiconductor device. Figure 1 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of various structures in a semiconductor device fabrication method provided by an embodiment of the present invention. (Combined with...) Figure 1 and Figure 2The semiconductor device fabrication method specifically includes the following steps:

[0050] S110, providing a substrate 10.

[0051] S120, a field oxide layer 20 is formed on the front side of the substrate 10.

[0052] For example, a field oxide layer is formed on the front side of a cleaned substrate. The field oxide layer is used to protect and passivate the surface of the semiconductor substrate and to form an insulation between the electrode leads of the device and the conductive substrate, preventing device leakage. For example, for a silicon substrate, the field oxide layer formed on the substrate surface is a silicon dioxide layer of a certain thickness.

[0053] S130, Perform pre-diffusion treatment and bonding of the first preset material on the back side of the substrate 10.

[0054] For example, a pre-diffusion treatment of a first preset material is performed on the back side of the substrate, i.e., the first preset material is deposited on the back side of the substrate to control the concentration of the first preset material on the substrate surface. After the pre-diffusion treatment, the first preset material deposited on the back side surface of the substrate is pushed at a high temperature to a certain depth to form a certain junction depth, thereby forming a heavily doped region with a certain carrier concentration gradient on the back side of the substrate. For example, Figure 2 The diagram illustrates the formation of an N-type heavily doped region, with phosphorus oxychloride as the first pre-selected material and a silicon wafer as the substrate. Using phosphorus oxychloride as the phosphorus source, phosphorus pre-diffusion and bonding treatment are performed on the back side of the silicon wafer to form an N-type heavily doped region of a certain depth and with a certain carrier concentration gradient on the back side of the silicon wafer.

[0055] S140, A plurality of arrayed holes 30 are etched on the back side of the substrate 10 toward the interior of the substrate 10; wherein the depth of the holes 30 is less than the push-in depth.

[0056] For example, multiple trenches are formed from the back side of the substrate toward the interior of the substrate. A material film with a certain carrier concentration gradient can be formed within these trenches, thereby creating a carrier concentration gradient from the front side to the back side of the substrate. The etched trenches are located in heavily doped regions of the substrate, thus creating a carrier concentration gradient between the trench locations and the front side of the substrate. Therefore, the trench depth should be less than the push-in depth of the phosphorus source. Specifically, the trench depth and push-in depth can be set according to the actual needs of device fabrication and are not limited here.

[0057] S150: Fill each hole 30 with a second preset material to obtain a substrate structure with filled holes on the back side, in order to replace the epitaxial wafer.

[0058] For example, a second preset material is filled into each etched trench to completely fill the trenches, so that the substrate has a satisfactory carrier concentration gradient from the front to the back side. After the above steps, a substrate structure with multiple trenches on the back side and filled with the second preset material is formed. This substrate structure has a certain carrier concentration gradient, thus replacing the epitaxial wafer fabrication process on the substrate surface, reducing the process difficulty and fabrication cost. For example, the second preset material filled into each trench is phosphorus-doped polycrystalline silicon.

[0059] This embodiment provides a technical solution that replaces the epitaxial wafer by creating deep trenches on the back side and filling them with a corresponding material. A field oxide layer is formed on the front side of the substrate, and a pre-diffusion treatment and push-bonding of a first preset material are performed on the back side of the substrate to form a heavily doped region with a certain carrier concentration gradient. Multiple trenches are etched from the back side of the substrate into the substrate interior, and the trenches are filled with a second preset material to form a substrate structure with a certain carrier concentration gradient from the front side to the back side. Compared to preparing epitaxial wafers using epitaxial processes, the preparation method provided in this embodiment does not require parameter settings considering various influencing factors of epitaxial layer growth, has lower process complexity, lower requirements for process precision compared to parameter control, and reduces preparation costs.

[0060] Optionally, based on the above embodiments, step S130 in the semiconductor device fabrication method specifically includes:

[0061] The first preset material was pre-diffusion and bonding was carried out in a diffusion furnace with silicon carbide furnace tubes.

[0062] Specifically, when performing pre-diffusion treatment and bonding of the corresponding material on the back side of the substrate, the substrate is placed in a diffusion furnace and a certain gas is filled into the diffusion furnace tube to place the substrate in a specific gas atmosphere and perform pre-diffusion treatment under high temperature conditions.

[0063] For example, the diffusion furnace used for pre-diffusion treatment and bonding can be a diffusion furnace with a silicon carbide furnace tube. Silicon carbide furnace tubes have high purity and few impurities, do not contaminate the substrate during pre-diffusion treatment and bonding, and are not easily deformed or cracked, exhibiting good quality. Using a diffusion furnace with a silicon carbide furnace tube ensures better maintenance of the specific atmosphere within the furnace tube, thus shortening the bonding time of the substrate and avoiding prolonged exposure of the substrate to a high-temperature atmosphere. If a diffusion furnace with a furnace tube made of other materials, such as a quartz furnace tube, is used, the quality of the furnace tube is inferior to that of a silicon carbide furnace tube, resulting in poorer maintenance of the specific temperature and gas atmosphere. This can lead to substrate contamination, poorer pre-diffusion treatment and bonding, and a longer bonding time. Prolonged exposure of the substrate to a high-temperature atmosphere during bonding can easily generate defects in the substrate, reducing its quality. Using a poor-quality substrate to fabricate semiconductor devices will also significantly affect the parameters of the semiconductor devices, degrading their performance.

[0064] Optionally, Figure 3 This is a schematic flowchart of another semiconductor device fabrication method provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of various structures in another semiconductor device fabrication method provided by an embodiment of the present invention. Based on the above embodiments, the following embodiments specifically describe the method for forming a field oxide layer on the front side of a substrate. (Combined with...) Figure 3 and Figure 4 The method for fabricating this semiconductor device includes:

[0065] S210, providing a substrate 10.

[0066] S220, a field oxide layer 20 is prepared on both the front and back sides of the substrate 10 using a hydrogen-oxygen synthesis method.

[0067] For example, a substrate is placed in a furnace tube filled with hydrogen and oxygen to grow the material film. In this hydrogen and oxygen atmosphere, a field oxide layer is prepared on the cleaned substrate surface using a hydrogen-oxygen synthesis method. During the preparation of the field oxide layer, field oxide layers of a certain thickness can be grown simultaneously on both the front and back sides of the substrate. For example, the thickness of the field oxide layer on the front side of the substrate is 10,000–13,000 angstroms. Preferably, the thickness of the field oxide layer prepared on the front side of the substrate can be selected to be 10,000 angstroms, which can both protect the semiconductor substrate surface and prevent leakage current in semiconductor devices, while also saving materials and reducing manufacturing costs.

[0068] S230, Remove the field oxide layer 20 on the back side of the substrate 10.

[0069] Specifically, after obtaining a substrate with field oxide layers on both the front and back sides, since the back side of the substrate does not need to be protected by a field oxide layer and subsequent operations are required on the back side of the substrate, the field oxide layer on the back side of the substrate is completely removed.

[0070] S240, Perform pre-diffusion treatment and bonding of the first preset material on the back side of the substrate 10.

[0071] S250, a plurality of arrayed holes 30 are etched on the back side of the substrate 10 toward the interior of the substrate 10; wherein the depth of the holes 30 is less than the push-in depth.

[0072] S260. The second preset material is used to fill each hole 30 to obtain a substrate structure with filled holes on the back side, which replaces the epitaxial wafer.

[0073] Optionally, based on the above embodiments, step S230 specifically includes:

[0074] S2301. A layer of photoresist is coated on the surface of the field oxide layer 20 on the front side of the substrate 10 to form a protective layer.

[0075] Specifically, the field oxide layer on the front side of the substrate needs to be retained to protect the front surface of the substrate and prevent device leakage. Therefore, a layer of photoresist is applied to the surface of the field oxide layer on the front side of the substrate to form a protective layer, so as to protect the field oxide layer on the front side of the substrate from being contaminated and damaged in subsequent process flows.

[0076] S2302, Use hydrofluoric acid to completely etch the field oxide layer 20 on the back side of the substrate 10.

[0077] Specifically, the back side of the substrate is immersed in hydrofluoric acid of a certain concentration to etch the field oxide layer on the back side, thereby completely removing the field oxide layer formed on the back side. The front side of the substrate has a protective layer, so the field oxide layer on the front side is retained and will not be corroded by hydrofluoric acid. After immersion for a period of time, the substrate is removed. The substrate is then rinsed multiple times with room temperature deionized water to remove any residual hydrofluoric acid from the substrate surface, and then spun dry or blown dry with a nitrogen gun to remove any remaining deionized water, ready for subsequent operations.

[0078] This embodiment further defines the method for forming a field oxide layer on the front side of a substrate. By utilizing hydrogen-oxygen synthesis, field oxide layers are prepared on both the front and back sides of the substrate, and then the back side field oxide layer is removed. Compared to coating a photoresist layer on the back side of the substrate, the method provided in this embodiment ensures a higher level of cleanliness in the field oxide layer preparation environment, preventing the generation of other contaminants. Therefore, the method in this embodiment results in a field oxide layer with higher purity and a cleaner surface.

[0079] Optionally, based on the above embodiments, see below. Figure 4 The structural schematic diagram corresponding to step S240, during the pre-diffusion treatment and bonding of the first preset material on the back side of the substrate, also includes:

[0080] A passivation layer 40 is formed on the back side of the substrate 10.

[0081] Specifically, the substrate is placed in a specific gaseous atmosphere during pre-diffusion and bonding in the diffusion furnace. For example, in this embodiment, hydrogen and oxygen are introduced into the silicon carbide furnace tube before pre-diffusion and bonding. Placing the substrate in this hydrogen-oxygen atmosphere and performing pre-diffusion and bonding at high temperature simultaneously forms a passivation layer of a certain thickness on the back side of the substrate. For example, in this embodiment, the substrate is a silicon wafer; therefore, the passivation layer formed on the back side of the substrate during pre-diffusion and bonding is a silicon dioxide layer.

[0082] There are various methods for etching multiple holes on the back side of a substrate, including laser etching and photolithography. The following embodiments will explain these two etching methods respectively.

[0083] This embodiment specifically describes the method of forming hole grooves using laser etching. Optionally, based on the above embodiments, please continue to refer to... Figure 4 Multiple arrayed holes are etched on the back side of the substrate in the direction of inward etching. Specifically, this may include:

[0084] A femtosecond laser is used to etch the back side of the substrate 10 on the passivation layer 40 to obtain multiple holes 30 in sequence.

[0085] Specifically, this embodiment describes a method for forming apertures using laser etching. A high-energy laser is used for etching; for example, a femtosecond laser is selected in this embodiment. Femtosecond lasers represent the shortest pulse technology achievable under laboratory conditions, and the instantaneous power emitted by a femtosecond laser exceeds the total power output of the world's electricity. Due to the extremely high peak power of femtosecond lasers, after focusing, the intensity of the femtosecond laser far exceeds the Coulomb field originating from internal interactions. Therefore, femtosecond lasers can easily detach electrons from the bonds of atoms, forming plasma.

[0086] The principle of femtosecond laser etching is as follows: a high-energy femtosecond laser beam is used to irradiate the surface of the material, causing the irradiated part of the material to vaporize, thereby achieving cutting or peeling of the material. When using femtosecond lasers to etch the back side of a substrate through a passivation layer, the femtosecond laser can make the etched edges smooth, avoiding substrate damage.

[0087] For example, the etching rate of the femtosecond laser is 3000–3500 mm / s, and the etching pitch is 0.01–0.03 mm. The etching rate and etching pitch can be adjusted by the user according to actual process requirements and are not limited here. The etching pitch is the distance between the laser pulses emitted by two adjacent laser pulses irradiating the passivation layer surface, and the etching rate is the length etched by the laser per unit time. Preferably, the laser etching rate is 3000 mm / s, and the laser etching pitch is 0.015 mm. If the laser etching pitch is too small, the etching process has higher precision but lower etching efficiency; if the laser etching pitch is large, the etching efficiency can be improved, but the etching precision will decrease, and the etching edge will be rougher. Therefore, the laser etching rate and etching pitch can be set to appropriate parameter values ​​according to the actual process requirements.

[0088] For example, the power of the femtosecond laser used for laser etching can be set to 6.1–6.2 W. Preferably, a power of 6.18 W is selected for the femtosecond laser to achieve a better etching effect. If the laser power is too low, the etching depth of the hole may be insufficient; if the laser power is too high, the laser etching area at the edge of the hole may increase, resulting in lower etching accuracy.

[0089] The technical solution of this embodiment uses a femtosecond laser to etch holes on the back side of a substrate, which can produce holes with smooth edges and does not cause substrate damage during the etching process.

[0090] This embodiment specifically describes the method of forming vias using photolithography etching. Optionally, Figure 5 This is a schematic diagram illustrating the specific structure of step S140 in a semiconductor device fabrication method provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 5 Multiple arrayed holes are etched on the back side of the substrate inwards, specifically including:

[0091] S141. Photoresist is coated on the surface of passivation layer 40 to form photoresist layer 41.

[0092] Specifically, a photoresist layer is coated on the surface of the passivation layer formed on the back side of the substrate to form a mask layer.

[0093] S142. The photoresist layer 41 is exposed by exposure, development and dry etching to expose part of the substrate 10 area corresponding to the passivation layer 40.

[0094] Specifically, by exposing and developing specific areas of the photoresist layer, the etched areas for etching the passivation layer are exposed. Dry etching is then applied to the corresponding etched areas to remove the passivation layer, exposing the substrate area beneath the passivation layer, which serves as a marker for the location of the etched vias on the back side of the substrate.

[0095] S143. Using a deep trench etching machine, etch trenches 30 are obtained in the exposed areas of each substrate 10.

[0096] Specifically, a deep trench etching machine is used to sequentially etch at the marked locations determined by photolithography to obtain trenches of a certain depth. After etching, the photoresist on the back side of the substrate is removed, resulting in a substrate with multiple trenches of a certain depth arranged in an array on the back side.

[0097] The technical solution of this embodiment uses traditional photolithography to expose and etch the passivation layer on the back side of the substrate to determine the position of the etched trenches, and then uses a deep trench etching machine to etch, which can improve the accuracy of the trench etching.

[0098] Optionally, based on the above embodiments, see below. Figure 2 The structural schematic diagram corresponding to step S140 shows that the longitudinal cross-sectional shape of the slot 30 is a trapezoid with an angle of 80 to 88°; the push-bonding depth is 180±5μm, the depth of the slot 30 is 165±5μm, and the spacing between two adjacent slots 30 is 20 to 25μm.

[0099] For example, the hole grooves etched using laser etching or photolithography have different bottom and opening dimensions, and the longitudinal cross-sectional shape of the hole groove is a trapezoid, meaning the bottom dimension is larger than the opening dimension. For instance, the trapezoidal angle of the longitudinal cross-sectional shape of the hole groove is 80–88°, and hole grooves within this angle range are more convenient for material filling.

[0100] For example, the depth of the via can be 165±5 μm, and the junction depth formed during pre-diffusion treatment and push-junction on the back side of the substrate is 180±5 μm. Therefore, the depth of the via must be less than the junction depth to form a satisfactory carrier concentration gradient on the back side of the substrate. The depth of the via and the junction depth formed by push-junction can be determined by the user based on the substrate thickness and actual device fabrication requirements, and are not limited here.

[0101] For example, in the array of multiple vias formed on the back side of the substrate, the spacing between two adjacent vias is 20–25 μm, and the specific spacing is not limited here. If the via spacing is too small, the silicon layer between two vias will be too thin, making the silicon layer prone to breakage during subsequent filling processes. If the via spacing is too large, the number of vias formed in a given area of ​​substrate will be reduced, which may result in the fabricated substrate structure failing to achieve the required carrier concentration gradient.

[0102] The following embodiments illustrate a method for filling holes and grooves with material. Optionally, in one embodiment... Figure 6 This is a schematic flowchart of another semiconductor device fabrication method provided in an embodiment of the present invention. Figure 7This is a schematic diagram of various structures in another semiconductor device fabrication method provided by an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 6 and Figure 7 The method for fabricating this semiconductor device includes:

[0103] S710 provides a substrate 10.

[0104] S720, a field oxide layer 20 is formed on the front side of the substrate 10.

[0105] S730, Perform pre-diffusion treatment and bonding of the first preset material on the back side of the substrate 10.

[0106] S740, A plurality of arrayed holes 30 are etched on the back side of the substrate 10 toward the interior of the substrate 10; wherein the depth of the holes 30 is less than the push-in depth.

[0107] S750: The second preset material is evaporated using low-pressure chemical vapor deposition and deposited into the cavity 30.

[0108] For example, a second predetermined material is evaporated into a gas using low-pressure chemical vapor deposition (LPCVD). The gas is then deposited into the interior of each cavity to form a second predetermined material film, thus filling all the cavities. Using LCVD, a second predetermined material film with high purity can be obtained. For example, the second predetermined material includes phosphorus-doped polycrystalline silicon. Filling the cavities on the back side of the substrate with phosphorus-doped polycrystalline silicon can form a substrate structure with a certain carrier concentration gradient, thereby replacing epitaxial processes to obtain a substrate with a carrier concentration gradient.

[0109] S760: The passivation layer on the back side of the substrate is removed using a chemical mechanical polishing process to obtain the substrate structure.

[0110] Specifically, Chemical Mechanical Polishing (CMP) is a technique for obtaining a material surface that is both flat and free of scratches and contaminants. CMP is applied to polish the back side of a substrate, creating a smooth and flat back side. During the polishing process, the passivation layer on the back side of the substrate is completely removed, exposing the back side. Furthermore, the surface of the second pre-designed material filling each of the vias is flush with the back side of the substrate, resulting in a substrate structure that can replace an epitaxial wafer.

[0111] Another alternative embodiment, Figure 8 This is a schematic diagram of various structures in another semiconductor device fabrication method provided by an embodiment of the present invention. Based on the above embodiments, this semiconductor device fabrication method includes six steps, S810 to S860. Among them, except for step S850, the remaining steps are the same as steps S710 to S760.

[0112] The difference between step S850 in this embodiment and step S750 in the above embodiment is that, in step S850, see... Figure 8 The second preset material is evaporated using low-pressure chemical vapor deposition and deposited into the cavity until the surface of the second preset material film is flush with the back side of the substrate. Since the passivation layer on the back side of the substrate needs to be completely removed in step S860, the portion of the second preset material in the same layer as the passivation layer is also removed. Therefore, the portion in the same layer as the passivation layer can be omitted when depositing the second preset material, thereby saving some material and reducing costs.

[0113] In this embodiment, a second preset material is evaporated using low-pressure chemical vapor deposition and deposited into each cavity to fill the cavity, resulting in a high-purity second preset material film. Then, the excess passivation layer on the back side of the substrate is removed using chemical mechanical polishing, resulting in a substrate structure with deep grooves on the back side filled with the preset material. This structure exhibits a certain carrier concentration gradient from the front to the back side of the substrate, thus replacing the epitaxial wafer.

[0114] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method of fabricating a semiconductor device, characterized by, The application relates to a substrate manufacturing method. Providing a substrate; Forming a field oxide layer on the front surface of the substrate; Performing pre-diffusion treatment and push junction of a first preset material on the back surface of the substrate to form a certain junction depth, so as to form a heavily doped region with a certain carrier concentration gradient on the back surface of the substrate; Etching a plurality of array-arranged hole grooves in the direction of the interior of the substrate on the back surface of the substrate; wherein the depth of the hole grooves is less than the push junction depth; Filling each hole groove with a second preset material to obtain a substrate structure with a back surface provided with filled hole grooves, so as to replace an epitaxial wafer; The method comprises the following steps: Preparation of the field oxide layer on the front and back surfaces of the substrate by means of hydrogen-oxygen synthesis; Removal of the field oxide layer on the back surface of the substrate.

2. The method of fabricating a semiconductor device according to claim 1, wherein The method comprises the following steps: Coating a layer of photoresist on the surface of the field oxide layer on the front surface of the substrate to form a protective layer; Complete etching of the field oxide layer on the back surface of the substrate by means of hydrofluoric acid.

3. The method of fabricating a semiconductor device according to claim 1, wherein The thickness of the field oxide layer on the front surface of the substrate is 10000-13000 angstroms.

4. The method of fabricating a semiconductor device according to claim 1, wherein The method comprises the following steps: Pre-diffusion treatment and push junction of the first preset material by means of a diffusion furnace with a silicon carbide furnace tube.

5. The method of fabricating a semiconductor device according to claim 4, wherein The method further comprises the following steps: Formation of a passivation layer on the back surface of the substrate.

6. The method of fabricating a semiconductor device according to claim 5, wherein The method comprises the following steps: Etching of the back surface of the substrate by means of femtosecond laser on the passivation layer to obtain a plurality of hole grooves in sequence.

7. The method of fabricating a semiconductor device according to claim 6, wherein The etching speed of the femtosecond laser is 3000-3500 mm / s, and the etching interval is 0.01-0.03 mm.

8. The method of fabricating a semiconductor device according to claim 5, wherein The method comprises the following steps: Coating photoresist on the surface of the passivation layer to form a photoresist layer; Exposure, development and dry etching of the photoresist layer to expose the substrate regions corresponding to the passivation layer; Etching of the exposed substrate regions by means of a deep groove etching machine to obtain the hole grooves.

9. The method of fabricating a semiconductor device according to claim 6 or 8, wherein The longitudinal section shape of the hole grooves is a right trapezoid, and the right trapezoid angle is 80-88 degrees. The push junction depth is 180+ / -5 mu m, the depth of the hole grooves is 165+ / -5 mu m, and the interval between two adjacent hole grooves is 20-25 mu m.

10. The method of fabricating a semiconductor device of claim 1, wherein, The method comprises the following steps: Evaporation of the second preset material by means of low-pressure chemical vapor deposition to deposit the second preset material into the hole grooves.

11. The method of fabricating a semiconductor device according to claim 1, wherein The first preset material comprises chlorinated phosphorus oxychloride, and the second preset material comprises phosphorus-doped polysilicon.

12. The method of fabricating a semiconductor device according to claim 6 or 8, wherein The method comprises the following steps: Removal of the passivation layer on the back surface of the substrate by means of a chemical mechanical polishing process to obtain the substrate structure.

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