A circuit module for improving boost voltage efficiency

Abstract

The present invention relates to the field of circuit technology, and in particular to a circuit module for improving boost voltage efficiency, comprising an initialization tube P3, which is used to make the VBoost point voltage be a power supply voltage in an initial state, a load capacitor C1 and a capacitor tube as the VBoost point capacitor, one end of the load capacitor C1 is grounded, and also comprises a delay module and a switch circuit connected to the VBoost point, wherein the capacitor tube comprises a capacitor tube P1 and a capacitor tube P2, the switch circuit is arranged between the VBoost point and the initialization tube P3, and is used to transmit voltage, the gate of the capacitor tube P1 and the drain of the initialization tube P3 are connected to the VF point, the gate of the capacitor tube P2 is connected to the VBoost point, and the delay module is connected between the capacitor tube P1 and the capacitor tube P2. The present invention realizes the improvement of boost efficiency with a small amount of switch circuits without adding additional boost capacitors, and the boost voltage is higher.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a circuit module for improving boost voltage efficiency. Background Art

[0002] In low-voltage applications, the power supply voltage is too low to turn on the NMOS well (current flows through the NMOS when the voltage is low, and the voltage drop of the NMOS tube increases), so a separate boost circuit is used to temporarily increase the voltage to help the NMOS turn on. This is a circuit that provides high voltage for a short period of time to help turn on. Common solutions include Figure 1 , P0's PMOS tube (NMOS tube can also be used) is used as a boost capacitor, C1 is a load capacitor, and P3 is a PMOS tube, which plays the role of giving the initial voltage to the VBOOST point. Before starting the boost (that is, the moment when IN changes from low to high), the waveform is as follows Figure 3 As shown in the figure, the voltage at the VBOOST point is the power supply voltage. When the IN signal changes from low to high, the VBOOST point will start to increase from VDD (power supply voltage). At this time, the voltage of IN2 will change from low to high (turning off the P3 tube), disconnecting the path between VBOOST and the power supply VDD. When IN2 is high, it is the voltage of VBOOST, ensuring that the PMOS tube P3 is turned off.

[0003] When the value of the load capacitor C1 is relatively large, if you want to increase the boost voltage, the boost capacitor must be very large to achieve the boost effect. Therefore, the size of the boost capacitor P0 tube is often large. If the boost efficiency can be improved, this part of the capacitor area can be greatly saved.

[0004] In order to solve the above problems, the present application proposes a circuit module for improving boost voltage efficiency. Summary of the invention

[0005] (I) Purpose of the invention

[0006] In order to solve the technical problems existing in the background technology, the present invention proposes a circuit module for improving boost voltage efficiency. Without adding additional boost capacitors, the boost efficiency is improved with a small number of switching circuits, and the boost voltage is higher.

[0007] (II) Technical solution

[0008] To solve the above technical problems, the present invention provides a circuit module for improving boost voltage efficiency, including an initialization tube P3, which is used to make the VBoost point voltage the power supply voltage in the initial state, a load capacitor C1 and a capacitor tube serving as the VBoost point capacitor, one end of the load capacitor C1 is grounded, and also includes a delay module and a switching circuit connected to the VBoost point, the capacitor tube includes a capacitor tube P1 and a capacitor tube P2, the switching circuit is arranged between the VBoost point and the initialization tube P3, and is used to transmit voltage, the gate of the capacitor tube P1 and the drain of the initialization tube P3 are connected to the VF point, the gate of the capacitor tube P2 is connected to the VBoost point, and the delay module is connected between the capacitor tube P1 and the capacitor tube P2.

[0009] Preferably, the switch circuit comprises a PMOS transistor P4, a drain of the PMOS transistor P4 is connected to the node VF, and a source of the PMOS transistor P4 is connected to the VBoost point.

[0010] Preferably, the switching circuit further includes a PMOS tube P5 and a PMOS tube P6, the gate of the PMOS tube P5 is connected to the drain of the PMOS tube P4, the gate of the PMOS tube P6 is connected to the source of the PMOS tube P4, the drain of the PMOS tube P5 is connected to the VBoost point, the drain of the POMS tube P6 is connected to the VF point, and the substrates of the POMS tube P4, the substrates of the POMS tube P5 and the substrates of the POMS tube P6 are mutually connected to the sources of the POMS tube P6 and the POMS tube P5.

[0011] Preferably, the capacitor tube P1 and the capacitor tube P2 are both PMOS tubes, and the capacitor tube P1 and the capacitor tube P2 are both connected to the input and output ends of the delay module respectively by short-circuiting the source and the drain as signal input.

[0012] The above technical solution of the present invention has the following beneficial technical effects: the present invention achieves the improvement of boost efficiency with a small number of switching circuits without adding additional boost capacitors, and the boost voltage is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the circuit structure of the prior art;

[0014] Figure 2 It is a circuit structure diagram of the present invention;

[0015] Figure 3 for Figure 1 Waveform graph;

[0016] Figure 4 for Figure 2 Waveform graph. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0018] A circuit module for improving boost voltage efficiency provided by the present invention includes an initialization tube P3, which is used to make the VBoost point voltage be the power supply voltage in the initial state, a load capacitor C1 and a capacitor tube as the VBoost point capacitor, one end of the load capacitor C1 is grounded, and also includes a delay module and a switch circuit connected to the VBoost point, the capacitor tube includes a capacitor tube P1 and a capacitor tube P2, the switch circuit is arranged between the VBoost point and the initialization tube P3, and is used to transmit voltage, and is used to transmit voltage, the gate of the capacitor tube P1 and the drain of the initialization tube P3 are connected to the VF point, the gate of the capacitor tube P2 is connected to the VBoost point, and the delay module is connected between the capacitor tube P1 and the capacitor tube P2. The switch circuit includes a PMOS tube P4, the drain of the PMOS tube P4 is connected to the node VF, and the source is connected to the VBoost point. The switch circuit also includes a PMOS tube P5 and a PMOS tube P6. The gate of the PMOS tube P5 is connected to the drain of the PMOS tube P4, the gate of the PMOS tube P6 is connected to the source of the PMOS tube P4, the drain of the PMOS tube P5 is connected to the VBoost point, the drain of the PMOS tube P6 is connected to the VF point, and the substrates of the POMS tube P4, the substrates of the POMS tube P5 and the substrates of the POMS tube P6 are mutually connected to the sources of the POMS tube P6 and the POMS tube P5.

[0019] In the present invention, the gate of MOS transistor P3 is connected to input signal IN2, the drain of MOS transistor P1 as capacitor is connected to input signal IN, the drain of MOS transistor P2 as capacitor is connected to input signal IND, and the gate of switch transistor, namely PMOS transistor P4, is connected to input signal IN3.

[0020] It should be noted that in the present invention, all MOS tubes in the circuit diagram are PMOS, wherein P0, P1, and P2 are connection methods for using MOS tubes as capacitors, and their functions are equivalent to capacitors.

[0021] To facilitate understanding of the present invention, the following description is made with respect to the prior art:

[0022] according to Figure 1 , Figure 3 .

[0023] PMOS tube P0 is used as boost capacitor, capacitor C1 is load capacitor, and PMOS tube P3 plays the role of giving initial voltage to VBOOST point. Before starting boost (i.e. the moment when IN changes from low to high), the waveform is as follows Figure 3 As shown in the figure, the voltage at the VBOOST point is the power supply voltage. When the IN signal changes from low to high, the VBOOST point will start to increase from VDD (power supply voltage). At this time, the voltage of IN2 will change from low to high (turning off the PMOS tube P3), disconnecting the path between VBOOST and the power supply VDD. When IN2 is high, it is the voltage of VBOOST, ensuring that the PMOS tube P3 is turned off.

[0024] According to the formula (ΔU in )*C in =(ΔU out )*C out .

[0025] correspond Figure 1 The circuit is VDD*C p0 =ΔU out *(C p0 +C1);

[0026] ΔU out =(VDD*C p0 ) / (C p0 +C1);

[0027] Among them, Cp0 is the MOS capacitance of PMOS tube P0, then:

[0028] VBOOST=VDD+(VDD*C p0 ) / (C p0 +C1)=VDD*(1+C p0 / (C p0 +C1)).

[0029] From the formula, we can see that when the value of load capacitor C1 is relatively large, if we want to increase the boost voltage, the boost capacitor must be very large to achieve the boost effect. Therefore, the size of the boost capacitor P0 tube is often large. If the boost efficiency can be improved, this part of the capacitor area can be greatly saved.

[0030] This patent improves the efficiency of boost by using fewer tubes, thereby achieving the purpose of saving area.

[0031] refer to Figure 2 , Figure 4 .

[0032] The present invention will Figure 1 The capacitor P0 is divided into two parts. Figure 2The sum of the areas of the capacitors P1 and P2 is equal to Figure 1 The area of ​​the capacitor P0 is large, and the PMOS tube P3 is used as the tube for initialization to ensure that the voltage at the VBOOST point is VDD in the initial state. The PMOS tube P4 is used as a switch tube for transmitting voltage. The PMOS tube P5 and the PMOS tube P6 are used as substrate selection circuits to dynamically select the voltage of the drain and source of the PMOS tube P4. The voltage on the side with a higher voltage will be transmitted to the substrate of P4 to ensure that the substrate end of the PMOS tube P4 must be the highest voltage. If the source voltage of the PMOS tube P4 is high, then the PMOS tube P6 will be turned off, and the high voltage of the source of the PMOS tube P4 will be transmitted to the substrate of the PMOS tube P4 through the PMOS tube P5; if the drain voltage of the PMOS tube P4 is high, then the PMOS tube P5 will be turned off, and the high voltage of the drain of the PMOS tube P4 will be transmitted to the substrate end of the PMOS tube P4 through the PMOS tube P6.

[0033] The entire boost process is divided into two stages (waveform as Figure 4 As shown in the figure, before the first stage starts, that is, in the initial state, because the input signal IN2 is GND, the PMOS tube P3 is turned on and the voltage at the VF point is VDD; because the input signal IN3 is GND at this time, the PMOS tube P4 is also turned on, so the voltage at the VBOOST point is also VDD.

[0034] In the first stage, the input signal IN2 changes from GND to the voltage of VBOOST, so the PMOS tube P3 is turned off. The input signal IN changes from low to high (from GND to VDD), and the voltage of the VF point increases by ΔU on the basis of VDD through the coupling effect of the PMOS tube P1. out1 ; PMOS tube P4 is in the on state (because IN3 is GND at this time), so the voltage at VBOOST is equal to the voltage at VF, that is, VDD+ΔU out1 ;

[0035] In the second stage, the input IN3 becomes high (the voltage changes from GND to VBOOST voltage) to turn off the P4 tube; the IND signal becomes high (the voltage changes from GND to VDD voltage), and through the coupling effect of the P2 capacitor tube, the VBOOST point is based on the previously increased voltage (VDD + ΔU out1 ) further increases (VDD+ΔU out1 +ΔU out2 )

[0036] According to the formula:

[0037] VDD*C p1 =ΔU out1 *(C p1 +C p2+C1),ΔU out1 =(VDD*C p1 ) / (C p1 +C p2 +C1);

[0038] VDD*C p2 =ΔU out2 *(C p2 +C1), ΔU out2 =(VDD*C p2 ) / (C p2 +C1);

[0039] VBOOST=VDD+ΔU out1 +ΔU out2

[0040] =VDD+VDD*[C p1 / (C p1 +C p2 +C1)+C p1 / (C p1 +C1)]Formula 1

[0041] Where: C p1 is the MOS capacitor of PMOS tube P1, C p2 It is the MOS capacitor of PMOS tube P2. Figure 2 C p1 +C p2 equal Figure 1 C p0

[0042] and, Figure 1 middle:

[0043] VBOOST=VDD+VDD*Cp0 / (Cp0+C1)=VDD+VDD*[(Cp1+Cp2) / (Cp1+Cp2+C1)]

[0044] =VDD+VDD*[Cp1 / (Cp1+Cp2+C1)+Cp2 / (+Cp2+C1)]Formula 2

[0045] By comparing Formula 1 and Formula 2, it can be found that when the areas of the capacitor tubes are equal, Cp0=Cp1+Cp2 (this example is designed as Cp1=Cp2), the voltage value of VBOOST calculated by Formula 1 must be greater than Formula 2. That is, in the case of equal area (the area of ​​the capacitor tube is much larger than the area of ​​other switch tubes, so the capacitor tube is the main area factor), the Boost design of the present invention is more efficient than the traditional solution. Its essential principle is to divide the boost process into two boost stages. In the second stage, Cp1 is disconnected from the output, which is equivalent to the load capacitance of the 2nd stage becoming smaller, so the overall boost efficiency is improved. In theory, the same principle can be used to divide the circuit into 3 or even 4 stages of boost, but the benefits are gradually reduced, so the efficiency improvement is not obvious compared to the 2-stage boost.

[0046] According to the above description, the present invention divides the boost capacitor into two parts by adding a small amount of switching circuits and delay modules. The boost process is also divided into two stages. The first stage is similar to the traditional solution. In the second stage, half of the boost capacitor is disconnected from the output node, which is equivalent to reducing the load capacitance, so the boost efficiency is improved.

[0047] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A circuit module for improving boost voltage efficiency, comprising an initialization tube P3, which is used to make the VBoost point voltage equal to the power supply voltage in the initial state, a load capacitor C1 and a capacitor tube as the VBoost point capacitor, wherein one end of the load capacitor C1 is grounded, and is characterized in that: It also includes a delay module and a switching circuit connected to the VBoost point. The capacitor tube includes a capacitor tube P1 and a capacitor tube P2. The switching circuit is arranged between the VBoost point and the initialization tube P3 for transmitting voltage. The gate of the capacitor tube P1 and the drain of the initialization tube P3 are connected to the VF point, the gate of the capacitor tube P2 is connected to the VBoost point, and the delay module is connected between the capacitor tube P1 and the capacitor tube P2.

2. A circuit module for improving boost voltage efficiency according to claim 1, characterized in that: The switch circuit includes a PMOS transistor P4, a drain of the PMOS transistor P4 is connected to the node VF, and a source of the PMOS transistor P4 is connected to the VBoost point.

3. A circuit module for improving boost voltage efficiency according to claim 2, characterized in that: The switch circuit also includes a PMOS tube P5 and a PMOS tube P6. The gate of the PMOS tube P5 is connected to the drain of the PMOS tube P4, the gate of the PMOS tube P6 is connected to the source of the PMOS tube P4, the drain of the PMOS tube P5 is connected to the VBoost point, the drain of the PMOS tube P6 is connected to the VF point, and the substrates of the POMS tube P4, the substrates of the POMS tube P5 and the substrates of the POMS tube P6 are mutually connected to the sources of the POMS tube P6 and the POMS tube P5.

4. A circuit module for improving boost voltage efficiency according to claim 1, characterized in that: The capacitor tube P1 and the capacitor tube P2 are both PMOS tubes, and the capacitor tube P1 and the capacitor tube P2 are both connected to the input and output ends of the delay module respectively by short-circuiting the source and the drain as signal input.

Images