Control method, device, chip and electronic equipment

Abstract

The present application discloses a control method for controlling a resampling circuit, which includes a pre-circuit, a FIFO, and a variable sampling rate conversion circuit. The method includes obtaining a ratio coefficient of the FIFO depth occupied by data stored in the FIFO after being processed by the pre-circuit, and controlling whether the FIFO is written with the data processed by the pre-circuit based on the ratio coefficient. The data written in the FIFO after being processed by the pre-circuit is read by the variable sampling rate conversion circuit for resampling. The present application also provides a control device, a chip, and an electronic device.

Description

Technical Field

[0001] The present application relates to compensation technology for center frequency offset (CFO) and sampling frequency offset (SFO) in an orthogonal frequency division multiplexing (OFDM) communication system, and in particular to a control method, device, chip and electronic device. Background Art

[0002] In wireless communication systems, the transmitter and receiver use their own crystal oscillators as reference clocks. However, due to the influence of accuracy, temperature drift, and aging, the crystal oscillator always has a certain frequency error. Therefore, the transmitter and receiver cannot achieve true frequency synchronization, resulting in CFO and SFO.

[0003] In OFDM communication systems, both CFO and SFO can destroy subcarrier orthogonality, degrading system reception performance. Therefore, communication systems typically adjust the voltage-controlled oscillator (VCO) to minimize CFO and SFO, or use digital compensation to correct them.

[0004] For wireless LANs using the 802.11 protocol, cost factors often lead to direct digital compensation techniques for correcting the CFO and SFO in the receiver path. Specifically, in the receiver's SFO module, the receiver first estimates the CFO from the packet header of the received signal. Assuming the peer RF and baseband reference clocks are from the same source, the SFO can also be inferred from the CFO. After estimating the SFO, the receiver simply needs to continuously resample the received time domain signal. This is most commonly achieved by using a variable sampling rate converter (VSRC), typically employing a Farrow structure for signal resampling.

[0005] The newly released 802.11ax and 802.11be protocols introduce the Orthogonal Frequency Division Multiple Access (OFDMA) mechanism, which requires that the center frequency and sampling rate of the resource units (RUs) sent by all mobile stations (STAs) be aligned when they arrive at the wireless access point (AP). The AP receiver does not perform CFO and SFO compensation.

[0006] However, conventional methods use a first-in-first-out (FIFO) buffer to overcome the speed difference caused by VSRC. For example, when the AP clock is faster, the FIFO needs to be full before it starts sending data to the subsequent VSRC. When the AP clock is slower, an empty FIFO is needed to carry data that cannot be consumed temporarily.

[0007] With 802.11be supporting a maximum signal bandwidth of 320MHz, VSRC needs to operate at higher frequencies, such as 1280MHz, requiring a larger FIFO depth. Furthermore, communication systems often adjust their clock frequency to mitigate the effects of higher-order clock harmonics. Once this method is adopted, the required VSRC adjustment ratio is no longer expressed in ppm, but in percentage (%). In this scenario, assuming a 1% clock adjustment, the FIFO size needs to be larger.

[0008] It can be seen that the conventional method requires a larger FIFO, which occupies a larger area. The digital delay line in the larger FIFO is refreshed at every beat, resulting in high power consumption, which is not conducive to battery-powered terminals such as mobile phones. The larger FIFO also causes additional delays. It can be seen that in the existing communication system, the transmitter has large delays and power consumption when performing resampling. Summary of the Invention

[0009] Embodiments of the present application provide a control method, device, chip, and electronic device that can improve the delay and power consumption during transmitter resampling in a communication system.

[0010] The technical solution of this application is achieved as follows:

[0011] An embodiment of the present application provides a control method for controlling a resampling circuit, wherein the resampling circuit includes: a preamplifier circuit, a FIFO, and a variable sampling rate conversion circuit, including:

[0012] Obtaining a ratio coefficient of the depth of the FIFO occupied by the data stored in the FIFO and processed by the front-end circuit;

[0013] According to the proportional coefficient, whether the FIFO writes the data processed by the front-end circuit is controlled; wherein the data written into the FIFO after being processed by the front-end circuit is used for resampling after being read by the variable sampling rate conversion circuit.

[0014] An embodiment of the present application provides a control device for controlling a resampling circuit, wherein the resampling circuit includes: a preamplifier circuit, a FIFO, and a variable sampling rate conversion circuit, including:

[0015] an acquisition module, configured to acquire a ratio coefficient of the depth of the FIFO occupied by the data stored in the FIFO and processed by the front-end circuit;

[0016] A control module is used to control whether the FIFO writes the data processed by the front-end circuit according to the proportional coefficient; wherein the data written into the FIFO after the front-end circuit is used for the variable sampling rate conversion circuit to read and then resample.

[0017] An embodiment of the present application provides a control device, comprising: a processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations via a communication bus, and when the instructions are executed by the processor, the control method described in one or more of the above embodiments is executed.

[0018] An embodiment of the present application provides a chip, comprising a resampling circuit and the control device described in one or more of the above embodiments; wherein the resampling circuit comprises: a front-end circuit, a FIFO and a variable sampling rate conversion circuit.

[0019] An embodiment of the present application provides a chip, including: a processor, configured to call and run a computer program from a memory, so that a device equipped with the chip executes the control method described in one or more of the above embodiments.

[0020] An embodiment of the present application provides an electronic device, comprising a chip as described in one or more of the above embodiments.

[0021] An embodiment of the present application provides a computer storage medium, wherein the computer-readable storage medium is used to store a computer program, and the computer program enables a computer to execute the steps of the control method described in one or more of the above embodiments.

[0022] Embodiments of the present application provide a control method, device, chip, and electronic device. The method is used to control a resampling circuit, which includes: a front-end circuit, a FIFO, and a variable sampling rate conversion circuit. The method includes: obtaining a proportional coefficient of the FIFO depth occupied by the data processed by the front-end circuit stored in the FIFO, and controlling whether the FIFO is written with the data processed by the front-end circuit according to the proportional coefficient, wherein the data processed by the front-end circuit written in the FIFO is used for resampling after being read by the variable sampling rate conversion circuit; that is, in the embodiment of the present application, through the control of the resampling circuit by the control device, it is possible to control whether the FIFO is written with the data processed by the front-end circuit according to the proportional coefficient of the FIFO depth occupied by the stored data in the FIFO. In this way, the proportional coefficient of the FIFO depth occupied by the data stored in the FIFO is controlled, so that resampling can be achieved using a FIFO with a smaller depth, and the use of a smaller FIFO reduces the delay and power consumption of the transmitter of the communication system during resampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart of an optional control method provided in an embodiment of the present application;

[0024] Figure 2 This is a comparison chart of the related art with and without resampling when u=0.25;

[0025] Figure 3 This is a comparison diagram of different sampling rates when u=0.25 in the related art;

[0026] Figure 4 Schematic diagram of the structure of a communication circuit in a transmitter in a communication system in the related art;

[0027] Figure 5 A schematic structural diagram of a communication circuit in a transmitter in an optional communication system provided in an embodiment of the present application;

[0028] Figure 6 An optional timing diagram of vaild provided in an embodiment of the present application;

[0029] Figure 7 A schematic structural diagram of an optional control device provided in an embodiment of the present application;

[0030] Figure 8 A schematic structural diagram of another optional control device provided in an embodiment of the present application;

[0031] Figure 9 A schematic diagram of the structure of an optional chip provided in an embodiment of the present application;

[0032] Figure 10A schematic structural diagram of another optional chip provided in an embodiment of the present application;

[0033] Figure 11 A schematic structural diagram of an optional electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0035] The embodiment of the present application provides a control method for controlling a resampling circuit, wherein the resampling circuit includes: a preamplifier circuit, a FIFO, and a variable sampling rate conversion circuit. Figure 1 A flow chart of an optional control method provided in an embodiment of the present application is shown as follows: Figure 1 As shown, the method may include:

[0036] S101: Obtaining a ratio coefficient of the FIFO depth occupied by the data stored in the FIFO and processed by the front-end circuit;

[0037] Currently, the 802.11ax and 802.be protocols introduce the OFMDA mechanism, which requires that the center frequency and sampling rate of all transmitted RUs be aligned. The receiver does not perform CFO and SFO compensation, so the transmitter must implement pre-compensation for the RU center frequency and sampling rate.

[0038] Based on the protocol's accuracy of ±350Hz, the required accuracy at 7GHz is ±0.05ppm. Assuming the SFO of the transmitted signal detected by the receiver is 0.25, the ratio of the transmitter and receiver sampling rates is 1.25. Figure 2 This is a comparison chart of the related art with and without resampling when u=0.25, as shown in Figure 2 As shown in the figure, the sampling points of the thin circles indicate that the transmitter needs 10 clock beats to send out a complete signal. Without SFO correction, the duration of this signal will be 1.25 times that expected by the receiver, resulting in the receiver being unable to receive it correctly. Therefore, the transmitter needs to compress the signal playback duration to 0.8 times without changing its own sampling rate, that is, to send the signal in only 8 clock beats. Figure 2 The sampling points of the circles with medium-thick lines.

[0039] Figure 3 This is a comparison diagram of different sampling rates when u=0.25 in the related art, such as Figure 3As shown in the figure, the sampling points with thick lines are the original waveform, which consists of 10 sampling points. Now we need to reduce the sampling points to 8. In the time domain, we can expand the sampling period (Ts) to 1.25 times of the original one, that is, resample in the time domain through a resampling filter with u = 0.25. After the resampling filter, only 8 sampling points are needed to fully describe the same waveform, that is Figure 3 The sampling points of the medium and thin lines are the sampling points after resampling.

[0040] from Figure 3 It can also be seen that for every 8 sampling points generated, the circuit needs to read in 10 data points, that is, the VSRC filter reduces the number of sampling points, and the data generation speed is lower than the consumption speed.

[0041] Figure 4 FIG. 1 is a schematic diagram of a communication circuit in a transmitter in a communication system in the related art. Figure 4 As shown, the communication circuit includes a gated clock (CLOCK), an inverse fast Fourier transform (IFFT) and a memory (MEM), a CFO, a spectrum shaping filter (Mask Filter), an up-sampling filter (Up-Sampling Filter), a FIFO / digital delay line (DelayLine) and a Farrow structure filter; wherein, the CLOCK is used to send a clock edge to other modules so that other modules process data according to the clock edge, the IFFT MEM is used to perform an inverse fast Fourier transform on the received data and store the inverse fast Fourier transformed data in the Memory, the CFO is used to perform CFO compensation on the received data, the Mask Filter filters the received data, the Up-Sampling Filter upsamples and filters, the FIFO / DelayLine is used to store data, and the Farrow structure filter is used to read data and perform SFO compensation and resampling on the read data.

[0042] exist Figure 4 In the example, the Farrow filter follows the Up-Sampling Filter to prevent the Error Vector Magnitude (EVM) from being damaged. In addition, to overcome the aforementioned speed difference, some data needs to be pre-stored in a FIFO.

[0043] Alternatively, the opposite scenario exists: the transmitter's reference clock is faster than the receiver's. In this case, for every 10 samples read, more than 10 samples of data are generated after VSRC. In this case, the sample generation rate is faster than the consumption rate. To ensure that the FIFO can accommodate data, a common approach is to use an initially empty FIFO to temporarily store unused data.

[0044] As mentioned above, a larger FIFO is required to participate in the resampling of the transmitter, and a larger FIFO will bring greater delay and power consumption. In order to reduce delay and power consumption, a control device is provided in an embodiment of the present application, which is used to control the resampling circuit, wherein the resampling circuit includes a front-end circuit, a FIFO and a variable sampling rate conversion circuit. The resampling circuit uses the front-end circuit to process data, the FIFO caches the processed data, and the variable sampling rate conversion circuit reads data from the FIFO and resamples it to send the resampled data to the receiver.

[0045] Among them, for the resampling circuit, after the front-end circuit processes the data and obtains the processed data, the processed data needs to be written into the FIFO. Here, a FIFO with a smaller capacity is selected. Then, in order to prevent the data loss problem caused by the data written into the FIFO exceeding the range of the data amount that the FIFO can accommodate, a control device is used here to obtain the proportional coefficient of the data stored in the FIFO processed by the front-end circuit to the FIFO depth, so as to know the proportional coefficient of the data stored in the FIFO to the FIFO depth, and then control the processed data written into the FIFO according to the proportional coefficient.

[0046] S102: Controlling whether the FIFO writes the data processed by the front-end circuit according to the proportional coefficient.

[0047] The data written into the FIFO and processed by the front-end circuit is read by the variable sampling rate conversion circuit and then resampled.

[0048] After obtaining the proportional coefficient, in order to prevent the data in the FIFO from exceeding the range of the data amount that the FIFO can accommodate, the control device can control whether the FIFO writes the data processed by the front-end circuit according to the proportional coefficient. For example, when the proportional coefficient indicates that the data in the FIFO exceeds the range of the data amount that the FIFO can accommodate, the FIFO is controlled to write the processed data; when the proportional coefficient indicates that the data in the FIFO does not exceed the range of the data amount that the FIFO can accommodate, the FIFO is controlled to prohibit writing the processed data.

[0049] In this way, resampling can be achieved by using a FIFO with a smaller depth, and the delay and power consumption of the transmitter of the communication system during resampling are reduced.

[0050] For resampling implemented by including CFO compensation and SFO compensation, the above-mentioned front-end circuit includes: a CFO compensation circuit.

[0051] Among them, the CFO compensation circuit is used to implement CFO compensation of the data, obtain the CFO compensated data, and write it into the FIFO. The variable sampling rate conversion circuit is used to read the CFO compensated data from the FIFO, perform SFO compensation on the CFO compensated data, and then realize resampling.

[0052] In order to control whether the FIFO writes the data processed by the front-end circuit, in an optional embodiment, S102 may include:

[0053] When the proportional coefficient is less than a preset threshold, the front-end circuit is controlled to write the processed data into the FIFO;

[0054] When the proportional coefficient is greater than a preset threshold, the front-end circuit is controlled to prohibit writing the processed data into the FIFO.

[0055] Through S101, after obtaining the ratio coefficient of the FIFO depth occupied by the data processed by the front-end circuit stored in the FIFO, the ratio coefficient is compared with a preset threshold, wherein the preset threshold is less than 1, for example, the preset threshold is half, one quarter, or three quarters of the FIFO depth; then, when the ratio coefficient is less than the preset threshold, the front-end circuit is controlled to write the data processed by the front-end circuit into the FIFO, and when the ratio coefficient is greater than the preset threshold, the front-end circuit is controlled to prohibit writing the data processed by the front-end circuit into the FIFO. In this way, the ratio coefficient of the FIFO depth occupied by the processed data stored in the FIFO is maintained at a number that fluctuates based on the preset threshold, so that a smaller FIFO can realize data processing and resampling.

[0056] In addition, the data processed by the front-end circuit written in the FIFO is used for resampling after being read by the variable sampling rate conversion circuit to send out the resampled data. That is to say, the variable sampling rate conversion circuit is used to read the data processed by the front-end circuit written from the FIFO, and resample the read data to obtain the resampled data, so as to send it out. In this way, it is ensured that the receiving end can accurately receive the data.

[0057] Here, through the control of the control device, the resampling circuit can use a smaller FIFO to achieve resampling of the processed data, thereby reducing the delay and power consumption of the transmitter in the communication system when performing resampling.

[0058] In addition, it should be noted that when the proportional coefficient is equal to the preset threshold, the front-end circuit can be controlled to write the data processed by the front-end circuit to the FIFO, or the front-end circuit can be controlled to prohibit writing the data processed by the front-end circuit to the FIFO. Here, the embodiment of the present application does not make specific limitations on this.

[0059] Furthermore, in order to control the front-end circuit to write the data processed by the front-end circuit into the FIFO, in an optional embodiment, S102 may include:

[0060] When the proportional coefficient is less than a preset threshold, generating a first control signal;

[0061] The first control signal is used to control the front-end circuit to write the data processed by the front-end circuit into the FIFO.

[0062] It can be understood that when the proportional coefficient is less than the preset threshold, the first control signal generated can be used to control the front-end circuit to write the data processed by the front-end circuit into the FIFO. In actual applications, when the proportional coefficient is less than the preset threshold, the first control signal is generated as a high level, and the high level is transmitted to the front-end circuit. The high level received by the front-end circuit writes the data processed by the front-end circuit into the FIFO.

[0063] Furthermore, in order to control the front-end circuit to prohibit writing the data processed by the front-end circuit into the FIFO, in an optional embodiment, S103 may include:

[0064] When the proportional coefficient is greater than a preset threshold, generating a second control signal;

[0065] The second control signal is used to control the front-end circuit to prohibit writing the data processed by the front-end circuit into the FIFO.

[0066] It can be understood that when the proportional coefficient is greater than the preset threshold, the second control signal can be generated to control the front-end circuit to prohibit the writing of data processed by the front-end circuit into the FIFO. In actual applications, when the proportional coefficient is greater than the preset threshold, the second control signal is generated as a low level, and the low level is transmitted to the front-end circuit. The low level received by the front-end circuit prohibits the writing of data processed by the front-end circuit into the FIFO.

[0067] Among them, the above-mentioned control device generates the first control signal or the second control signal which is related to the clock of the resampling circuit. For example, the first control signal or the second control signal can be generated at the rising edge of each clock according to the relationship between the proportional coefficient and the preset threshold, and the first control signal or the second control signal can be generated at the falling edge of each clock according to the relationship between the proportional coefficient and the preset threshold. Here, the embodiment of the present application does not make specific limitations on this.

[0068] In the above-mentioned control of whether the front-end circuit writes the data processed by the front-end circuit into the FIFO by the first control signal or the second control signal, the first control signal and the second control signal can be directly used to control whether the front-end circuit writes the data into the FIFO. The first control signal or the second control signal can also be used to control the gated clock, thereby controlling whether the front-end circuit writes the data into the FIFO by the gated clock. In an optional embodiment, the resampling circuit further includes: a gated clock, which uses the first control signal to control the front-end circuit to write the data processed by the front-end circuit into the FIFO, including:

[0069] The first control signal is used to control the gated clock to start, so that the front-end circuit writes the data processed by the front-end circuit into the FIFO.

[0070] It can be understood that the first control signal is transmitted to the gated clock, and the gated clock receives the first control signal and turns on the gated clock, so that the gated clock sends a clock signal to the preamplifier circuit, thereby causing the preamplifier circuit to write data to the FIFO.

[0071] Regarding the second control signal, in an optional embodiment, the resampling circuit further includes: a gating clock, which uses the second control signal to control the front-end circuit to prohibit writing data processed by the front-end circuit into the FIFO, including:

[0072] The second control signal is used to control the gated clock to be turned off, so that the front-end circuit is prohibited from writing data processed by the front-end circuit into the FIFO.

[0073] It can be understood that the second control signal is transmitted to the gated clock, and the gated clock receives the second control signal and turns off the gated clock, so that the front-end circuit cannot receive the clock signal, and thus the front-end circuit writes data to the FIFO.

[0074] In addition, since the above-mentioned control device can enable the front-end circuit to control the writing of data to the FIFO, the front-end circuit will write data to the FIFO at different speeds. In order to adapt to the situation of high-speed writing to the FIFO, in an optional embodiment, the front-end circuit uses a parallel method to write the data processed by the front-end circuit into the FIFO.

[0075] That is to say, the front-end circuit writes data into the FIFO in a parallel manner, thereby increasing the channels for the front-end circuit to write into the FIFO and improving the speed at which the front-end circuit writes data to adapt to the situation of high-speed writing into the FIFO.

[0076] Here, it should be noted that, in addition to the CFO compensation circuit, the above-mentioned pre-circuit may also include circuits with other functions, such as IFFT MEM, Mask Filter, upsampling filter, etc. Here, the embodiment of the present application does not make specific limitations on this.

[0077] The parallel approach here includes that each circuit in the pre-circuit before the FIFO processes data in a parallel manner, so as to meet the high-speed writing of the FIFO.

[0078] Furthermore, in order to adapt to the situation of high-speed writing into the FIFO, in an optional embodiment, the variable sampling rate conversion circuit reads the processed data from the FIFO in a parallel manner.

[0079] It is understandable that when the frequency deviation accuracy between the receiver and the transmitter is large, a fast reading situation will occur. In order to adapt to the fast reading situation, the variable sampling rate conversion circuit uses a parallel method to read data from the FIFO to meet the needs of fast reading.

[0080] The control method in one or more of the above embodiments is described below with examples.

[0081] Figure 5 A schematic diagram of the structure of a communication circuit in a transmitter in an optional communication system provided in an embodiment of the present application is shown as follows: Figure 5 As shown, Figure 4 In comparison, the VSRC front-end circuit (including IFFT MEM, CFO, Mask Filter, Up-Sampling Filter) is modified to a parallel mode, and the VSRC front-end circuit is controlled by the Valid signal (equivalent to the first control signal and the second control signal mentioned above). In this way, the FIFO can work in 2x speed mode to write data, 1x speed mode to write data, and 0x speed mode to write data; and the originally required large-capacity FIFO is replaced by a small-capacity FIFO.

[0082] In this example, a control device is added between FIFO and VSRC, which has the following functions:

[0083] Generate a vaild signal: implement a back-pressure mechanism. When the size of the data stored in the FIFO is less than a threshold (which can be set to 1 / 4, 1 / 2, or 3 / 4 of the data size that the FIFO can accommodate, etc., according to requirements), the control device sets vaild to 1 and reversely controls the VSRC front-end circuit to start outputting data to write data into the FIFO. When the size of the data stored in the FIFO is greater than or equal to the threshold, the control device sets vaild to 0 and reversely controls the VSRC front-end circuit to stop outputting data to prohibit writing data into the FIFO.

[0084] Here, it should be noted that the above-mentioned vaild signal can be directly transmitted to the VSRC front-end circuit to control whether it writes data to the FIFO, or the vaild signal can be transmitted to CLOCK, and by controlling the opening and closing of CLOCK, the VSRC front-end circuit is indirectly controlled to control whether it writes data to the FIFO; here, the embodiment of the present application does not make specific limitations on this.

[0085] Figure 6 An optional timing diagram of vaild provided in an embodiment of the present application is as follows: Figure 6 As shown, according to the control logic of the control device described above, the value of vaild varies in different situations. For example, under normal circumstances, vaild changes from 1 to 0 following the clk value, thereby implementing a one-time write to the FIFO and a one-time stop, i.e., writing data at 1x speed. When the ppm value is greater than 0, vaild is set to 1 for two consecutive clk values, writing data to the FIFO twice, i.e., writing data at 2x speed. When multiplexing is in effect (ppm < 0), vaild is set to 0 for two consecutive clk values, stopping the FIFO twice, i.e., writing data at 0x speed. Furthermore, the rate at which data is read from the FIFO remains constant.

[0086] The jump point refers to the situation where the size of data read from the FIFO is large due to VSRC resampling, so that the size of data stored in the FIFO is smaller than a threshold value; the multiplexing refers to the situation where the size of data read from the FIFO is small due to VSRC resampling, so that the size of data stored in the FIFO is larger than a threshold value.

[0087] It should be noted that, for the initial state of the resampling circuit, the control device sets vaild to 1. For example, when the size of the data stored in the FIFO is less than the threshold, VSRC reads two different data in parallel, starts resampling, and outputs the result.

[0088] Under normal circumstances, the control device sets vaild to 1. For example, when FIFO writes 4 new data, VSRC reads 2 different data in parallel and generates 2 results in parallel, the control device sets vaild to 0.

[0089] When a jump point occurs, for example, VSRC will read in 3 new data in succession and generate 2 results in parallel. The control device will set vaild to 1, and FIFO will write a total of 8 data twice in succession. The control device will set vaild to 0.

[0090] When multiplexing occurs, for example, VSRC reads two identical data in parallel and generates two results in parallel, the control device sets vaild to 0, and the FIFO stops writing new data twice in succession.

[0091] During operation, the output rate of VSRC remains stable.

[0092] In this example, a FIFO that can accommodate relatively small data sizes is used in the resampling circuit. The variable front-end operating rate is used to meet the data transmission rates of the VSRC in normal, hopping, and multiplexing conditions, significantly saving circuit area, delay, and power consumption.

[0093] Using the above control logic, it can be seen that when ppm>0, the Ts of the Farrow structure needs to be increased to (1+ppm)Ts, and the sampling points decrease after passing through VSRC. At this time, the Farrow front-end FIFO adjusts the Valid signal to switch the FIFO front-end communication circuit between 2x speed and 1x speed, thereby achieving the purpose of improving the data rate of reading the VSRC front-end circuit; when ppm<0, the Ts of the Farrow structure needs to be reduced to (1-ppm)Ts. The sampling points will increase after passing through VSRC. At this time, the Farrow front-end FIFO adjusts the Valid signal to switch the FIFO front-end communication circuit between 1x speed and 0x speed, thereby achieving the purpose of reducing the data rate of obtaining the VSRC front-end circuit.

[0094] It can be seen that, through this example, the area of FIFO is greatly saved, thereby saving the FIFO area and reducing the cost, and the reduction of FIFO also brings about a synchronous reduction in power consumption.

[0095] In related technologies, different circuit logic is required for processing when the ppm is positive or negative. For example, when the ppm is positive, the FIFO needs to be filled before sending data to the VSRC, while when the ppm is negative, the FIFO must send data when it is empty. In this example, the VSRC and FIFO can actively adjust the transmission rate of the VSRC front-end circuit in real time based on their own processing status, thereby simplifying the logic and reducing the delay caused by the large-capacity FIFO.

[0096] An embodiment of the present application provides a control method for controlling a resampling circuit, the resampling circuit including: a front-end circuit, a FIFO, and a variable sampling rate conversion circuit, including: obtaining a ratio coefficient of the FIFO depth occupied by the data processed by the front-end circuit stored in the FIFO, and controlling whether the FIFO writes the data processed by the front-end circuit according to the ratio coefficient, wherein the data processed by the front-end circuit written in the FIFO is used for resampling after being read by the variable sampling rate conversion circuit; that is, in an embodiment of the present application, through the control of the resampling circuit by the control device, it is possible to control whether the FIFO writes the data processed by the front-end circuit according to the ratio coefficient of the FIFO depth occupied by the stored data in the FIFO, so that the ratio coefficient of the FIFO depth occupied by the data stored in the FIFO is controlled, so that resampling can be achieved using a FIFO with a smaller depth, and the use of a smaller FIFO reduces the delay and power consumption of the transmitter of the communication system during resampling.

[0097] Based on the same inventive concept as the above embodiments, an embodiment of the present application provides a control device for controlling a resampling circuit, the resampling circuit comprising: a preamplifier circuit, a FIFO, and a variable sampling rate conversion circuit. Figure 7 A schematic diagram of the structure of an optional control device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the device includes:

[0098] An acquisition module 71 is used to obtain a ratio coefficient of the FIFO depth occupied by the data stored in the FIFO and processed by the front-end circuit;

[0099] A control module 72 is used to control whether the FIFO writes the data processed by the front-end circuit according to the proportional coefficient;

[0100] The data written into the FIFO and processed by the front-end circuit is read by the variable sampling rate conversion circuit and then resampled.

[0101] In an optional embodiment, the control module 72 is specifically configured to:

[0102] When the proportional coefficient is less than a preset threshold, the front-end circuit is controlled to write the processed data into the FIFO;

[0103] When the proportional coefficient is greater than a preset threshold, the front-end circuit is controlled to prohibit writing the processed data into the FIFO.

[0104] In an optional embodiment, the front-end circuit includes: a CFO compensation circuit.

[0105] In an optional embodiment, when the proportional coefficient is less than a preset threshold, the control device 72 controls the front-end circuit to write the processed data into the FIFO, including:

[0106] When the proportional coefficient is less than a preset threshold, generating a first control signal;

[0107] The first control signal is used to control the front-end circuit to write the data processed by the front-end circuit into the FIFO.

[0108] In an optional embodiment, the resampling circuit further includes: a gated clock, wherein the control device 72 uses a first control signal to control the front-end circuit to write the data processed by the front-end circuit into the FIFO, including:

[0109] The first control signal is used to control the gated clock to start, so that the front-end circuit writes the data processed by the front-end circuit into the FIFO.

[0110] In an optional embodiment, when the proportional coefficient is greater than a preset threshold, the control device 72 controls the front-end circuit to prohibit writing the processed data into the FIFO, including:

[0111] When the proportional coefficient is greater than a preset threshold, generating a second control signal;

[0112] The second control signal is used to control the front-end circuit to prohibit writing the data processed by the front-end circuit into the FIFO.

[0113] In an optional embodiment, the resampling circuit further includes: a gated clock, wherein the control device 72 uses the second control signal to control the front-end circuit to prohibit writing the data processed by the front-end circuit into the FIFO, including:

[0114] The second control signal is used to control the gated clock to be turned off, so that the front-end circuit is prohibited from writing data processed by the front-end circuit into the FIFO.

[0115] In an optional embodiment, the front-end circuit writes the data processed by the front-end circuit into the FIFO in a parallel manner.

[0116] In an optional embodiment, the variable sampling rate conversion circuit reads the data processed by the front-end circuit from the FIFO in a parallel manner.

[0117] In practical applications, the acquisition module 71 and the control module 72 may be implemented by a processor located on a control device, specifically a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0118] The embodiment of the present application provides a control method. Figure 8 A schematic diagram of the structure of another optional control device provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, an embodiment of the present application provides a control device 800, including:

[0119] A processor 81 and a storage medium 82 storing executable instructions of the processor 81, wherein the storage medium 82 relies on the processor 81 to perform operations through a communication bus 83. When the instructions are executed by the processor 81, the control method executed in one or more of the above embodiments is executed.

[0120] It should be noted that in actual application, the various components in the terminal are coupled together through the communication bus 83. It is understood that the communication bus 83 is used to realize the connection and communication between these components. In addition to the data bus, the communication bus 83 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 8 Various buses are labeled as communication buses 83.

[0121] The embodiment of the present application provides a chip, Figure 9 A schematic diagram of the structure of an optional chip provided in an embodiment of the present application is shown as follows: Figure 9 As shown, the chip 900 includes: a resampling circuit and the control device described in one or more of the above embodiments; wherein the resampling circuit includes: a front-end circuit, a FIFO and a variable sampling rate conversion circuit.

[0122] The chip 900 may be a wireless local area network (Wireless Fidelity, Wi-Fi) chip or a baseband chip.

[0123] The embodiment of the present application provides a chip, Figure 10 The structural diagram of another optional chip provided in the embodiment of the present application is as follows: Figure 10As shown, the chip 1000 includes: a processor 101, which is used to call and run a computer program from a memory 102, so that a device equipped with the chip 1000 executes the control method as described in one or more of the above embodiments.

[0124] Alternatively, as Figure 10 As shown, the chip 1000 may further include a memory 102. The processor 101 may call and run a computer program from the memory 102 to implement the method in the embodiment of the present application. The memory 102 may be a separate device independent of the processor 101, or may be integrated into the processor 101. Optionally, the chip 1000 may further include an input interface 103. The processor 101 may control the input interface 103 to communicate with other devices or chips, specifically, to obtain information or data sent by other devices or chips. Optionally, the chip 1000 may further include an output interface 104. The processor 101 may control the output interface 104 to communicate with other devices or chips, specifically, to output information or data to other devices or chips.

[0125] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0126] The chip 1000 may be a Wi-Fi chip or a baseband chip.

[0127] Figure 11 A schematic diagram of the structure of an optional electronic device provided in an embodiment of the present application is shown in FIG. Figure 11 As shown, an embodiment of the present application provides an electronic device 1100, including a chip 111 as described in one of the above embodiments.

[0128] Among them, the chip 111 can be Figure 9 Chip 900 or Figure 10 Chip 1000.

[0129] An embodiment of the present application provides a computer storage medium, wherein the computer-readable storage medium is used to store a computer program, and the computer program enables a computer to execute the steps of the control method described in one or more of the above embodiments.

[0130] Among them, the computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (Flash Memory), a magnetic surface storage device, an optical disc, or a compact disc read-only memory (CD-ROM) and other memories.

[0131] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0132] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0133] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0135] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A control method, characterized in that: The method is used to control a resampling circuit, wherein the resampling circuit includes: a preamplifier circuit, a FIFO, and a variable sampling rate conversion circuit, including: Obtaining a ratio coefficient of the depth of the FIFO occupied by the data stored in the FIFO and processed by the front-end circuit; According to the proportional coefficient, whether the FIFO is written with the data processed by the front-end circuit is controlled; wherein the data written in the FIFO after being processed by the front-end circuit is used for resampling after being read by the variable sampling rate conversion circuit; The step of controlling whether the FIFO writes the data processed by the front-end circuit according to the proportional coefficient includes: When the proportional coefficient is less than a preset threshold, controlling the front-end circuit to write the processed data into the FIFO; When the proportional coefficient is greater than the preset threshold, the front-end circuit is controlled to prohibit writing the processed data into the FIFO.

2. The method according to claim 1, characterized in that The front-end circuit includes: a CFO compensation circuit.

3. The method according to claim 1, characterized in that When the proportional coefficient is less than the preset threshold, controlling the front-end circuit to write the processed data into the FIFO includes: When the proportional coefficient is less than the preset threshold, generating a first control signal; The first control signal is used to control the front-end circuit to write the processed data into the FIFO.

4. The method according to claim 3, characterized in that The resampling circuit further includes: a gated clock, wherein the use of the first control signal to control the front-end to write the processed data into the FIFO includes: The first control signal is used to control the gated clock to start, so that the front-end circuit writes the processed data into the FIFO.

5. The method according to claim 1, wherein When the proportional coefficient is greater than the preset threshold, controlling the front-end circuit to prohibit writing the processed data into the FIFO includes: When the proportional coefficient is greater than the preset threshold, generating a second control signal; The second control signal is used to control the front-end circuit to prohibit writing the processed data into the FIFO.

6. The method according to claim 5, characterized in that The resampling circuit further includes: a gated clock, wherein the use of the second control signal to control the front-end circuit to prohibit writing the processed data into the FIFO includes: The second control signal is used to control the gated clock to be turned off, so that the front-end circuit prohibits writing the processed data into the FIFO.

7. The method according to claim 1, characterized in that The front-end circuit writes the processed data into the FIFO in a parallel manner.

8. The method according to claim 1, characterized in that The variable sampling rate conversion circuit reads the processed data from the FIFO in a parallel manner.

9. A control device, characterized in that: The control device is used to control the resampling circuit, which includes: a pre-circuit, a FIFO and a variable sampling rate conversion circuit, including: an acquisition module, configured to acquire a ratio coefficient of the depth of the FIFO occupied by the data stored in the FIFO and processed by the front-end circuit; A control module, configured to control whether the FIFO is written with the data processed by the front-end circuit according to the proportional coefficient; wherein the data written into the FIFO after being processed by the front-end circuit is read by the variable sampling rate conversion circuit and then resampled; The control module is used to: When the proportional coefficient is less than a preset threshold, controlling the front-end circuit to write the processed data into the FIFO; When the proportional coefficient is greater than the preset threshold, the front-end circuit is controlled to prohibit writing the processed data into the FIFO.

10. A control device, characterized in that: include: A processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the control method described in any one of claims 1 to 8 is executed.

11. A chip, characterized in that: include: A resampling circuit and a control device as claimed in claim 10; wherein the resampling circuit comprises: a front-end circuit, a FIFO and a variable sampling rate conversion circuit.

12. A chip, characterized in that: include: A processor, configured to call and run a computer program from a memory, so that a device equipped with the chip executes the control method according to any one of claims 1 to 8.

13. An electronic device, characterized in that: Comprising the chip as claimed in claim 11 or 12.

14. A computer-readable storage medium for storing a computer program, wherein the computer program enables a computer to execute the steps of the control method according to any one of claims 1 to 8.

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