Dynamic laser-assisted etching method

Abstract

The present disclosure provides a dynamic laser-assisted etching method. An etching method includes forming a plurality of semiconductor regions on a wafer; placing the wafer in an etching chamber; heating the wafer as a whole using a heating source; and projecting a laser beam onto the wafer. The plurality of semiconductor regions on the wafer are etched when the wafer is heated both by the heating source and by the laser beam.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to dynamic laser-assisted etching. Background Technology

[0002] The manufacturing of integrated circuits involves multiple process steps, including epitaxy and etching of semiconductor regions. Epitaxy and etching processes are typically performed at the wafer level, and often across the entire wafer. A wafer can contain multiple chips, which are subsequently diced into discrete dies. To maintain manufacturing yield, it is necessary to maintain the uniformity of the epitaxy and etching processes across the entire wafer. Summary of the Invention

[0003] According to one aspect of this application, an etching method is provided, comprising: forming a plurality of semiconductor regions on a wafer; placing the wafer in an etching chamber; heating the wafer as a whole using a heating source; projecting a first laser beam onto the wafer; and etching the plurality of semiconductor regions on the wafer while the wafer is heated by both the heating source and the first laser beam.

[0004] According to another aspect of this application, an etching method is provided, comprising: heating a wafer as a whole; using a first beam generated by a first local radiation source to locally heat a first portion of the wafer, wherein the first beam has a first size smaller than a second size of the wafer; and etching the wafer each time the wafer is both heated as a whole and locally heated.

[0005] According to another aspect of this application, an etching method is provided, comprising: generating a laser beam; adjusting the beam size of the laser beam using an optical device; heating a wafer using the laser beam; rotating the wafer; and etching the wafer while the wafer is heated and rotated by the laser beam. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1-6 An intermediate stage of transistor formation, including a laser-assisted etching process, is shown according to some embodiments.

[0008] Figure 7 A cross-sectional view of a wafer with non-uniform thickness of semiconductor regions according to some embodiments is shown.

[0009] Figure 8 A cross-sectional view of a wafer is shown, in which the thickness uniformity of the semiconductor region is improved according to some embodiments.

[0010] Figure 9 An apparatus for a laser-assisted etching process is shown according to some embodiments.

[0011] Figure 10 The tilt of a laser projector according to some embodiments is shown.

[0012] Figure 11 A top view of a wafer having a laser beam spot on it, according to some embodiments, is shown.

[0013] Figure 12 A top view of a wafer having multiple laser beam spots of different sizes, according to some embodiments, is shown.

[0014] Figure 13 The energy distribution in a laser beam according to some embodiments is shown.

[0015] Figure 14 The etching rate of a semiconductor region according to some embodiments is shown.

[0016] Figure 15-18 The diagram illustrates some laser beam travel patterns on a wafer according to some embodiments.

[0017] Figure 19 A process flow for forming transistors, including a laser-assisted etching process, is shown according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0020] A transistor formation process, including a laser-assisted etching process, is provided, along with corresponding apparatus for performing this process. According to some embodiments, epitaxial regions are formed on a wafer. Due to inhomogeneities in the epitaxial process, epitaxial regions in different portions of the wafer may have different thicknesses. An etching process can be performed to reduce or eliminate inhomogeneities. According to some embodiments, one or more laser beams are provided to selectively heat selected areas on the wafer during the etching process. The laser beams may be fixed to heat certain portions of the wafer or may be moved to project onto different locations on the wafer. The power, spot size, incident angle, etc., of the one or more laser beams can be adjusted according to the desired heating at the selected locations. The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of the invention, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. Similar reference numerals are used to designate similar elements in the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0021] Figures 1 to 6 A cross-sectional view of an intermediate stage of transistor formation according to some embodiments of the present disclosure is shown. Figure 19 The flowchart shown also schematically reflects the corresponding process.

[0022] Figure 1 A cross-sectional view of wafer 10 is shown. According to some embodiments, wafer 10 includes a semiconductor substrate 12, which may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, etc. Wafer 10 may include a number of different features formed of different materials, which may include, but are not limited to, shallow trench isolation (STI) regions, well regions, etc.

[0023] According to some embodiments, wafer 10 includes a plurality of semiconductor regions 14, one of which is illustrated. Semiconductor region 14 may be a protruding semiconductor fin that protrudes above an adjacent STI region (not in the plane shown), the adjacent STI region defining the boundary of semiconductor region 14.

[0024] Gate stack 16 can be formed on the top surface and sidewalls of semiconductor region 14. Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 202. According to some embodiments, the gate stack 16 is a dummy gate stack, and is therefore referred to hereinafter as dummy gate stack 16. According to alternative embodiments, the gate stack 16 is actually the gate stack in the final structure. The dummy gate stack 16 may include a dummy gate dielectric 18 and a dummy gate electrode 20 located on the dummy gate dielectric 18. The dummy gate dielectric 18 may be formed by oxidizing a surface portion of the protruding fin 14 to form an oxide layer or by depositing a dielectric layer such as a silicon oxide layer. For example, polycrystalline silicon or amorphous silicon may be used, and other materials such as amorphous carbon may also be used to form the dummy gate electrode 20. Each dummy gate stack 16 may also include corresponding hard masks 22 and 24 on each dummy gate electrode 20. The hard masks 22 and 24 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxynitride, or multiple layers thereof. The formation of the dummy gate stack 16 may include: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by one or more patterning processes.

[0025] Deposited spacer layers 26A and 26B, collectively referred to as spacer layer 26. In Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 204. According to some embodiments of this disclosure, the spacer layer 26 is formed of a dielectric material selected from the group consisting of silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxynitride (SiOCN), etc. As shown, the spacer layer 26 can have a multilayer structure and can include two, three, or more sublayers comprising different materials. Alternatively, a single spacer layer 26 can be used. The formation process can include one or more conformal deposition processes such that spacer layers 26A and 26B are conformal, for example, different portions of each of spacer layers 26A and 26B have a thickness variation of less than about 20% or less than about 10%. The formation process can include ALD, CVD, etc.

[0026] refer to Figure 2 An anisotropic etching process is performed. The horizontal portion of the spacer layer 26 is removed, thereby exposing the lower portion of the semiconductor region 14. Figure 19In the process flow 200 shown, the corresponding process is shown as process 206. The vertical portion of the spacer layer 26 is retained as the gate spacer 26'. The etching process can be performed using etching gases (e.g., mixtures of NF3 and NH3, mixtures of HF and NH3, and / or fluorine-containing gases (e.g., CF4, NF3, SF6, CHF3) or combinations thereof).

[0027] Next, an etching process is used to vertically recess a portion of the semiconductor region 14 that is laterally offset from the dummy gate stack 16 and the gate spacer 26', to form a recess 28. Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 208. For example, a dry etching process can be performed using C2F6, CF4, SO2; a mixture of HBr, Cl2, and O2; or a mixture of HBr, Cl2, O2, and CH2F2 to etch the semiconductor region 14. According to some embodiments where the semiconductor region 14 includes protruding semiconductor fins, the bottom of the recess 28 may be flush with or below the bottom of the protruding semiconductor fins to extend into the body portion beneath the semiconductor substrate 12. The etching can be anisotropic, such that some sidewalls of the semiconductor region 14 facing the recess 28 are vertical and straight.

[0028] Figure 3 The epitaxy of semiconductor region 32 is schematically shown. Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 210. It should be understood that although one semiconductor region 32 is shown, multiple semiconductor regions 32 are grown simultaneously throughout the wafer 10. Therefore, throughout the specification, when referring to (one or more) semiconductor regions 32, either the singular or plural form may be used. The epitaxial process may be performed in a vacuum chamber, and the wafer 10 is placed on a substrate (e.g., an electronic chuck) 33.

[0029] Semiconductor region 32 may be or may include silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium gallium arsenide (InxGa1-xAs), indium aluminum arsenide (InxAl1-xAs), indium phosphide (InP), indium antimonide (InSb), indium gallium antimonide (InxGa1-xSb), gallium antimonide (GaSb), etc., or combinations thereof. According to some embodiments, semiconductor region 32 is selectively grown from a semiconductor material (e.g., the exposed surface of semiconductor region 14) rather than from an exposed dielectric region (e.g., STI region, gate spacer 26', hard mask 24, etc.). For example, selective growth can be achieved by introducing an etching gas such as HCl or Cl2.

[0030] According to some embodiments, epitaxial growth is performed using chemical vapor deposition (CVD), atomic layer deposition (ALD), reduced pressure chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. Semiconductor region 32 can be a source / drain region for forming an n-type or p-type transistor, and therefore can also be referred to as source / drain region 32. The source / drain region 32 of an n-type transistor can be doped with n-type impurities, such as phosphorus, arsenic, antimony, etc., or combinations thereof. The source / drain region 32 of a p-type transistor can be doped with p-type impurities, such as boron, indium, gallium, etc., or combinations thereof.

[0031] During the epitaxial process, heat source 36 can be used to heat the wafer 10 as a whole. According to some embodiments, heat source 36 includes one or more lamps (e.g., halogen lamps) that can project visible light or broad-spectrum light in the range from infrared (IR) to ultraviolet (UV). Heat source 36 may also include multiple regions, such as external and internal regions with separate controls. According to an alternative embodiment, wafer 10 is heated from below, and a pedestal 33 may be heated to heat wafer 10. Heating of the pedestal may also be based on heating of the bottom lamps, which may also include multiple regions. According to yet another alternative embodiment, both heat source 36 and heated pedestal 33 are used.

[0032] According to some embodiments, wafer-level inhomogeneity may exist in the growth rate of semiconductor regions 32 throughout wafer 10. Therefore, the growth rate of semiconductor regions 32 in some portions of wafer 10 may be higher than the growth rate of semiconductor regions 32 in other portions of wafer 10. Wafer-level inhomogeneity may be caused by inhomogeneity in heating wafer 10 during epitaxial processes and / or other factors such as inhomogeneity in precursor flow.

[0033] Figure 7 A cross-sectional view of wafer 10 is schematically shown, in which some example semiconductor regions 32 are shown. Figure 7 Other features of wafer 10 are not shown, such as Figure 3 The dummy gate stack 16 and gate spacer 26' shown are also present as part of wafer 10.

[0034] Due to non-uniformity in the epitaxial process, such as Figure 7 As shown, different epitaxial regions 32 may have different thicknesses, such as the thicknesses T1, T2, and T3 shown. For example, at the wafer center, the thickness T1 corresponding to the epitaxial region 32 can be greater than the thicknesses T2 and T3, where thickness T3 is the thickness of the semiconductor region 32 near the edge of the wafer 10, and thickness T2 is the thickness of the semiconductor region 32 in the region between the center and the edge of the wafer 10. In the region between the center and the edge of the wafer 10, the semiconductor region 32 has a thickness T2.

[0035] Depending on the materials, epitaxial processes, etc., different types of inhomogeneities may exist. For example, the thickness T2 in some regions may be greater than the thickness T1 and / or the thickness T3. Furthermore, when moving laterally along the diameter of wafer 10 from the center of wafer 10 to the edge of wafer 10, the thickness of the corresponding semiconductor region 32 may gradually increase or decrease until at a certain point, the thickness begins to decrease or increase again.

[0036] refer to Figure 4 An etching process 34 is performed on wafer 10. Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 212. During the etch-back process, semiconductor regions 32 are selectively etched and recessed, but not completely removed. The etch-back process has the function of causing some regions of semiconductor regions 32 to be etched back more or less than other semiconductor regions 32, thereby improving through-wafer uniformity in terms of the thickness of wafer 32. In addition, the etch-back process can be performed to remove any semiconductor material that has been unintentionally deposited on dielectric regions (e.g., on the sidewalls of gate spacer 26' and hard mask 24).

[0037] According to some embodiments, an etching process 34 is performed after the epitaxial process is completed, and the top surface of semiconductor region 32 is higher than the top surface of semiconductor region 14, such as... Figure 4 As shown. According to an alternative embodiment, etch-back can be performed before the epitaxial process is complete. For example, Figure 3 The dashed line 35 represents the surface of semiconductor region 32 during the etch-back process. After the etch-back process is performed on surface 35, epitaxy can continue. There can be one or more epitaxy and etch-back cycles.

[0038] According to some embodiments, the etch-back process is performed in situ in the same vacuum chamber as the preceding epitaxial process, or in a non-situ vacuum chamber different from the epitaxial chamber. When in different vacuum chambers, the etching chamber performing the etch-back process can be in the same production tool as the epitaxial chamber performing the epitaxial process. Vacuum disruption may not occur when transferring wafer 10 between the epitaxial chamber and the etching chamber.

[0039] In the etching process, wafer 10 is placed and fixed on a base (electronic chuck) 33', which can be connected to base 33 ( Figure 3 The substrate 33' may be the same as or different from the epitaxial process 34, depending on whether the etch-back process is performed in the same vacuum chamber as the epitaxial process. According to some embodiments, the substrate 33' is configured to rotate during the etch-back process 34. A heat source 36' may be provided and used to heat the wafer 10 as a whole during the etch-back process. The heat source 36' may also be the same as the heat source 36 (…). Figure 3The heat source 36' may be the same or different, depending on whether the etch-back process is performed in the same vacuum chamber as the epitaxial process. According to some embodiments, the heat source 36' projects visible light or light with a broad spectrum from infrared to UV. The heat source 36' may be located outside or inside the corresponding vacuum chamber (e.g., Figure 9 (as shown in vacuum chamber 76).

[0040] During the etch-back process, one or more laser projectors 40 are used to generate laser beams and locally heat wafer 10. This means that each time, the laser projectors 40 heat a portion or some portions of wafer 10, but not the entire top surface area of ​​wafer 10. The laser projectors 40 are configured to generate laser beams 42 and are alternatively referred to as laser generators. The corresponding etching process 34 is referred to below as laser-assisted etching. Details of the laser projectors 40 and their use will be discussed in detail in subsequent paragraphs.

[0041] According to some embodiments, during the etch-back process, wafer temperature affects the etching rate, and the higher the wafer temperature, the higher the etching rate. According to some embodiments, wafer 10 can be heated to a temperature in the range of approximately 400°C to approximately 700°C. The temperature can also be in the range of approximately 500°C to approximately 600°C. The etching gas can be selected from HCl, Cl2, GeH... x Cl 4-x SiH x Cl 4-x Or a combination thereof. The pressure in the etching chamber can be in the range of about 1 torr to about 200 torr, and can be in the range of about 1 torr to about 50 torr. The flow rate of the etching gas can be in the range of about 10 sccm to about 1000 sccm, and can be in the range of about 10 sccm to about 200 sccm. One or more carrier gases such as hydrogen (H2) and / or nitrogen (N2) can be used. The flow rate of the etching gas can be in the range of about 5000 sccm to about 75000 sccm, and can be in the range of about 40000 sccm to about 50000 sccm.

[0042] The etching-back process can achieve near-wafer-level uniformity in terms of thickness in the semiconductor region 32. For example, Figure 8 This illustrates that after the etch-back process, the resulting semiconductor region 32 has thicknesses T1', T2', and T3', which are greater than... Figure 7The thicknesses T1, T2, and T3 shown are more uniform. The absolute value of the thickness difference in semiconductor region 32 is reduced through the etching process. For example, the absolute thickness difference |T1'-T2'| is less than the absolute thickness difference |T1-T2|. Furthermore, the relationships |T2'-T3'|<|T2-T3| and |T1'-T3'|<|T1–T3| can be obtained through the etching process.

[0043] Wafer-level uniformity of the thickness of semiconductor regions 32 is achieved by locally heating wafer 10 using a laser projector 40. For example, assuming the first semiconductor region 32 is thicker than the second semiconductor region 32, the first semiconductor region 32 will be etched more than the second semiconductor region 32 during the etch-back process. This can be achieved by using the laser projector 40 to raise the temperature of the first semiconductor region 32 to a higher temperature than the second semiconductor region 32. With the first semiconductor region 32 at a higher temperature, the etch rate of the semiconductor region 32 increases more than that of the second semiconductor region 32. Because the wafer 10 is locally heated using one or more projectors 40, the temperature of selected portions of the wafer 10 can be adjusted to a selected temperature, and the etch rate can also be locally adjusted to achieve wafer-level uniformity.

[0044] To achieve wafer-level uniformity in the thickness of the semiconductor region 32, experiments can be conducted to determine thickness non-uniformity within the wafer and the corresponding temperatures in different portions of the wafer. For example, a sample wafer can be formed, and the semiconductor region 32 can be formed within it. The thickness of the semiconductor region 32 in different portions of the sample wafer is then measured, and wafer-level non-uniformity is determined. Accordingly, the thickness reduction value for different portions of the sample wafer is calculated. Furthermore, a relationship between wafer temperature and the etching rate of the semiconductor region 32 is established. Then, the local temperature (and temperature difference) used by different portions of the wafer during etching is calculated using the thickness reduction value and the correlation.

[0045] Furthermore, the parameters for laser local heating (e.g., laser beam size, incident angle, laser beam travel speed, number of laser projectors used, etc.) are also determined based on the requirements for local heating. These parameters will be discussed in detail in subsequent paragraphs. The non-uniformity data collected from the sample wafers can then be used for mass production wafers, thereby enabling wafer-level uniformity in mass-produced wafers.

[0046] In the above embodiments, a laser-assisted etching process is used to etch the epitaxial region. According to alternative embodiments, the laser-assisted etching process and etching apparatus can be used to etch other features and materials besides the semiconductor region 32. For example, the etching material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, crystalline silicon-germanium, polycrystalline silicon-germanium, amorphous silicon-germanium, III-V compound semiconductors, etc. The etched region may be doped with n-type dopant, p-type dopant, or undoped.

[0047] Figure 5 The formation of the contact etch stop layer (CESL) 52 and the interlayer dielectric (ILD) 54 is shown. Figure 19 In the process flow 200 shown, the corresponding process is shown as process 214. According to some embodiments of this disclosure, CESL 52 is formed of or contains silicon nitride, silicon carbonitride, etc. CESL 52 can be formed by conformal deposition processes such as ALD or CVD. ILD 54 is formed on CESL 52 and can be formed using processes such as FCVD, spin coating, CVD, etc. ILD 54 can be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), silicon oxide, etc. Planarization processes, such as chemical mechanical polishing (CMP) or mechanical polishing, can be performed to make the top surfaces of CESL 52, ILD 54, dummy gate stack 16, and gate spacer 26' flush with each other.

[0048] For example Figure 5 As shown, a replacement gate stack 68 is formed. It should be understood that the replacement gate stack 68 can be formed before the source / drain contact plug 58 is formed (e.g., Figure 5 (as shown) or formed subsequently, such as Figure 6 As shown. The replacement gate stack 68 may include a gate dielectric 64 and a gate electrode 66.

[0049] Etching was performed on CESL 52 and ILD 54 to form contact opening 49. Figure 19 In the process flow 200 shown, the corresponding process is shown as process 216. Figure 5 The formation of silicide region 50 is further illustrated. Figure 19In the illustrated process flow 200, the corresponding process is shown as process 218. According to some embodiments, a metal layer 46 (e.g., a titanium or cobalt layer) is deposited, for example, using physical vapor deposition (PVD). A capping layer 48 is then deposited over the metal layer 46. The capping layer 48 may be a metal nitride layer, such as a titanium nitride or tantalum nitride layer. Both the metal layer 46 and the capping layer 48 may be conformal and extend into the contact opening 49. An annealing process is then performed to react the metal layer 46 with silicon (and germanium, if present) in the semiconductor region 32. This forms the source / drain silicide region 50.

[0050] Figure 6 The formation of the contact plug 58 is shown. In Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 220. According to some embodiments, a metal material is deposited on and in contact with a conductive capping layer 48. The metal material may include tungsten, cobalt, etc. A planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove excess portions of the capping layer 48 and the metal material. The remaining portion of the metal material is referred to as metal region 56. Metal region 56, together with the metal layer 46 and the remaining portion of the capping layer 48, forms the source / drain contact plug 58. A transistor 60 is thus formed.

[0051] refer to Figure 9 The diagram shows a production tool 70, which includes tools for etching semiconductor regions 32 (such as...). Figure 4 Vacuum chamber 76 (shown). Vacuum chamber 76 may or may not be used for epitaxial processes. Wafer 10 is placed and secured on base 33'. According to some embodiments, base 33' is configured to rotate, as indicated by arrow 72. Process gas 78 is supplied to wafer 10, which may include etching gases such as HCl, Cl2, and (one or more) carrier gases.

[0052] A heat source 36' is provided and configured to project light 74 onto the wafer 10 for overall heating of the wafer 10. The heat source 36' may be located outside or inside the vacuum chamber 76. A heat source may or may not be located beneath the wafer 10. The heat source 36' is configured to provide as uniform heating as possible to the wafer 10 so that different portions of the wafer 10 are heated to the same temperature as much as possible, which may be in the range of approximately 400°C to approximately 700°C. Alternatively, the temperature may be in the range of approximately 500°C to approximately 600°C.

[0053] At least one laser projector 40 or more laser projectors 40 are used in the laser-assisted etching process. According to some embodiments, the laser projector 40 is located inside the vacuum chamber 76, such as... Figure 9As shown. According to alternative embodiments, one or all of the laser projectors 40 are located outside the vacuum chamber 76. According to these embodiments, at least the top portion of the chamber wall of the vacuum chamber 76 (which may have a transparent window) is transparent to allow the laser beam 42 to pass through. The transparent chamber wall may be formed of or contain materials such as quartz, silicon dioxide, ceramic, glass, etc.

[0054] The laser projector 40 is configured to generate a laser beam 42 and project it onto the wafer 10, thereby increasing the temperature of the projected area of ​​the wafer 10. The laser beam 42 is projected onto a region of the semiconductor region 32 where the thickness is greater than that of other regions through etch-back. The laser beam 42 can also be directed to a wafer region where the temperature is lower than other wafer regions, so that temperature non-uniformity caused by the heat source 36' can be corrected.

[0055] The laser projector 40 can be of various types, and the generated laser beam 42 can be selected from a variety of different types. For example, the generated laser can be a gas laser (e.g., a helium-neon laser), an excimer laser (e.g., a KrF laser (wavelength approximately 248 nm)), a XeCl laser (wavelength approximately 308 nm), a XeF laser (wavelength approximately 351 nm), a solid-state laser, a semiconductor diode laser, or other lasers.

[0056] According to some embodiments, a single laser projector 40 is present. According to alternative embodiments, multiple (e.g., 2, 3, 4, 5 or more) laser projectors 40 are used. In the following discussion, multiple laser projectors 40 are discussed as examples, and the embodiments discussed can also be applied to a single laser projector 40 if applicable. The laser beams 42 generated by different laser projectors 40 can be the same as each other or different from each other, for example, having the same or different wavelengths, spot sizes, power density values, etc.

[0057] Laser projectors 40 are electrically and signal-connected to control unit 80, which is configured to control the operation of each laser projector 40. The corresponding operations are then discussed. For example, control unit 80 is configured to tilt the laser projectors 40 so that the laser beam 42 travels on wafer 10. Control unit 80 can also adjust the output power of the laser beam 42 based on non-uniformity data obtained from the sample wafer. For example, when the laser beam 42 travels to certain portions of wafer 10 requiring more etching, control unit 80 increases the output power of the corresponding laser projector. Conversely, when the laser beam 42 travels to other portions of the wafer requiring less etching, control unit 80 decreases or turns off the output power of the corresponding laser projector 40. Control unit 80 can control the operation of the laser projectors 40 independently of each other. For example, when the output power of one laser projector 40 decreases, the output power of another laser projector 40 can increase. The travel direction, speed, etc., of multiple laser beams 42 can also be controlled independently. Control unit 80 can also control the motor that rotates wafer 10 to adjust the rotation speed of wafer 10. The control of the laser beam 42 can be synchronized with the adjustment of the wafer rotation.

[0058] According to some embodiments, some of all laser projectors 40 may have optical devices 82 (including optical devices 82A and 82B as examples) for adjusting the size of the corresponding laser beam 42. For example, optical device 82A may include a convex lens (and additional convex and concave lenses) and can be used to reduce the size of the corresponding laser beam. Optical device 82B may include a concave lens (and additional convex and concave lenses) and can be used to increase the size of the corresponding laser beam. There may (or there may not be) some laser projectors 40 that are not attached with any optical devices, such as... Figure 9 As shown.

[0059] Figure 10 An example of how the laser beam 42 travels on wafer 10 is shown. The corresponding laser projector 40 can be tilted, for example, having a tilt angle range β. This also causes the corresponding laser beam 42 to tilt within the tilt angle range β. The tilt angle range β is selected such that the corresponding laser beam 42 can travel between the center and the edge of wafer 10, or can travel from one edge to another along the same diameter of wafer 10. According to some embodiments, the tilt angle range β can be less than about 45 degrees. The travel path of the laser beam 42 can be along the diameter of wafer 10, or it can be misaligned with any diameter of wafer 10.

[0060] Figure 11A top view of wafer 10 is shown, having a center 10C and an edge 10E, wherein the edge 10E is circular. During the etch-back process, wafer 10 rotates relative to the center 10C. Wafer 10 can rotate at speeds ranging from approximately 1 revolution per minute to approximately 60 revolutions per minute. A laser beam spot 84 is shown, which is a laser beam 42 ( Figure 9 The landing area on wafer 10. As the laser beam 42 travels, the laser beam spot 84 can be projected onto and cover any selected area on wafer 10. The laser beam spot 84 can travel back and forth within a selected range on wafer 10. For example, Figure 11 An example travel range is shown. The travel range can also extend from the center 10C to the edge 10E, or from edge 10E1 to the opposite edge 10E2.

[0061] The power density of the laser beam 42 cannot be too high or too low. If the power density is too high, it will be difficult to control the temperature rise. If the power density is too low, it will take too long to heat the area to the ideal temperature, and the laser beam may not be able to cover all the desired areas of the wafer in time. The power density of the laser beam 42 can be around 1 mW / mm². 2 Approximately 50000mW / mm 2 Within the range, and can be at approximately 100mW / mm 2 Approximately 1000mW / mm 2 Within a certain range. The laser power can be fixed or adjustable. For example, for solid-state lasers or semiconductor diode lasers, the power can be tuned by adjusting the input drive current of the laser projector 40. Laser beam spot 84 ( Figure 11 The received power density can be the same as or slightly lower than the output power density of the laser beam 42.

[0062] During the etching process, the power intensity of some or all of the laser beam 42 can remain constant or change dynamically over time. For example, the laser power density can be tuned to approximately 100 mW / mm². 2 It lasted for 1 second and was then tuned to approximately 200 mW / mm. 2The laser beam power density can be adjusted in conjunction with the movement of the laser projector 40 and the adjustment of the incident angle for 1 second. For example, during the movement of the laser beam spot, the laser power can be increased when the laser beam spot passes through a wafer region requiring more thickness reduction. Conversely, the laser power can be decreased when the laser beam spot passes through a wafer region requiring less thickness reduction. The laser power can be turned off when the laser beam spot passes through a wafer region requiring minimal thickness reduction. Furthermore, as the laser beam 42 travels along a path in one direction (e.g., from edge 10E1 to edge 10E2), the laser beam 42 can be turned on and off for multiple cycles, and the power density can also be adjusted for multiple cycles. This allows for different heating temperatures to be achieved for multiple portions (e.g., multiple annular regions) on the wafer 10.

[0063] Figure 12 A top view of wafer 10 is shown, illustrating multiple laser beam spots 84 (including 84A, 84B, and 84C). The spot size of the laser beam 42 partially determines the power density values, such as P1, P2, and P3, which affect the desired temperature change induced by the laser beam. The spot size also affects the expected heating rate (e.g., temperature change per unit time, in °C / min). Smaller spot sizes result in higher and faster temperature rise. Furthermore, smaller spot sizes allow for more precise and selective heating in more localized areas, while larger spot sizes allow for coverage of larger areas. Spot sizes D1, D2, and D3 can range from approximately 1 mm to approximately 50 mm, and specifically from approximately 5 mm to approximately 10 mm. Spot sizes D1, D2, and D3 can be the same or different from each other, and these spot sizes can be adjusted using optical devices if necessary.

[0064] The wavelength of the laser beam 42 is related to the power density, and the smaller the wavelength, the higher the power density. According to some embodiments, the wavelength of the laser beam 42 can be in the range of about 400 nm to about 1400 nm, and can be in the range of about 800 nm to about 1100 nm. The wavelengths of different laser beams 42 can be selected independently and can be the same as or different from each other.

[0065] Return to Figure 9 The incident angle of the laser beam 42 (including θ1, θ2, and θ3) can also affect the power density received by the wafer 10, and the smaller the incident angle, the lower the power density received by the wafer 10. According to some embodiments, the incident angle of the laser beam 42 can be in the range of about 45 degrees to about 90 degrees, and can be in the range of about 75 degrees to about 90 degrees. The incident angles of different laser beams can also be controlled independently and can be the same or different from each other.

[0066] Figure 13 The power density distribution in the laser beam is shown, which is a function of distance from the beam center. It is observed that the power density may peak at the beam center and decreases with distance from the beam center. Therefore, the corresponding temperature rise caused by the laser beam also exhibits a similar distribution.

[0067] Figure 14 The etching rate of an etched semiconductor region affected by a laser beam is shown, where the etching rate is the decrease in the thickness of the etched region (per unit time). Figure 14 The etch rates of wafer regions projected by three laser beams are illustrated by an example. The etch rate ER0 represents the etch rate of the portion of the etched semiconductor region affected by overall heating rather than localized heating. This indicates that the etch rate can be significantly higher in the portion of the wafer to which the laser beams are projected. For example, the etch rate ratios ER1 / ER0, ER2 / ER0, and ER3 / ER0 may be greater than 1.0, and can range from 1 to about 10, or from about 1.5 to about 5. The corresponding temperature rise in the laser-heated portion of wafer 10 can range from about 20°C to about 150°C.

[0068] Figures 15 to 18 Some patterns of laser beam spots on wafer 10 according to some embodiments are shown. Figure 15 In this configuration, wafer 10 is stationary and does not rotate. The laser beam spot 84 can be moved to any selected area on wafer 10 and can be heated point-by-point. For example, Figure 15 A straight path for heating wafer 10 is shown according to some embodiments. Point heating can also be performed at random points on wafer 10 based on the etching rate requirements of local areas of wafer 10.

[0069] Figure 16 An embodiment is shown where the wafer 10 is rotated while the laser projector 40 is fixed at an angle. Therefore, when the laser projector 40 is fixed in one position, the laser beam spot 84 will scan along a circle. When the laser projector 40 moves to a second position and is fixed there, the laser beam spot 84 will scan along another circle. As the laser beam spot moves to multiple positions, multiple concentric laser scanning paths are generated.

[0070] Figure 17 An embodiment is shown where wafer 10 rotates and laser projector 40 moves simultaneously. For example, initially, wafer 10 rotates and the laser beam spot is located at position 86. Therefore, the scanning path includes circles. Then, the laser beam spot moves towards the edge of wafer 10. Therefore, the scanning path also includes a spiral pattern.

[0071] Figure 18An embodiment is shown where the wafer 10 rotates and the laser beam spot moves simultaneously. These embodiments are similar to... Figure 17 The embodiment shown differs in that, Figure 17 In this process, the laser beam travels slowly, and by the time the laser beam travels from position 86 to edge 10E, wafer 10 has already rotated at least one or more times. However, in Figure 18 In the process, the laser beam travels very quickly, and by the time wafer 10 rotates once, the laser beam has already traveled back and forth multiple times (e.g., Figure 18 (8 laps in the middle).

[0072] like Figures 15 to 18 As shown, pattern selection can be influenced by the desired temperature change and rate of temperature rise. The target area exposed to the laser beam may require approximately 10 milliseconds to reach a stable temperature, and after 5 milliseconds, the temperature is essentially stable. Further heating (before reaching a stable temperature) requires additional time, which may be longer at higher temperatures (and other factors such as power density also affect the required heating time). Therefore, the dwell time (the period during which the target area is exposed to the laser beam) can be selected to be at least 5 milliseconds, and within the range of approximately 5 milliseconds to approximately 500 milliseconds, or within the range of approximately 5 milliseconds to approximately 100 milliseconds.

[0073] According to some embodiments, the localized heating process (e.g., which parts of the wafer will be heated, the desired temperature rise, etc.) is determined before the etch-back process. According to alternative embodiments, the determination is performed dynamically. For example, the desired temperature on a localized region of wafer 10 can be determined from a sample wafer. During the etch-back process, the temperature of the localized region heated by the laser beam is measured in real time, for example, using one or more pyrometers. The measured temperature can be fed back to the control unit 80 (…). Figure 9 The control unit 80 adjusts the power, intensity, moving speed, and moving range of the laser beam 42 to ensure that the local temperature (and local etching rate) meets the requirements.

[0074] It should be recognized that while lasers are used as a heat source for locally heating wafers, alternative local heat sources capable of locally heating wafers can also be employed. For example, focused UV beams of limited size (e.g., less than approximately 50 mm) can also be used. When using alternative local heat sources, references can also be applied. Figures 9 to 18 Examples of laser projectors discussed.

[0075] Although etching of epitaxial semiconductor regions is used as an example to illustrate the concept of the invention, the concept can be applied to etching of other features and materials (including but not limited to dielectric materials, metals, etc.). For example, in... Figure 1Before forming the dummy gate, a uniform-thickness semiconductor layer can be epitaxially grown on the semiconductor substrate 12. The uniform-thickness semiconductor layer can be a fully strained silicon-germanium layer, a fully strained germanium layer, or the like. The uniform-thickness semiconductor layer may have thickness non-uniformity, which can be reduced by employing a laser-assisted etching process according to some embodiments.

[0076] The embodiments of this disclosure have several advantageous features. By locally heating the wafer in a controlled manner, the etching rate in a localized area of ​​the wafer can be increased to a desired value. This can be used to reduce the inhomogeneity of the etched material.

[0077] According to some embodiments of this disclosure, a method includes: forming a plurality of semiconductor regions on a wafer; placing the wafer in an etching chamber; heating the wafer as a whole using a heat source; projecting a first laser beam onto the wafer; and etching the plurality of semiconductor regions on the wafer while the wafer is heated by both the heat source and the first laser beam. In one embodiment, the method further includes projecting a second laser beam onto the wafer while the plurality of semiconductor regions are being etched. In one embodiment, the laser beam spot of the first laser beam and the laser beam spot of the second laser beam have different sizes.

[0078] In one embodiment, the first laser beam and the second laser beam have different power density values. In one embodiment, the first laser beam and the second laser beam have different wavelengths. In one embodiment, the wafer is rotated during etching. In one embodiment, during etching, the spot of the first laser beam travels between the center and the edge of the wafer. In one embodiment, the method further includes: fixing the first laser beam at a first position at a first distance from the center of the wafer and rotating the wafer at least one revolution; and moving the first laser beam to a second position at a second distance from the center and rotating the wafer at least one revolution. In one embodiment, the first laser beam is generated by a laser beam generator, and the method further includes: inserting an optical device between the laser beam generator and the wafer to adjust the size of the first laser beam. In one embodiment, the size of the first laser beam is increased by using the optical device.

[0079] According to some embodiments of this disclosure, a method includes: overall heating of a wafer; localizing heating of a first portion of the wafer using a first beam generated by a first local radiation source, wherein the first beam has a first size smaller than a second size of the wafer; and etching the wafer each time the wafer is both overall and locally heated. In one embodiment, the first portion of the wafer has a first temperature when heated by the first beam, and a second portion of the wafer not heated by the first beam has a second temperature lower than the first temperature.

[0080] In one embodiment, a first portion of the wafer has a first etch rate when heated by a first beam, and a second portion of the wafer, located away from the first portion and not heated by the first beam, has a second etch rate lower than the first etch rate. In one embodiment, the first local radiation source includes a laser beam generator. In one embodiment, the first local radiation source includes an ultraviolet beam generator. In one embodiment, the method further includes: locally heating a second portion of the wafer using a second beam generated by a second local radiation source, wherein the first beam and the second beam are separated from each other.

[0081] According to some embodiments of this disclosure, a method includes: generating a laser beam; adjusting the beam size of the laser beam using optical devices; heating a wafer using the laser beam; rotating the wafer; and etching the wafer while it is heated and rotated by the laser beam. In one embodiment, the laser beam generates a laser beam spot on the wafer, and the laser beam spot travels between the center and the edge of the wafer as it is etched and rotated. In one embodiment, the method further includes: epitaxially growing an epitaxial semiconductor region as a top portion of the wafer, wherein etching the wafer includes etching the epitaxial semiconductor region.

[0082] Here are some specific examples.

[0083] Example 1. An etching method, comprising:

[0084] Multiple semiconductor regions are formed on the wafer;

[0085] The wafer is placed in the etching chamber;

[0086] The wafer is heated as a whole using a heating source;

[0087] Projecting a first laser beam onto the wafer; and

[0088] When the wafer is heated by both the heating source and the first laser beam, the plurality of semiconductor regions on the wafer are etched.

[0089] Example 2. The method according to Example 1 further includes projecting a second laser beam onto the wafer while the plurality of semiconductor regions are being etched.

[0090] Example 3. The method according to Example 2, wherein the laser beam spot of the first laser beam and the laser beam spot of the second laser beam have different sizes.

[0091] Example 4. The method according to Example 2, wherein the first laser beam and the second laser beam have different power density values.

[0092] Example 5. The method according to Example 2, wherein the first laser beam and the second laser beam have different wavelengths.

[0093] Example 6. The method according to Example 1, wherein the wafer is rotated during the etching.

[0094] Example 7. The method according to Example 6, wherein, during etching, the spot of the first laser beam travels between the center and the edge of the wafer.

[0095] Example 8. The method described in Example 6 further includes:

[0096] The first laser beam is fixed at a first position at a first distance from the center of the wafer, and the wafer is rotated at least one revolution; and

[0097] The first laser beam is moved to a second position at a second distance from the center, and the wafer is rotated at least one revolution.

[0098] Example 9. The method according to Example 1, wherein the first laser beam is generated by a laser beam generator, and the method further comprises: inserting an optical device between the laser beam generator and the wafer to adjust the size of the first laser beam.

[0099] Example 10. The method according to Example 9, wherein the size of the first laser beam is increased by using the optical device.

[0100] Example 11. An etching method, comprising:

[0101] Whole-wafer heating;

[0102] A first portion of the wafer is locally heated using a first beam of light generated by a first local radiation source, wherein the first beam has a first size smaller than a second size of the wafer; and

[0103] The wafer is etched each time it is heated both as a whole and in a localized manner.

[0104] Example 12. The method according to Example 11, wherein the first portion of the wafer has a first temperature when heated by the first light beam, and the second portion of the wafer not heated by the first light beam has a second temperature lower than the first temperature.

[0105] Example 13. The method according to Example 12, wherein the temperature difference between the first temperature and the second temperature is in the range of 20°C to 150°C.

[0106] Example 14. The method according to Example 11, wherein the first portion of the wafer has a first etch rate when heated by the first beam, and a second portion of the wafer, located away from the first portion and not heated by the first beam, has a second etch rate lower than the first etch rate.

[0107] Example 15. The method according to Example 11, wherein the first local radiation source includes a laser beam generator.

[0108] Example 16. The method according to Example 11, wherein the first local radiation source includes an ultraviolet beam generator.

[0109] Example 17. The method according to Example 11 further includes: locally heating a second portion of the wafer using a second beam generated by a second local radiation source, wherein the first beam and the second beam are separated from each other.

[0110] Example 18. An etching method, comprising:

[0111] Generate a laser beam;

[0112] The size of the laser beam is adjusted using optical equipment;

[0113] The laser beam is used to heat the wafer;

[0114] Rotate the wafer; and

[0115] The wafer is etched when it is heated and rotated by the laser beam.

[0116] Example 19. The method according to Example 18, wherein the laser beam generates a laser beam spot on the wafer, and wherein, as the wafer is etched and rotated, the laser beam spot travels between the center and the edge of the wafer.

[0117] Example 20. The method according to Example 18 further includes: epitaxially growing an epitaxial semiconductor region as a top portion of the wafer, wherein etching of the wafer includes etching the epitaxial semiconductor region.

[0118] This disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An etching method, comprising: Multiple semiconductor regions are formed on the wafer; The wafer is placed in the etching chamber; The wafer is heated as a whole using a heating source; A first laser beam is projected onto a first portion of the wafer using a first laser projector; A second laser beam is projected onto a second portion of the wafer using a second laser projector that is positioned separately from the first laser projector; as well as When the wafer is heated by both the heat source and the first and second laser beams, the plurality of semiconductor regions on the wafer are etched. During the etching process, the wafer is rotated, and the spot of the first laser beam travels between the center and the edge of the wafer.

2. The method according to claim 1, wherein, The laser beam spot of the first laser beam and the laser beam spot of the second laser beam have different sizes.

3. The method according to claim 1, wherein, The first laser beam and the second laser beam have different power density values.

4. The method according to claim 1, wherein, The first laser beam and the second laser beam have different wavelengths.

5. The method according to claim 1, further comprising: The first laser beam is fixed at a first position at a first distance from the center of the wafer, and the wafer is rotated at least one revolution. as well as The first laser beam is moved to a second position at a second distance from the center, and the wafer is rotated at least one revolution.

6. The method according to claim 1, wherein, The first laser beam is generated by a laser beam generator, and the method further includes inserting an optical device between the laser beam generator and the wafer to adjust the size of the first laser beam.

7. The method according to claim 6, wherein, The size of the first laser beam is increased by using the optical device.

8. An etching method, comprising: Whole-wafer heating; A first portion of the wafer is locally heated using a first beam generated by a first local radiation source, wherein the first beam has a first size smaller than a second size of the wafer; A second portion of the wafer is locally heated using a second beam generated by a second local radiation source arranged separately from the first local radiation source, wherein the first beam and the second beam are separated from each other; and Each time the wafer is heated both overall and locally, the wafer is etched. During the etching process, the wafer is rotated, and the spot of the first beam travels between the center and the edge of the wafer.

9. The method according to claim 8, wherein, The first portion of the wafer has a first temperature when heated by the first light beam, and the third portion of the wafer that is not heated by the first light beam and the second light beam has a second temperature that is lower than the first temperature.

10. The method according to claim 9, wherein, The temperature difference between the first temperature and the second temperature is in the range of 20°C to 150°C.

11. The method according to claim 8, wherein, The first portion of the wafer has a first etch rate when heated by the first beam, and the third portion of the wafer, which is away from the first portion and is not heated by the first beam and the second beam, has a second etch rate that is lower than the first etch rate.

12. The method according to claim 8, wherein, The first local radiation source includes a laser beam generator.

13. The method according to claim 8, wherein, The first local radiation source includes an ultraviolet beam generator.

14. An etching method, comprising: A first laser beam is generated using a first laser projector; The size of the first laser beam is adjusted using optical equipment; A second laser beam is generated using a second laser projector that is arranged separately from the first laser projector; The first portion of the wafer is heated using the first laser beam, and the second portion of the wafer is heated using the second laser beam. Rotate the wafer; as well as The wafer is etched when it is heated and rotated by the first laser beam and the second laser beam. Wherein, the first laser beam generates a first laser beam spot on the wafer, and wherein, when the wafer is etched and rotated, the first laser beam spot travels between the center and the edge of the wafer.

15. The method of claim 14, further comprising: An epitaxial semiconductor region is grown as the top portion of the wafer, wherein etching of the wafer includes etching the epitaxial semiconductor region.

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