Memory elements and methods of making the same

Abstract

A memory device having a plurality of word lines (WL) and reduced leakage and a method of fabricating the same are provided. The memory device includes a semiconductor substrate defining an active region and including a recess extending into the semiconductor substrate; and a word line disposed in the recess, wherein the word line includes an insulating layer disposed in the recess, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the recess and a protruding portion disposed over the conductive layer. A method of fabricating the memory device is also disclosed.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 552,882 and 17 / 552,736 (i.e., priority date of “December 16, 2021”), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory element and a method of fabricating the same, and more particularly, to a memory element having a word line with reduced leakage and a method of fabricating the same. BACKGROUND

[0003] Dynamic random access memory (DRAM) is a semiconductor configuration for storing data bits in individual capacitors within an integrated circuit (IC). DRAM is typically formed as a trench capacitor DRAM cell. An advanced method of fabricating a buried gate electrode involves building a transistor’s gate and word line in a trench of an active area (AA) including a shallow trench isolation (STI) structure.

[0004] Over the past few decades, as semiconductor fabrication technology has advanced, electronic devices have correspondingly shrunk in size. As the size of a unit transistor is reduced to a length of a few nanometers, current leakage can occur. Leakage current can cause a significant degradation in the performance of the unit transistor. Accordingly, it is desirable to develop improved measures that address the associated fabrication challenges.

[0005] The foregoing “background” description is for the purpose of generally presenting the technical field and does not necessarily pertain to the present disclosure, which, as provided herein, presents a new and improved method of fabricating a buried gate electrode. The foregoing “background” description is not to be taken as an admission of the validity of any portion of the “background” description, and is not to be taken as an indication that the “background” description is related to a prior art of the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate defining an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the recess and a protrusion portion disposed above the conductive layer.

[0007] In some embodiments, a top surface of the liner portion and a top surface of the protrusion portion are exposed through the semiconductor substrate.

[0008] In some embodiments, the protrusion portion is in contact with a top surface of the conductive layer.

[0009] In some embodiments, the protrusion portion is disposed above the conductive member.

[0010] In some embodiments, the liner portion and the protruding portion comprise a same material.

[0011] In some embodiments, the liner portion and the protruding portion are integrally formed.

[0012] In some embodiments, the insulating layer comprises an oxide.

[0013] In some embodiments, the conductive layer comprises titanium nitride (TiN).

[0014] In some embodiments, the conductive member comprises tungsten (W).

[0015] In some embodiments, the word line comprises a work function member disposed above the conductive layer and the conductive member, and a gate insulating member disposed above the work function member.

[0016] In some embodiments, the work function member and the gate insulating member are surrounded by the insulating layer.

[0017] In some embodiments, the work function member and the gate insulating member are in contact with the protruding portion.

[0018] In some embodiments, a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the work function member.

[0019] In some embodiments, a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the gate insulating member.

[0020] In some embodiments, the work function member comprises polysilicon.

[0021] In some embodiments, the gate insulating member comprises nitride.

[0022] Another embodiment of the present disclosure provides a memory element. The memory element comprises a semiconductor substrate defining an active region and comprising a first recess extending into the semiconductor substrate; and a word line disposed within the first recess, wherein the word line comprises a first insulating layer disposed within the first recess, a first conductive layer surrounded by the first insulating layer, and a first conductive member surrounded by the first conductive layer, and the first insulating layer is at least partially disposed on the first conductive layer.

[0023] In some embodiments, the first insulating layer is in contact with a top surface of the first conductive layer.

[0024] In some embodiments, a width of the first insulating layer on the first conductive layer is substantially greater than a width of the first insulating layer around the first conductive layer and the first conductive member.

[0025] In some embodiments, the memory element further includes an isolation structure adjacent to the word line and extending into the semiconductor substrate, a second conductive layer surrounded by the isolation structure, and a second conductive member surrounded by the second conductive layer.

[0026] In some embodiments, a width of the isolation structure over the second conductive layer is substantially greater than a width of the isolation structure surrounding the second conductive layer and the second conductive member.

[0027] In some embodiments, the second conductive layer comprises titanium nitride (TiN).

[0028] In some embodiments, the second conductive member comprises tungsten (W).

[0029] In some embodiments, the first conductive layer and the second conductive layer comprise a same material.

[0030] In some embodiments, the first conductive member and the second conductive member comprise a same material.

[0031] Another embodiment of the disclosure provides a method of fabricating a memory element. The method includes the steps of: providing a semiconductor substrate defining an active region and including an isolation layer surrounding the active region; forming a first recess extending into the semiconductor substrate and through the active region; forming a first liner portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first liner portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer surrounding the first conductive member; and forming a first protruding portion of the first insulating layer over the first conductive layer and the first conductive member.

[0032] In some embodiments, the forming of the first liner portion is performed prior to the forming of the first protruding portion.

[0033] In some embodiments, the method further includes, after disposing the second conductive material, removing a portion of the first conductive material disposed over the first conductive member.

[0034] In some embodiments, the forming of the first protruding portion includes disposing an insulating material over the semiconductor substrate, the first liner portion, the first conductive layer, and the first conductive member.

[0035] In some embodiments, the insulating material is disposed by atomic layer deposition (ALD).

[0036] In some embodiments, the forming of the first protrusion portion includes removing a portion of the insulating material disposed over the semiconductor substrate and the first liner portion.

[0037] In some embodiments, the portion of the insulating material is removed by anisotropic etching.

[0038] In some embodiments, the fabrication method further includes forming a second recess extending to the spacer to form a second liner portion of the isolation structure; forming a second conductive layer surrounded by the second liner portion; forming a second conductive member surrounded by the second conductive layer; and forming a second protrusion portion of the isolation structure over the second conductive layer and the second conductive member.

[0039] In some embodiments, the first protrusion portion and the second protrusion portion are formed simultaneously.

[0040] In some embodiments, the fabrication method further includes forming a first work function member over the first conductive layer and surrounded by the first protrusion portion; and forming a first gate insulating member over the first work function member and surrounded by the first protrusion portion.

[0041] In summary, since the insulating layer surrounding the word line around the work function member has a greater thickness compared to the insulating layer surrounding the conductive member under the work function member, gate induced drain leakage current (GIDL) can be suppressed. In addition, the insulating layer surrounding the conductive member has a smaller thickness, so operation control of the word line can be improved. Therefore, the performance of the memory element and the manufacturing process of the memory element are improved.

[0042] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. The present disclosure is to be considered as encompassing all possible embodiments and equivalents thereof. One skilled in the art will readily recognize from the following description that alternative embodiments of the present disclosure can be utilized without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is not to be restricted in scope only to the specific embodiments described. BRIEF DESCRIPTION OF DRAWINGS

[0043] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference symbols refer to like elements throughout the several views, and in which:

[0044] Figure 1 is a cross-sectional side view illustrating a memory element of some embodiments of the present disclosure.

[0045] Figure 2 is a cross-sectional side view illustrating a memory element of other embodiments of the present disclosure.

[0046] Figure 3 is a flowchart illustrating a method of manufacturing a memory element of some embodiments of the present disclosure.

[0047] Figures 4 to 20 is a cross-sectional view illustrating an intermediate stage in the formation of a memory element of some embodiments of the present disclosure.

[0048] In the drawings:

[0049] 100: memory element

[0050] 101: semiconductor substrate

[0051] 101a: active region

[0052] 101b: first surface

[0053] 101c: second surface

[0054] 102: isolation structure

[0055] 102a: second liner portion

[0056] 102b: second protruding portion

[0057] 102c: top surface

[0058] 102d: top surface

[0059] 102e: isolation layer

[0060] 103: trench

[0061] 103a: recess (first recess)

[0062] 103b: second recess

[0063] 104: first insulating layer

[0064] 104a: first liner portion

[0065] 104b: first protruding portion

[0066] 104c: top surface

[0067] 104d: top surface

[0068] 105: first conductive layer

[0069] 105a: top surface

[0070] 105b: first conductive material

[0071] 105c: fifth conductive material

[0072] 106: second conductive layer

[0073] 106a: top surface

[0074] 106b: second conductive material

[0075] 106c: sixth conductive material

[0076] 107: first conductive member

[0077] 107a: third conductive material

[0078] 108: second conductive member

[0079] 108a: fourth conductive material

[0080] 111: first work function member

[0081] 111a: first work function material

[0082] 112: second work function member

[0083] 112a: first work function material

[0084] 113: first gate insulating member

[0085] 114: second gate insulating member

[0086] 120: word line

[0087] 124: insulating material

[0088] 125: conductive material

[0089] 200: memory element

[0090] A-A': line

[0091] B-B': line

[0092] S300: manufacturing method

[0093] S301: step

[0094] S302: step

[0095] S303: step

[0096] S304: step

[0097] S305: step

[0098] S306: step

[0099] S307: step

[0100] W1 : overall width

[0101] W2: overall width

[0102] W3: width

[0103] W4: width

[0104] W5: width

[0105] W6: width DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. For simplicity, in the following description a particular embodiment will be described solely as taught herein. Of course, that embodiment is merely an example of the claimed subject matter and should not be considered in isolation to be limiting. For example, in the following description, the formation of a first feature on a second feature can include embodiments in which the first and second features are in direct contact, and can also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact.

[0107] Furthermore, the disclosure can employ reference numerals and / or letters in various embodiments in order to more readily describe some of the various embodiments and / or settings. Such re-use of designators is for purposes of convenience and illustration and does not in fact limit the scope of the application as set forth in the claims.

[0108] In addition, spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The spatially relative terms can therefore include the various orientations of the elements described herein, as well as their orientations in the figures. The spatially relative terms are intended to encompass various other orientations of the elements and, therefore, the spatially relative terms can also be interpreted to include the various other orientations of the elements described herein.

[0109] Figure 1 is a cross-sectional side view illustrating a memory element 100 of some embodiments of the present disclosure. In some embodiments, the memory element 100 includes a number of unit cells arranged in rows and columns.

[0110] In some embodiments, the memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped monocrystalline silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

[0111] In some embodiments, the semiconductor substrate 101 includes a plurality of active areas (AAs) 101a. An active area 101a is a doped region in the semiconductor substrate 101. In some embodiments, an active area 101a extends horizontally above or below a top surface of the semiconductor substrate 101. In some embodiments, each active area 101a includes a same type of dopant. In some embodiments, each active area 101a includes a different type of dopant than included in other active areas 101a. In some embodiments, each active area 101a has a same conductivity type. In some embodiments, the active areas 101a include an N-type dopant.

[0112] In some embodiments, the semiconductor substrate 101 includes a first surface 101b and a second surface 101c opposite the first surface 101b. In some embodiments, the first surface 101b is a front surface of the semiconductor substrate 101, where electronic elements or components are subsequently formed above the first surface 101b and configured to electrically connect with external circuitry. In some embodiments, the second surface 101c is a back surface of the semiconductor substrate 101, where there are no electronic elements or components.

[0113] In some embodiments, the semiconductor substrate 101 includes a recess 103a extending into the semiconductor substrate 101. In some embodiments, the recess 103a extends from the first surface 101b toward the second surface 101c of the semiconductor substrate 101. In some embodiments, the recess 103a tapers from the first surface 101b toward the second surface 101c of the semiconductor substrate 101. In some embodiments, a depth of the recess 103a is substantially greater than a depth of the active areas 101a.

[0114] In some embodiments, the memory element 100 includes a word line 120 disposed within the recess 103a. In some embodiments, the word line 120 includes the first insulating layer 104, the first conductive layer 105, and the first conductive member 107. In some embodiments, the first insulating layer 104 is conformal to the recess 103a and disposed therein. In some embodiments, the first conductive layer 105 is surrounded by the first insulating layer 104. In some embodiments, the first conductive member 107 is surrounded by the first conductive layer 105.

[0115] In some embodiments, the first insulating layer 104 is disposed along the entire sidewall of the recess 103a. In some embodiments, the first insulating layer 104 includes a dielectric material, such as an oxide. In some embodiments, the first insulating layer 104 is fabricated from an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof. In some embodiments, the first insulating layer 104 includes an insulating material having a low dielectric constant (low-k).

[0116] In some embodiments, the first insulating layer 104 includes a first liner portion 104a conformal to the recess 103a and a first overhanging portion 104b disposed over the first conductive layer 105. In some embodiments, the first liner portion 104a is disposed along the entire sidewall of the recess 103a. In some embodiments, the first liner portion 104a is coupled to the first overhanging portion 104b. In some embodiments, the first overhanging portion 104b overhangs from the first liner portion 104a.

[0117] In some embodiments, the first overhanging portion 104b has a thickness in a range of about 2 microns to about 3 microns. In some embodiments, the first overhanging portion 104b includes a low-k dielectric material. In some embodiments, the first liner portion 104a has a thickness in a range of about 4 microns to 6 microns. In some embodiments, the first liner portion 104a has a thickness substantially greater than a thickness of the first overhanging portion 104b.

[0118] In some embodiments, a top surface 104c of the first liner portion 104a and a top surface 104d of the first overhanging portion 104b are exposed by the semiconductor substrate 101. In some embodiments, the first liner portion 104a and the first overhanging portion 104b include a same material or a different material. In some embodiments, the first liner portion 104a and the first overhanging portion 104b are integrally formed.

[0119] In some embodiments, the first conductive layer 105 is disposed within the recess 103a and is surrounded by the first insulating layer 104. In some embodiments, the first conductive layer 105 is surrounded by the first liner portion 104a and is disposed below the first protrusion portion 104b. In some embodiments, a top surface 105a of the first conductive layer 105 is in contact with the first protrusion portion 104b. In some embodiments, the top surface 105a of the first conductive layer 105 is substantially lower than a top surface 104c of the first liner portion 104a and a top surface 104d of the first protrusion portion 104b. In some embodiments, the first conductive layer 105 comprises a conductive material, such as titanium nitride (TiN).

[0120] In some embodiments, the first conductive member 107 is disposed within the first conductive layer 105. The first conductive member 107 is surrounded by the first liner portion 104a. In some embodiments, the first conductive member 107 is disposed below the active region 101a of the semiconductor substrate 101. In some embodiments, the first protrusion portion 104b is disposed over the first conductive member 107. In some embodiments, the first conductive member 107 comprises a conductive material, such as tungsten (W).

[0121] In some embodiments, the word line 120 further comprises a first work function member 111 disposed over the first conductive layer 105 and the first conductive member 107, and a first gate insulating member 113 disposed over the first work function member 111. In some embodiments, the first work function member 111 and the first gate insulating member 113 are surrounded by the first insulating layer 104. In some embodiments, the first work function member 111 and the first gate insulating member 113 are surrounded by and in contact with the first protrusion portion 104b. In some embodiments, the first work function member 111 is in contact with the top surface 105a of the first conductive layer 105.

[0122] In some embodiments, a total width Wl of the first conductive layer 105 and the first conductive member 107 is substantially equal to a total width W2 of the first protrusion portion 104b and the first work function member 111. In some embodiments, the total width Wl is substantially equal to a total width W2 of the first protrusion portion 104b and the first gate insulating member 113. In some embodiments, the first work function member 111 comprises polysilicon or polycrystalline silicon. In some embodiments, the first work function member 111 has a low work function. In some embodiments, the first work function member 111 has a dual work function, comprising a metal and polysilicon. In some embodiments, the first work function member 111 functions as a gate electrode.

[0123] In some embodiments, the first gate insulating member 113 comprises a dielectric material, such as nitride. In some embodiments, the first gate insulating member 113 functions as a gate dielectric. In some embodiments, a top surface of the first gate insulating member 113 is substantially coplanar with a top surface 104c of the first liner portion 104a and a top surface 104d of the first protruding portion 104b.

[0124] In some embodiments, the memory element 100 further comprises an isolation structure 102 adjacent to the word line 120. In some embodiments, the isolation structure 102 extends from the first surface 101b to the second surface 101c into the semiconductor substrate 101. In some embodiments, the isolation structure 102 is a shallow trench isolation (STI). In some embodiments, the isolation structure 102 defines a boundary of the active region 101a.

[0125] In some embodiments, the isolation structure 102 comprises a second liner portion 102a and a second protruding portion 102b laterally protruding from the second liner portion 102a. In some embodiments, a thickness of the second protruding portion 102b is in a range from about 2 microns to about 3 microns. In some embodiments, the second liner portion 102a and the second protruding portion 102b comprise a same material or a different material. In some embodiments, the second liner portion 102a and the second protruding portion 102b are integrally formed.

[0126] In some embodiments, a fabrication technique of the isolation structure 102 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof. In some embodiments, the isolation structure 102 and the first insulating layer 104 comprise a same material or a different material. In some embodiments, a width of the isolation structure 102 is substantially greater than a width of the word line 120. In some embodiments, a depth of the isolation structure 102 is substantially greater than a depth of the word line 120.

[0127] In some embodiments, the second conductive layer 106 and the second conductive member 108 are surrounded by the second liner portion 102a of the isolation structure 102. In some embodiments, the second conductive member 108 is surrounded by the second conductive layer 106. In some embodiments, the second conductive layer 106 and the second conductive member 108 are disposed under the second protruding portion 102b. In some embodiments, the second protruding portion 102b is in contact with the second conductive layer 106.

[0128] In some embodiments, the second conductive layer 106 comprises a conductive material, such as titanium nitride (TiN). In some embodiments, the second conductive member 108 comprises a conductive material, such as tungsten (W). In some embodiments, the first conductive layer 105 and the second conductive layer 106 comprise a same material or a different material. In some embodiments, the first conductive member 107 and the second conductive member 108 comprise a same material or a different material.

[0129] In some embodiments, a second work function member 112 is disposed over the second conductive layer 106 and the second conductive member 108, and a second gate insulating member 114 is disposed over the second work function member 112. In some embodiments, the second work function member 112 and the second gate insulating member 114 are surrounded by the isolation structure 102. In some embodiments, the second work function member 112 and the second gate insulating member 114 are surrounded by and in contact with the second protruding portion 102b. In some embodiments, the second work function member 112 is in contact with the top surface 106a of the second conductive layer 106.

[0130] In some embodiments, the second work function member 112 comprises polysilicon or poly-silicon. In some embodiments, the second work function member 112 has a low work function. In some embodiments, the second work function member 112 has a dual work function, comprising a metal and polysilicon. In some embodiments, the second gate insulating member 114 comprises a dielectric material, such as nitride.

[0131] In some embodiments, the first work function member 111 and the second work function member 112 comprise a same material or a different material. In some embodiments, the first gate insulating member 113 and the second gate insulating member 114 comprise a same material or a different material. In some embodiments, a top surface of the second gate insulating member 114 is substantially coplanar with a top surface 102c of the second liner portion 102a and a top surface 102d of the second protruding portion 102b.

[0132] Since the upper portion of the first insulating layer 104 (surrounding the word line 120 of the first work function member 111) has a greater thickness than the lower portion of the first insulating layer 104 (surrounding the first conductive layer 105 and the first conductive member 107 below the first work function member 111), gate-induced drain leakage (GIDL) can be suppressed. Furthermore, the first insulating layer 104 surrounding the first conductive layer 105 and the first conductive member 107 has a smaller thickness, and thus operation control of the word line 120 can be improved. Therefore, performance of the memory element 100 can be improved.

[0133] Figure 2This is a cross-sectional side view illustrating a memory element 200 according to some embodiments of the present disclosure. The memory element 200 is similar to the memory element 100, except that... Figure 2 There are no interfaces within the first insulating layer 104 and the isolation structure 102. In other words, as Figure 1 The first liner portion 104a and the first protruding portion 104b shown are integrally formed, respectively becoming Figure 2 The first insulating layer 104 and the isolation structure 102 are shown. In some embodiments, the first insulating layer 104 is at least partially disposed on the first conductive layer 105.

[0134] In some embodiments, the width W3 of the first insulating layer 104 above the first conductive layer 105 is substantially greater than the width W4 of the first insulating layer 104 surrounding the first conductive layer 105 and the first conductive member 107. In some embodiments, the width W5 of the isolation structure 102 above the second conductive layer 106 is substantially greater than the width W6 of the isolation structure 102 surrounding the second conductive layer 106 and the second conductive member 108.

[0135] Figure 3 This is a flowchart illustrating method S300 for fabricating memory element 100 or 200 according to some embodiments of this disclosure. Figures 4 to 20 This is a cross-sectional view illustrating an intermediate stage in the formation of a memory element 100 or 200 according to some embodiments of this disclosure.

[0136] exist Figures 4 to 20 The illustrated stage can also be found in Figure 3 This is illustrated in the flowchart. In the following discussion, Figures 4 to 20 The exemplified preparation stage is a reference. Figure 3 The process steps are discussed. Preparation method S300 includes several operations, and the description and explanation are not intended to limit the order of operations. Preparation method S300 includes several steps (S301, S302, S303, S304, S305, S306 and S307).

[0137] Reference Figure 4 and Figure 5 ,according to Figure 3 In step S301, a semiconductor substrate 101 is provided. Figure 4 This is a cross-sectional top view illustrating a semiconductor substrate 101. Figure 5 This is an example along Figure 4FIG. 3 is a cross-sectional view of the semiconductor substrate 101 taken along line A-A'. In some embodiments, the semiconductor substrate 101 is defined to have an active region 101a and includes an isolation layer 102e surrounding the active region 101a. In some embodiments, the isolation layer 102e extends from a first surface 101b to a second surface 101c of the semiconductor substrate 101. In some embodiments, the isolation layer 102e comprises a dielectric material, such as an oxide or the like.

[0138] Referring to Figure 6 and Figure 7 , according to step S302 in Figure 3 , a first recess 103a extending to the semiconductor substrate 101 is formed. Figure 6 FIG. 4 is a cross-sectional top view of the semiconductor substrate 101, Figure 7 FIG. 5 is a cross-sectional view of the semiconductor substrate 101 taken along line B-B' in Figure 6 In some embodiments, a plurality of trenches 103 are formed on the first surface 101b of the semiconductor substrate 101. The trenches 103 extend through the active region 101a or the isolation region 102e (as shown in Figure 4 and Figure 5 ).

[0139] In some embodiments, the formation of the trenches 103 includes the formation of the first recess 103a and the formation of a second recess 103b. In some embodiments, the formation of the first recess 103a and the formation of the second recess 103b are performed separately or simultaneously. In some embodiments, the formation of the first recess 103a includes removing portions of the semiconductor substrate 101. In some embodiments, the formation of the second recess 103b includes removing portions of the isolation layer 102e.

[0140] In some embodiments, the first recess 103a extends through the active region 101a and the second recess 103b extends through the isolation layer 102e. In some embodiments, the first recess 103a and the second recess 103b extend from the first surface 101b to the second surface 101c of the semiconductor substrate 101. In some embodiments, the second liner portion 102a is formed after the formation of the second recess 103b.

[0141] Referring to Figure 8 , according to step S303 in Figure 3 , a first liner portion 104a of a first insulating layer 104 conformal to the first recess 103a is formed. In some embodiments, the first liner portion 104a is disposed within the first recess 103a. In some embodiments, the first liner portion 104a is formed by deposition, oxidation, or any other suitable process. In some embodiments, the first liner portion 104a comprises an oxide.

[0142] Referring toFigure 9 and Figure 10 According to step S304 in Figure 3 , a first conductive material 105b is disposed conformal to the first liner portion 104a. In some embodiments, as shown in Figure 9 , a conductive material 125 is disposed over the semiconductor substrate 101 and surrounded by the first liner portion 104a and the second liner portion 102a, and then portions of the conductive material 125 are removed to form the first conductive material 105b and the second conductive material 106b, as shown in Figure 10 .

[0143] In some embodiments, the first conductive material 105b and the second conductive material 106b are disposed separately or simultaneously by deposition or any other suitable process. In some embodiments, the first conductive material 105b and the second conductive material 106b comprise titanium nitride (TiN). In some embodiments, the first conductive material 105b and the second conductive material 106b are conformal to the first liner portion 104a and the second liner portion 102a, respectively.

[0144] Referring to Figure 11 and Figure 12 , according to step S305 in Figure 3 , a first conductive member 107 is formed surrounded by the first conductive material 105b. The first conductive member 107 is disposed within the first recess 103a and surrounded by the first liner portion 104a and the first conductive material 105b. In some embodiments, the first conductive member 107 is formed by disposing a third conductive material 107a surrounded by the first conductive material 105b, as shown in Figure 11 , and then removing a portion of the third conductive material 107a to become the first conductive member 107, as shown in Figure 12 .

[0145] In some embodiments, the third conductive material 107a is disposed by deposition or any other suitable process. In some embodiments, the portion of the third conductive material 107a is removed by etching or any other suitable process. In some embodiments, the third conductive material 107a comprises tungsten (W).

[0146] In some embodiments, a second conductive member 108 is also formed surrounded by the second conductive material 106b. The second conductive member 108 is disposed within the second recess 103b and surrounded by the second liner portion 102a and the second conductive material 106b. In some embodiments, the second conductive member 108 is formed by disposing a fourth conductive material 108a surrounded by the second conductive material 106b, as shown in Figure 11 , and then removing a portion of the fourth conductive material 108a to become the second conductive member 108, as shown in Figure 12shown.

[0147] In some embodiments, the fourth conductive material 108a is disposed by deposition or any other suitable process. In some embodiments, the portion of the fourth conductive material 108a is removed by etching or any other suitable process. In some embodiments, the fourth conductive material 108a comprises tungsten (W). In some embodiments, the formation of the first conductive member 107 and the formation of the second conductive member 108 are performed separately or simultaneously.

[0148] Referring to Figure 13 and Figure 14 , according to step S306 in Figure 3 , the fifth conductive material 105c is disposed over the first conductive member 107 to form the first conductive layer 105 surrounding the first conductive member 107. In some embodiments, the fifth conductive material 105c is disposed on the first conductive member 107 by deposition or any other suitable process. In some embodiments, the fifth conductive material 105c and the first conductive material 105b are the same material. In some embodiments, the fifth conductive material 105c comprises titanium nitride (TiN).

[0149] In some embodiments, after the fifth conductive material 105c is disposed as shown in Figure 13 , a portion of the first conductive material 105b is removed to form the first conductive layer 105 as shown in Figure 14 . In some embodiments, the portion of the first conductive material 105b is removed by etching, cleaning or any other suitable process.

[0150] In some embodiments, the sixth conductive material 106c is disposed on the second conductive member 108 by deposition or any other suitable process. In some embodiments, the sixth conductive material 106c and the second conductive material 106b are the same material. In some embodiments, the sixth conductive material 106c comprises titanium nitride (TiN). In some embodiments, the first conductive material 105b, the fifth conductive material 105c, the second conductive material 106b and the sixth conductive material 106c are the same material. In some embodiments, the disposing of the fifth conductive material 105c and the disposing of the sixth conductive material 106c are performed separately or simultaneously.

[0151] In some embodiments, after the sixth conductive material 106c is disposed as shown in Figure 13 , a portion of the second conductive material 106b is removed to form the second conductive layer 106 as shown in Figure 14The second conductive layer 106 is shown. In some embodiments, the portion of the second conductive material 106b is removed by etching, cleaning, or any other suitable process. In some embodiments, the removal of the portion of the first conductive material 105b and the removal of the portion of the second conductive material 106b are performed separately or simultaneously.

[0152] Referring to Figure 15 and Figure 16 , according to step S307 in Figure 3 , a first protruding portion 104b of the first insulating layer 104 over the first conductive layer 105 and the first conductive member 107 is formed. In some embodiments, the formation of the first protruding portion 104b includes disposing an insulating material 124 over the semiconductor substrate 101, the first liner portion 104a, the first conductive layer 105, and the first conductive member 107. In some embodiments, the insulating material 124 is disposed by atomic layer deposition (ALD) or any other suitable process.

[0153] In some embodiments, after the insulating material 124 is disposed as shown in Figure 15 , a portion of the insulating material 124 disposed over the semiconductor substrate 101 and the first liner portion 104a is removed to form the first protruding portion 104b. In some embodiments, the portion of the insulating material 124 is removed by anisotropic etching, planarization, or any other suitable process. The first protruding portion 104b is disposed over the first conductive layer 105 and the first conductive member 107.

[0154] In some embodiments, a second protruding portion 102b of the isolation structure 102 over the second conductive layer 106 and the second conductive member 108 is also formed. In some embodiments, the formation of the second protruding portion 102b includes disposing the insulating material 124 over the semiconductor substrate 101, the second liner portion 102a, the second conductive layer 106, and the second conductive member 108 as shown in Figure 15 , and then removing a portion of the insulating material 124 disposed over the semiconductor substrate 101 and the second liner portion 102a to form the second protruding portion 102b as shown in Figure 16 . The second protruding portion 102b is disposed over the second conductive layer 106 and the second conductive member 108. In some embodiments, the formation of the first protruding portion 104b and the formation of the second protruding portion 102b are performed separately or simultaneously.

[0155] Referring to Figure 17 and Figure 18 , a first work function member 111 over the first conductive layer 105 and surrounded by the first protruding portion 104b is formed. In some embodiments, as shown in Figure 17As shown, the first work function component 111 is formed by providing a first work function material 111a surrounded by a first protrusion 104b, and then removing a portion of the first work function material 111a to form such a structure. Figure 18 The first work function component 111 is shown. In some embodiments, the first work function material 111a is formed by deposition, CVD, or any other suitable process. In some embodiments, this portion of the first work function material 111a is removed by etching or any other suitable process.

[0156] In some embodiments, the second work function member 112 is formed by providing a second work function material 112a surrounded by the second protrusion 102b, such as Figure 17 As shown, then a portion of the second work function material 112a is removed to form the second work function component 112, as... Figure 18 As shown. In some embodiments, the second work function material 112a is formed by deposition, CVD, or any other suitable process. In some embodiments, this portion of the second work function material 112a is removed by etching or any other suitable process.

[0157] In some embodiments, the setting of the first work function material 111a and the setting of the second work function material 112a are performed separately or simultaneously. In some embodiments, the first work function material 111a and the second work function material 112a are the same material. In some embodiments, the first work function material 111a and the second work function material 112a comprise polycrystalline silicon.

[0158] Reference Figure 19 A first gate insulating member 113 is formed over the first work function member 111 and surrounded by a first protrusion 104b. In some embodiments, the formation of the first gate insulating member 113 includes depositing a gate insulating material by deposition or any other suitable process. In some embodiments, a second gate insulating member 114 is formed over the second work function member 112 and surrounded by a second protrusion 102b. In some embodiments, the formation of the first gate insulating member 113 and the second gate insulating member 114 are performed separately or simultaneously. In some embodiments, Figure 1 Memory element 100, such as Figure 19 As shown in the diagram. In some embodiments, Figure 2 Memory element 200, such as Figure 20 As shown in the diagram.

[0159] In one embodiment of the present disclosure, a memory element is provided. The memory element includes a semiconductor substrate defining an active region and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the recess and a protruding portion disposed over the conductive layer.

[0160] In another embodiment of the present disclosure, a memory element is provided. The memory element includes a semiconductor substrate defining an active region and including a first recess extending into the semiconductor substrate; and a word line disposed within the first recess, wherein the word line includes a first insulating layer disposed within the first recess, a first conductive layer surrounded by the first insulating layer, and a first conductive member surrounded by the first conductive layer, and the first insulating layer is at least partially disposed over the first conductive layer.

[0161] In another embodiment of the present disclosure, a method of fabricating a memory element is provided. The method includes the steps of: providing a semiconductor substrate defining an active region and including an isolation layer surrounding the active region; forming a first recess extending into the semiconductor substrate and through the active region; forming a first liner portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first liner portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer surrounding the first conductive member; and forming a first protruding portion of the first insulating layer over the first conductive layer and the first conductive member.

[0162] In summary, since the insulating layer of the word line surrounding the work function member has a greater thickness compared to the insulating layer surrounding the conductive member under the work function member, gate induced drain leakage current (GIDL) can be suppressed. In addition, the insulating layer surrounding the conductive member has a smaller thickness, so operation control of the word line can be improved. Therefore, performance of the memory element and the fabrication process of the memory element are improved. While the present disclosure and the best mode thereof have been described in detail herein, it should be understood that the inventive concepts described herein can be varied greatly without departing from the spirit or scope of the disclosure. Numerous variations, substitutions, and changes can be made without departing from the spirit or scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented differently, and many of the described processes can be implemented using different methodologies or in different orders or sequences, or in combination with other processes or steps not expressly described above.

[0163] Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure is open to equivalents and substitutions without departing from the scope of the disclosure. It is expressly intended that all combinations of those elements that are described by the word "comprising" or variations such as "comprise", "comprises", "including", "includes", "includes", "include", and "contains" be within the scope of the disclosure.

Claims

1. A method for fabricating a memory element, comprising: providing a semiconductor substrate defining an active region and including an isolation layer surrounding the active region; forming a first recess extending into the semiconductor substrate and through the active region; forming a first liner portion of a first insulating layer conformal to the first recess; conformally disposing a first conductive material to the first liner portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer surrounding the first conductive member; forming a first overhang portion of the first insulating layer over the first conductive layer and the first conductive member; and removing a portion of the first conductive material disposed over the first conductive member after disposing the second conductive material.

2. The method of claim 1, wherein the forming of the first liner portion is performed prior to the forming of the first overhang portion.

3. The method of claim 1, wherein the forming of the first overhang portion includes disposing an insulating material over the semiconductor substrate, the first liner portion, the first conductive layer, and the first conductive member.

4. The method of claim 3, wherein the insulating material is disposed by atomic layer deposition.

5. The method of claim 3, wherein the forming of the first overhang portion includes removing a portion of the insulating material disposed over the semiconductor substrate and the first liner portion.

6. The method of claim 5, wherein the portion of the insulating material is removed by anisotropic etching.

7. The method of claim 1, further comprising: forming a second recess extending into the isolation layer to form a second liner portion of an isolation structure; forming a second conductive layer surrounded by the second liner portion; forming a second conductive member surrounded by the second conductive layer; and forming a second overhang portion of the isolation structure over the second conductive layer and the second conductive member.

8. The method of claim 7, wherein the first overhang portion and the second overhang portion are formed simultaneously.

9. The method of claim 1, further comprising: forming a first work function member over the first conductive layer and surrounded by the first overhang portion; and forming a first gate insulating member over the first work function member and surrounded by the first overhang portion.

10. The method of claim 1, wherein the first insulating layer includes an oxide.

11. The method of claim 1, wherein the first conductive layer includes titanium nitride (TiN).

12. The method of claim 1, wherein the first conductive member includes tungsten (W).

13. The method of claim 1, wherein a word line includes a first work function member disposed over the first conductive layer and the first conductive member, and a first gate insulating member disposed over the first work function member.

14. The method of claim 13, wherein the first work function member and the first gate insulating member are surrounded by the first insulating layer. ​ ​ ​ 15. The method of claim 13, wherein the first work function member and the first gate insulating member are in contact with the first protrusion.

16. The method of claim 13, wherein a total width of the first conductive layer and the first conductive member is substantially equal to a total width of the first protrusion and the first work function member.

17. The method of claim 13, wherein a total width of the first conductive layer and the first conductive member is substantially equal to a total width of the first protrusion and the first gate insulating member.

18. The method of claim 13, wherein the first work function member comprises a polysilicon.

19. The method of claim 13, wherein the first gate insulating member comprises a nitride.

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