An NVMe controller and initialization, data read-write method thereof

Abstract

The application discloses an NVMe controller, a user API interface provides a custom interface for operating the NVMe controller, and after being called, a custom instruction encapsulated in the custom interface is stored in a user command queue; queue processing logic checks and maintains the command state of each slot of the user command queue in real time, and according to the command type, is transferred into NVMe command processing logic or custom command processing logic for standardized processing; the NVMe command processing logic controls DMA transmission logic, write data buffer control, read data buffer control, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine and PCIe receiving engine according to the specific requirements of NVMe standard commands to complete initialization, data reading and data writing. The application reduces the interaction frequency between a user program and the NVMe controller, and maximizes the performance of the NVMe protocol.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a logic-based NVMe controller and its initialization and data read / write methods. Background Technology

[0002] NVMe protocol dedicated solid-state storage media can fully leverage the advantages of solid-state storage media such as high performance, low power consumption, and high concurrency. NVMe protocol-based solid-state electronic disks (SSDs) are widely used in high-speed data acquisition and storage systems, and a single NVMe electronic disk has broken through the continuous sequential read and write bandwidth of no less than 2GB / s.

[0003] Generally, the NVMe protocol is carried over the PCIe interface. Most processors support PCIe controllers, and solid-state drives supporting the NVMe protocol are connected to the PCIe interface. The NVMe protocol functionality is implemented in software on the processor. This method offers high flexibility and versatility, achieving high-performance data access without additional hardware changes. However, it consumes certain processor resources and is suitable for scenarios with low performance requirements and insensitive data transmission latency.

[0004] To free up processor resources and further improve NVMe protocol processing efficiency, the NVMe protocol is typically implemented through logic. FPGA logic completes the instruction processing flow according to the NVMe standard protocol specification. Logic processing of the NVMe protocol is extremely efficient and does not require deep processor involvement. Summary of the Invention

[0005] The purpose of this invention is to provide an NVMe controller, which is implemented through logic and encapsulates a set of custom instructions, allowing users to directly perform data read and write operations on NVMe solid-state drives. The invention also provides an initialization method for the NVMe controller, simplifying the interaction between the user program and the NVMe controller during NVMe device initialization; and a data read and write method for the NVMe controller, which automatically analyzes user-issued I / O read and write operations and performs functions such as transmission address conversion and protocol packet assembly through logic, greatly simplifying data read and write operations and improving protocol processing efficiency. This invention can significantly improve NVMe protocol processing efficiency, reduce the frequency of interaction between the user program and the NVMe controller, reduce resource and time consumption during protocol processing, and maximize NVMe protocol performance.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] An NVMe controller includes a user API interface, a data cache space, a user command queue, queue processing logic, custom command processing logic, DMA transfer logic, write data buffer control logic, read data buffer control logic, NVMe command processing logic, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine, PCIe receiving engine, and command execution status queue.

[0008] The user API interface provides a custom interface for operating this NVMe controller. The custom interface encapsulates custom commands built in a specific format, including power-on interface, power-off interface, read data interface, and write data interface.

[0009] The user command queue contains several slots to store custom commands encapsulated in the called user API interfaces;

[0010] The queue processing logic checks and maintains the command status of each slot in the user command queue in real time. Once it detects that a new custom command has been written to a slot in the user command queue, it retrieves the custom command from that slot. If it is a write data command or read data command, it is transferred to the NVMe command processing logic for further processing; if it is a power-on command or power-off command, it is transferred to the custom command processing logic for processing.

[0011] The custom command processing logic is used to parse custom commands, converting them into one or more standard NVMe commands defined by the standard specification. The parsed NVMe standard commands will then be transferred to the NVMe command processing logic.

[0012] After receiving a custom command from the queue processing logic, the NVMe command processing logic parses the command content and constructs an NVMe standard command. Based on the specific requirements of the NVMe standard command, it controls the DMA transfer logic, write data buffer control, read data buffer control, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine, PCIe receiving engine initialization, data reading, and data writing.

[0013] Preferably, the data cache space is a cache space during data transmission, including but not limited to DDR and SRAM; the data cache space is connected to the DMA transfer logic in the controller through an AXI or PCIe bus, and the DMA transfer logic completes the data transfer.

[0014] Preferably, the write data buffer control and read data buffer control are logic control modules composed of FIFO and BRAM, used for data buffer synchronization between different buses.

[0015] Preferably, the write data PRP cache and the read data PRP cache are used to store the data cache addresses during write and read data transmissions in accordance with the Parallel Redundancy Protocol (PRP).

[0016] Preferably, the NVMe command send queue and the NVMe command completion queue are used to store send commands and completion commands defined in the NVMe specification.

[0017] Preferably, the PCIe transmit engine and PCIe receive engine are PCIe transmit and receive control logic that completes the writing of data to the NVMe electronic disk and the reading of data from the NVMe electronic disk.

[0018] Preferably, the command execution status queue is a set of caches built using the FPGA's internal RAM resources, and each slot in the command execution status queue stores the status information of the completion of the command execution corresponding to the slot in the user command queue.

[0019] The initialization method for the above NVMe controller consists of the following steps:

[0020] Step A1: After power-on, the upper-layer application checks the link status register of the NVMe controller to determine whether the current NVMe controller has established a connection with the NVMe disk; if a connection is established, proceed to step A2; otherwise, continue polling and checking the link status register until timeout, then end the initialization and proceed to step A5.

[0021] Step A2: Call the boot interface in the user API interface, write the boot command encapsulated in the boot interface into the user command queue, and perform NVMe controller initialization;

[0022] Step A3: The queue processing logic monitors the user command queue in real time, extracts the boot command, and then transfers the boot command to the custom command processing logic. The custom command processing logic parses the boot command, breaks it down into several NVMe standard commands, transfers them to the NVMe command processing logic for processing, fills them into the NVMe command sending queue, and sends them to the NVMe electronic disk.

[0023] Step A4: The upper layer monitors the initialization status register of the NVMe controller and judges the initialization result. If successful, the attribute information of the mounted NVMe electronic disk is obtained according to the NVMe controller register information and the Identify information in the data receiving RAM. If the timeout occurs, the initialization fails and proceeds to step A5.

[0024] Step A5: NVMe controller initialization complete.

[0025] The steps for reading data from the above NVMe controller are as follows:

[0026] Step B1: The upper-layer application calls the read data interface in the user API interface to perform data reading operations. The read data interface constructs a read data command based on the starting sector number, the number of sectors in this transmission, and the data cache address passed by the application and writes it to the free slot in the user command queue; where the data cache address points to the data cache area in the data cache space.

[0027] Step B2: The queue processing logic checks and maintains the status of each slot in the user command queue in real time. Once it is detected that a read data command has been written to a slot in the user command queue, the read data command is retrieved and handed over to the NVMe command processing logic. At the same time, the status of the slot is set to active.

[0028] Step B3: The NVMe command processing logic parses the parameters in the read operation command, constructs a standard NVMe I / O read command based on the data cache address passed in the read data command; the PRP in the NVMe I / O read command uses the read data PRP cache to store the data read address, writes the NVMe I / O read command into the NVMe command sending queue, and writes to the doorbell register of the NVMe electronic disk;

[0029] Step B4: After receiving the door bell update operation, the NVMe electronic disk obtains the NVMe I / O read command from the NVMe command sending queue and sends a memory read request to the NVMe command processing logic;

[0030] Step B5: After receiving the memory read request, the NVMe command processing logic sends the read return to the PCIe receiving engine within 10 clock cycles. The received data is written to the data buffer space by the DMA transfer logic after passing through the read data buffer control.

[0031] Step B6: The PCIe receiving engine receives the command completion status information sent by the NVMe electronic disk and writes it into the NVMe command completion queue;

[0032] Step B7: The NVMe command processing logic monitors the command completion status of each slot in the NVMe command completion queue in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic.

[0033] Step B8: The queue processing logic updates the status of the command in the slot corresponding to this command to complete or abnormal based on the command completion status, and at the same time updates the corresponding command status information in the command execution status queue.

[0034] Step B9: The upper-layer application determines the execution result of this operation based on the completion status of this read command. If the completion status is normal, the read command is completed. If the completion status is abnormal, the reason can be analyzed based on the command status of the corresponding slot in the command execution status queue.

[0035] The steps for writing data to the above NVMe controller are as follows:

[0036] Step C1: The upper-layer application calls the write data interface in the user API to perform a data write operation. The write data interface constructs a write data command based on the starting sector number, the number of sectors to be transferred, and the data cache address passed by the application, and writes it to the free slot in the user command queue. The data cache address points to the data cache area in the data cache space.

[0037] Step C2: The queue processing logic checks and maintains the status of each slot in the user command queue in real time. Once it is detected that a write data command has been written to a slot in the user command queue, the write data command is retrieved and handed over to the NVMe command processing logic. At the same time, the status of the slot is set to active.

[0038] Step C3: The NVMe command processing logic parses the parameters in the write operation command, constructs a standard NVMe I / O write command based on the data cache address passed in the write data instruction; the PRP in the NVMe I / O write command uses the write data PRP cache to store the data write address, writes the NVMe I / O write data instruction into the NVMe command sending queue, and writes the door bell register of the NVMe electronic disk.

[0039] Step C4: After receiving the door bell update operation, the NVMe electronic disk obtains the NVMe I / O write command from the NVMe command sending queue and sends a memory read request to the NVMe command processing logic;

[0040] Step C5: After receiving the memory read request, the NVMe command processing logic sends the read return to the PCIe send engine within 10 clock cycles and starts the DMA transfer logic to retrieve the data from the data cache space. After passing through the write data buffer control, the data is sent out by the PCIe send engine.

[0041] Step C6: The PCIe receiving engine receives the command completion status information sent by the SSD and writes it to the NVMe command completion queue;

[0042] Step C7: The NVMe command processing logic monitors the command completion status of each slot in the NVMe command completion queue in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic.

[0043] Step C8: The queue processing logic updates the status of the command corresponding to the slot of this command to complete or abnormal based on the command completion status, and at the same time updates the corresponding command status information in the command execution status queue.

[0044] Step C9: Determine the execution result of this operation based on the completion status of this write command. If the completion status is normal, the write command has been executed. If the completion status is abnormal, analyze the reason based on the command status of the corresponding slot in the command execution status queue.

[0045] The beneficial effects of this invention are as follows:

[0046] This invention utilizes FPGA to implement the NVMe host controller logic, handling the parsing, packet assembly, and processing of NVMe protocol commands entirely within the logic. This reduces processor resource consumption and significantly improves NVMe protocol processing efficiency. The NVMe command send / receive queues and PRP linked list space are constructed using internal logic resources, achieving ultra-low and deterministic latency access. Command completion status detection is achieved through real-time polling of the status of each slot in the completion queue, avoiding the traditional NVMe protocol method of waiting for a completion queue interrupt signal, then checking the tail pointer of the completion queue and sequentially reading elements. This avoids context switching caused by interrupts, effectively improving command completion processing efficiency. Encapsulated custom instructions greatly simplify the user's operation of the NVMe electronic disk; users only need to focus on data read / write results, reducing NVMe protocol maintenance costs. This invention is applicable to data access devices that require high performance and low latency, reducing the difficulty of NVMe function development and simplifying the development process, significantly improving NVMe protocol processing efficiency. Attached Figure Description

[0047] Figure 1 This is a diagram showing the internal module structure of the NVMe controller of this invention.

[0048] Figure 2 This is the NVMe controller initialization flowchart of the present invention.

[0049] Figure 3 This is a flowchart of the NVMe data read / write process of this invention. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0051] See Figure 1As shown in the figure, the NVMe controller shown in this embodiment includes a user API interface 201, a data cache space 202, a user command queue 101, a queue processing logic 102, a custom command processing logic 103, a DMA transfer logic 104, a write data buffer control logic 105, a read data buffer control logic 106, an NVMe command processing logic 107, a write data PRP cache 108, a read data PRP cache 109, an NVMe command sending queue 110, an NVMe command completion queue 111, a PCIe sending engine 112, a PCIe receiving engine 113, a command execution status queue 114, a data transceiver RAM 115, and a data receiving RAM 116.

[0052] User API interface 201 provides a custom interface for operating this NVMe controller. This custom interface encapsulates custom commands built in a specific format, including a power-on interface, a power-off interface, a read data interface, a write data interface, a read information interface, and a write information interface. The power-on interface encapsulates the power-on command to complete controller initialization and NVMe disk mounting; the power-off interface encapsulates the power-off command to complete disk unloading and logical resource reset; the read data interface encapsulates the read data command to complete NVMe disk data reading; the write data interface encapsulates the write data command to complete NVMe disk data writing; the read information interface encapsulates log read command, ID read command, feature read command, and dataset management command to complete NVMe log and feature information reading; and the write information interface encapsulates feature setting command to complete NVMe feature information setting.

[0053] The data cache space 202 is a cache space for data transmission, including but not limited to DDR and SRAM. This data cache space is connected to the DMA transfer logic 104 in the controller via an AXI or PCIe bus, and the DMA transfer logic 104 completes the data transfer.

[0054] Modules 101 to 113 are all logic implementations and are the core processing part of the controller.

[0055] User command queue 101 is a set of cache spaces located inside the FPGA, storing custom commands encapsulated in the called user API interface. The depth of user command queue 101 can be configured as needed according to logic resources, with a default depth of 64. The user command queue is connected end to end to form a ring structure. Each slot in the user command queue can store a 64-byte custom instruction. When the upper-layer application calls the user API interface, the corresponding slot is automatically filled. Each slot is represented by a corresponding status identifier indicating the execution status of the custom command in that slot, including idle, active, completed, and abnormal.

[0056] The queue processing logic 102 checks and maintains the command status of each slot in the user command queue in real time. Once it detects that a new custom command has been written to a slot in the user command queue 101, it retrieves the command from that slot and forwards it to the custom command processing logic 103 or the NVMe command processing logic 107 according to the custom command type. At the same time, it sets the status of the slot to active. The queue processing logic 102 can retrieve multiple pending commands from the user command queue at once.

[0057] Typically, the acquired write data command, read data command, write information command, and read information command are transferred to the NVMe command processing logic 107 for further processing; the power-on command and power-off command are transferred to the custom command processing logic 103 for processing.

[0058] Custom command processing logic 103 is used for custom command parsing, which parses the custom command into one or more standard NVMe commands defined by the standard specification, such as the boot command to complete the NVMe protocol initialization process, which implements NVMe standard commands such as Identify and Get / Set Feature step by step; the parsed NVMe standard commands will be transferred to NVMe command processing logic 107.

[0059] After receiving the custom command sent by the queue processing logic 102, the NVMe command processing logic 107 parses the command content and constructs the NVMe standard command. According to the specific requirements of the NVMe standard command, it controls the DMA transfer logic 104, write data buffer control 105, read data buffer control 106, write data PRP cache 108, read data PRP cache 109, NVMe command sending queue 110, NVMe command completion queue 111, and PCIe sending engine 112 and PCIe receiving engine 113 to complete initialization, data reading, data writing and other operations.

[0060] The DMA transfer logic 104 is used for NVMe data transfer and is the controller's data transfer engine. It connects to the data cache space 202 via an AXI or PCIe bus. When a user performs a data write operation, the DMA transfer logic sends the data in the corresponding address segment of the data cache space 202 to the NVMe disk via the PCIe send engine 112 after passing through the write data buffer control 105. When a user performs a data read operation, the data received by the PCIe receive engine 113 is moved to the corresponding read address segment space in the data cache space 202 via the DMA transfer logic after passing through the read data buffer control 106. The DMA transfer logic 104 is controlled and started by the NVMe command processing logic 107.

[0061] The write data buffer control 105 and read data buffer control 106 are logic control modules composed of FIFO and BRAM, used for data buffer synchronization between different buses to achieve low latency and deterministic access latency when transmitting data between different buses.

[0062] The write data PRP cache 108 and the read data PRP cache 109 are used to store the data cache addresses during write and read data transmissions in accordance with the Parallel Redundancy Protocol (PRP).

[0063] NVMe command sending queue 110 and NVMe command completion queue 111 are a pair of NVMe command sending and receiving queues used to store sending commands or completion commands defined in the NVMe specification.

[0064] PCIe transmit engine 112 and PCIe receive engine 113 are PCIe transmit and receive control logic, which completes the writing of data to the NVMe electronic disk and the reading of data from the NVMe electronic disk.

[0065] The NVMe command processing logic 107 is used to process the NVMe command sending queue 110 and the NVMe command completion queue 111, organizing command frames or parsing command execution status according to the command type. When writing or reading data, the NVMe command processing logic 107 organizes NVMe command frames to be written to the NVMe command sending queue 110 according to the command transferred from the queue processing logic 102, updates the write data PRP address to the write data PRP cache 108 or updates the read data PRP address to the read data PRP cache 109, and starts the DMA transfer logic 104 and the PCIe sending engine 112 to send data or the PCIe receiving engine 113 to receive data.

[0066] The NVMe command processing logic 107 polls and checks the status of the NVMe command completion queue 111 in real time. The PCIe receiving engine 113 sends the command execution result to the NVMe command completion queue 111. When the NVMe command processing logic 107 detects that a command has been executed, it automatically parses the command completion status and updates the result to the command execution status queue 114 through the queue processing logic 102.

[0067] Command execution status queue 114 is a set of caches built using the FPGA's internal RAM resources, with a default depth of 64. Each slot in the command execution status queue stores the status information of the corresponding slot in the user command queue after the command execution is completed, with each completion message being 16 bytes.

[0068] The data transceiver RAM 115 and the data receive RAM 116 are buffer areas composed of BRAM, with a size of 1~4KB, used to store data when management instructions for data transmission are executed.

[0069] like Figure 2 As shown, the initialization method for the NVMe controller provided in this embodiment includes the following steps:

[0070] Step A1: After power-on, the upper-layer application checks the link status register of the NVMe controller to determine whether the current NVMe controller has established a connection with the NVMe electronic disk; if a connection is established, proceed to step A2; otherwise, continue to poll and check the link status register until timeout, then end the initialization and proceed to step A5.

[0071] Step A2: Call the power-on interface in the user API interface 201, write the power-on command encapsulated in the power-on interface into the user command queue 101, and perform NVMe controller initialization.

[0072] Step A3: Queue processing logic 102 detects user command queue 101 in real time, extracts the boot command, and then transfers the boot command to custom command processing logic 103; custom command processing logic 103 parses the boot command, splits it into several NVMe standard commands, transfers them to NVMe command processing logic 107 for processing, fills them into NVMe command sending queue 110, and sends them to the NVMe electronic disk.

[0073] Step A4: The upper layer monitors the initialization status register of the NVMe controller and judges the initialization result. If successful, the attribute information of the mounted NVMe electronic disk is obtained according to the NVMe controller register information and the Identify information in the data receiving RAM. If the timeout occurs, the initialization fails and proceeds to step A5.

[0074] Step A5: NVMe controller initialization complete.

[0075] like Figure 3 As shown, the NVMe controller data reading method provided in this embodiment includes the following steps:

[0076] Step B1: The upper-layer application calls the read data interface in user API interface 201 to perform a data reading operation. The read data interface constructs a read data command based on the parameters passed by the application, such as the starting sector number, the number of sectors to be transferred, and the data cache address, and writes it to the free slot in user command queue 101. The data cache address points to the data cache area in data cache space 202.

[0077] Step B2: The queue processing logic 102 checks and maintains the status of each slot in the user command queue 101 in real time. Once it is detected that a read data command has been written to a slot in the user command queue 101, the read data command is retrieved and handed over to the NVMe command processing logic 107, and the status of the slot is set to active.

[0078] Step B3: NVMe command processing logic 107 parses the parameters in the read operation command, constructs a standard NVMe I / O read command based on the data cache address passed in the read data instruction; the PRP in the NVMe I / O read command uses the read data PRP cache 109 to store the data read address, writes the NVMe I / O read command into the NVMe command sending queue 110, and writes to the door bell register of the solid-state electronic disk SSD to trigger a PCIe bus memory read request.

[0079] Step B4: After receiving the door bell update operation, the SSD obtains the NVMe I / O read command from the NVMe command sending queue 110 and sends a memory read request to the NVMe command processing logic 107.

[0080] Step B5: After receiving the memory read request, the NVMe command processing logic 107 sends the read return to the PCIe receiver engine 113 within 10 clock cycles. The received data is written to the data buffer space 202 by the DMA transfer logic 104 after passing through the read data buffer control 106.

[0081] Step B6: The PCIe receiving engine receives the command completion status information sent by the SSD and writes it into the NVMe command completion queue 111.

[0082] Step B7: NVMe command processing logic 107 monitors the command completion status in each slot of the NVMe command completion queue 111 in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic 102.

[0083] Step B8: Queue processing logic 102 updates the status of the command corresponding to the slot of this command to complete or abnormal according to the command completion status, and at the same time updates the corresponding command status information in the command execution status queue 114.

[0084] Step B9: The upper-layer application determines the execution result of this operation based on the completion status of this read command. If the completion status is normal, the read command is completed. If the completion status is abnormal, the reason can be analyzed based on the command status of the corresponding slot in command execution status queue 114.

[0085] The data writing method for the NVMe controller provided in this embodiment is similar to the data reading method, and the steps are as follows:

[0086] Step C1: The upper-layer application calls the write data interface in user API interface 201 to perform a data write operation. The write data interface constructs a write data command based on the parameters passed by the application, such as the starting sector number, the number of sectors to be transferred, and the data cache address, and writes it to the free slot in the user command queue 101. The data cache address points to the data cache area in the data cache space 202.

[0087] Step C2: The queue processing logic 102 checks and maintains the status of each slot in the user command queue 101 in real time. Once it is detected that a write data command has been written to a slot in the user command queue 101, the write data command is retrieved and handed over to the NVMe command processing logic 107, and the status of the slot is set to active.

[0088] Step C3: NVMe command processing logic 107 parses the parameters in the write operation command, constructs a standard NVMe I / O write command based on the data cache address passed in the write data instruction; the PRP in the NVMe I / O write command uses the write data PRP cache 108 to store the data write address, writes the NVMe I / O write data instruction into the NVMe command sending queue 110, and writes to the SSD-side door bell register to trigger a PCIe bus memory write request.

[0089] Step C4: After receiving the door bell update operation, the SSD obtains the NVMe I / O write command from the NVMe command sending queue 110 and sends a memory read request to the NVMe command processing logic 107.

[0090] Step C5: After receiving the memory read request, the NVMe command processing logic 107 sends the read return to the PCIe send engine 112 within 10 clock cycles and starts the DMA transfer logic to retrieve the data from the data cache space 202. After passing through the write data buffer control 105, the data is sent out by the PCIe send engine 112.

[0091] Step C6: The PCIe receiving engine receives the command completion status information sent by the SSD and writes it into the NVMe command completion queue 111.

[0092] Step C7: NVMe command processing logic 107 monitors the command completion status in each slot of the NVMe command completion queue 111 in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic 102.

[0093] Step C8: Queue processing logic 102 updates the status of the command corresponding to the slot of this command to complete or abnormal according to the command completion status, and at the same time updates the corresponding command status information in the command execution status queue 114.

[0094] Step C9: The user determines the result of this operation based on the completion status of this write command. If the completion status is normal, the write command is completed. If the completion status is abnormal, the reason can be analyzed based on the command status of the corresponding slot in the command execution status queue 114.

[0095] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. An NVMe controller, comprising a user API interface, a data cache space, a user command queue, queue processing logic, custom command processing logic, DMA transfer logic, write data buffer control logic, read data buffer control logic, NVMe command processing logic, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine, PCIe receiving engine, and command execution status queue, characterized in that: The user API interface provides a custom interface for operating this NVMe controller. The custom interface encapsulates custom commands, including power-on interface, power-off interface, read data interface, and write data interface. The user command queue contains several slots to store custom commands encapsulated in the called user API interfaces; The queue processing logic checks and maintains the command status of each slot in the user command queue in real time. Once it detects that a new custom command has been written to a slot in the user command queue, it retrieves the custom command from that slot. If it is a write data command or read data command, it is transferred to the NVMe command processing logic for further processing; if it is a power-on command or power-off command, it is transferred to the custom command processing logic for processing. The custom command processing logic is used to parse custom commands, converting them into one or more standard NVMe commands defined by the standard specification. The parsed NVMe standard commands will then be transferred to the NVMe command processing logic. After receiving a custom command from the queue processing logic, the NVMe command processing logic parses the command content and constructs an NVMe standard command. Based on the specific requirements of the NVMe standard command, it controls the DMA transfer logic, write data buffer control, read data buffer control, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine, PCIe receiving engine initialization, data reading, and data writing. The steps for reading data are as follows: Step B1: The upper-layer application calls the read data interface in the user API interface to perform data reading operations. The read data interface constructs a read data command based on the starting sector number, the number of sectors in this transmission, and the data cache address passed by the application and writes it to the free slot in the user command queue; where the data cache address points to the data cache area in the data cache space. Step B2: The queue processing logic checks and maintains the status of each slot in the user command queue in real time. Once it is detected that a read data command has been written to a slot in the user command queue, the read data command is retrieved and handed over to the NVMe command processing logic. At the same time, the status of the slot is set to active. Step B3: The NVMe command processing logic parses the parameters in the read operation command, constructs a standard NVMe I / O read command based on the data cache address passed in the read data command; the PRP in the NVMe I / O read command uses the read data PRP cache to store the data read address, writes the NVMe I / O read command into the NVMe command sending queue, and writes the door bell register of the NVMe electronic disk. Step B4: After receiving the door bell update operation, the NVMe electronic disk obtains the NVMe I / O read command from the NVMe command sending queue and sends a memory read request to the NVMe command processing logic; Step B5: After receiving the memory read request, the NVMe command processing logic sends the read return to the PCIe receiving engine within 10 clock cycles. The received data is written to the data buffer space by the DMA transfer logic after passing through the read data buffer control. Step B6: The PCIe receiving engine receives the command completion status information sent by the NVMe electronic disk and writes it into the NVMe command completion queue; Step B7: The NVMe command processing logic monitors the command completion status of each slot in the NVMe command completion queue in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic. Step B8: The queue processing logic updates the status of the command in the slot corresponding to this command to complete or abnormal based on the command completion status, and at the same time updates the corresponding command status information in the command execution status queue. Step B9: The upper-layer application determines the execution result of this operation based on the completion status of this read command. If the completion status is normal, the read command is completed. If the completion status is abnormal, the reason can be analyzed based on the command status of the corresponding slot in the command execution status queue.

2. An NVMe controller according to claim 1, characterized in that... The data cache space is the cache space during data transmission, including but not limited to DDR and SRAM; this data cache space is connected to the DMA transfer logic in the controller through the AXI or PCIe bus, and the DMA transfer logic completes the data transfer.

3. An NVMe controller according to claim 1, characterized in that... The write data buffer control and read data buffer control are logic control modules composed of FIFO and BRAM, used for data buffer synchronization between different buses.

4. An NVMe controller according to claim 1, characterized in that... The write data PRP cache and read data PRP cache are used to store the data cache addresses during write and read data transmissions in accordance with the Parallel Redundancy Protocol (PRP).

5. An NVMe controller according to claim 1, characterized in that... The NVMe command send queue and NVMe command completion queue are used to store send commands and completion commands defined in the NVMe specification.

6. An NVMe controller according to claim 1, characterized in that... The PCIe transmit engine and PCIe receive engine are the PCIe transmit and receive control logic, which completes the writing of data to the NVMe electronic disk and the reading of data from the NVMe electronic disk.

7. An NVMe controller according to claim 1, characterized in that... The command execution status queue is a set of caches built using the FPGA's internal RAM resources. Each slot in the command execution status queue stores the status information of the completion of the command execution corresponding to the slot in the user command queue.

8. An NVMe controller according to claim 1, characterized in that... The initialization steps are as follows: Step A1: After power-on, the upper-layer application checks the link status register of the NVMe controller to determine whether the current NVMe controller has established a connection with the NVMe disk; if a connection is established, proceed to step A2; otherwise, continue polling and checking the link status register until timeout, then end the initialization and proceed to step A5. Step A2: Call the boot interface in the user API interface, write the boot command encapsulated in the boot interface into the user command queue, and perform NVMe controller initialization; Step A3: The queue processing logic monitors the user command queue in real time, extracts the boot command, and then transfers the boot command to the custom command processing logic. The custom command processing logic parses the boot command, breaks it down into several NVMe standard commands, transfers them to the NVMe command processing logic for processing, fills them into the NVMe command sending queue, and sends them to the NVMe electronic disk. Step A4: The upper layer monitors the initialization status register of the NVMe controller and judges the initialization result. If successful, the attribute information of the mounted NVMe electronic disk is obtained according to the NVMe controller register information and the Identify information in the data receiving RAM. If the timeout occurs, the initialization fails and proceeds to step A5. Step A5: NVMe controller initialization complete.

9. An NVMe controller according to claim 1, characterized in that... The steps for writing data are as follows: Step C1: The upper-layer application calls the write data interface in the user API interface to perform a data writing operation. The write data interface constructs a write data command based on the starting sector number, the number of sectors to be transferred, and the data cache address passed by the application and writes it to the free slot in the user command queue; where the data cache address points to the data cache area in the data cache space. Step C2: The queue processing logic checks and maintains the status of each slot in the user command queue in real time. Once it is detected that a write data command has been written to a slot in the user command queue, the write data command is retrieved and handed over to the NVMe command processing logic. At the same time, the status of the slot is set to active. Step C3: The NVMe command processing logic parses the parameters in the write operation command, constructs a standard NVMe I / O write command based on the data cache address passed in the write data instruction; the PRP in the NVMe I / O write instruction uses the write data PRP cache to store the data write address, writes the NVMe I / O write data instruction into the NVMe command sending queue, and writes the doorbell register of the NVMe electronic disk. Step C4: After receiving the door bell update operation, the NVMe electronic disk obtains the NVMe I / O write command from the NVMe command sending queue and sends a memory read request to the NVMe command processing logic; Step C5: After receiving the memory read request, the NVMe command processing logic sends the read return to the PCIe send engine within 10 clock cycles and starts the DMA transfer logic to retrieve the data from the data cache space. After passing through the write data buffer control, the data is sent out by the PCIe send engine. Step C6: The PCIe receiving engine receives the command completion status information sent by the SSD and writes it to the NVMe command completion queue; Step C7: The NVMe command processing logic monitors the command completion status of each slot in the NVMe command completion queue in real time. When a new command completion return status is detected, the command completion status is obtained, parsed, and then sent to the queue processing logic. Step C8: The queue processing logic updates the status of the command corresponding to the slot of this command to complete or abnormal based on the command completion status, and at the same time updates the corresponding command status information in the command execution status queue. Step C9: Determine the execution result of this operation based on the completion status of this write command. If the completion status is normal, the write command has been executed. If the completion status is abnormal, analyze the reason based on the command status of the corresponding slot in the command execution status queue.

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