A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate, forming a trench extending from a first surface of the substrate to an interior of the substrate, forming a shielding dielectric layer at a bottom and a part of a sidewall of the trench, and forming a shielding gate in the trench. The shielding gate fills a part of the trench, a top surface of the shielding gate is higher than a top surface of the shielding dielectric layer, and a distance from the top surface of the shielding dielectric layer to the first surface is a first depth. A part of the shielding gate is etched to make the top surface of the shielding gate flush with the top surface of the shielding dielectric layer, and a predetermined thickness of the substrate is etched from the first surface to make the distance from the top surface of the shielding dielectric layer to the first surface a second depth. The first depth is greater than the second depth. An inter-gate dielectric layer and a control gate structure are formed in the trench. The method of the application etches a predetermined thickness of the substrate while etching the shielding gate, thereby effectively reducing a high-density plasma filling aspect ratio, and further increasing a filling window and improving a filling effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Shielded gate trenches (SGTs) are widely used in advanced logic circuit processes, and their quality directly affects the performance of devices. For example, shielded gate trenches are used in metal oxide semiconductor field effect transistors (MOSFETs).

[0003] In related technologies, when shielding gate trenches are applied to metal-oxide-semiconductor field-effect transistors (MOSFETs), a trench extending from the first surface of the substrate into the substrate is typically formed first. A shielding dielectric material layer is formed on the bottom, sidewalls, and first surface of the substrate of the trench. A shielding gate of a certain depth is filled into the trench. Part of the shielding dielectric material layer within the trench is removed by etching back to form the shielding dielectric layer, while a portion of the shielding dielectric material layer on the trench sidewalls is retained to prevent damage to the trench sidewalls during etching. After etching back, the top surface of the shielding gate is higher than the top surface of the shielding dielectric layer inside the trench. Because a portion of the shielding dielectric layer is retained on the trench sidewalls, the filling width of the inter-gate dielectric material layer is less than the critical dimension of the trench. Therefore, this leads to an increase in the fill aspect ratio of the inter-gate dielectric material layer deposition process. An excessively large fill aspect ratio results in insufficient filling windows during the filling of the inter-gate dielectric material layer, making it easy for voids 105 to appear during the filling process. Figure 1C As shown, this can affect the electrical properties of the product and reduce the product yield. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this invention provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided, and a trench is formed extending from a first surface of the substrate into the interior of the substrate. A shielding dielectric layer is formed at the bottom and part of the sidewalls of the trench, and a shielding grid is formed in the trench. The shielding grid fills a portion of the depth of the trench, and the top surface of the shielding grid is higher than the top surface of the shielding dielectric layer. The distance from the top surface of the shielding dielectric layer to the first surface is a first depth.

[0007] The shielding gate is partially etched away so that the top surface of the shielding gate is flush with the top surface of the shielding dielectric layer, and a substrate of a predetermined thickness is etched away from the first surface so that the distance from the top surface of the shielding dielectric layer to the first surface is a second depth, wherein the first depth is greater than the second depth.

[0008] An inter-gate dielectric layer is formed in the trench, and a control gate structure is formed in the portion of the trench located on the inter-gate dielectric layer.

[0009] Exemplarily, a method for forming the shielding medium layer at the bottom and part of the sidewalls of the trench and forming the shielding grid in the trench includes:

[0010] A shielding dielectric material layer is formed at the bottom of the trench, on the sidewalls, and on the first surface of the substrate;

[0011] The shielding grid is formed to fill a portion of the depth of the trench;

[0012] Etching removes a portion of the shielding dielectric material layer on the sidewall of the trench and exposes a portion of the sidewall of the trench, while simultaneously etching removes the shielding dielectric material layer on the first surface, forming the shielding dielectric layer.

[0013] For example, a wet etching process is used to etch away a portion of the shielding dielectric layer on the trench sidewall and to etch away the shielding dielectric layer on the first surface.

[0014] For example, a dry etching process is used to etch away a portion of the shielding gate and the substrate of a predetermined thickness.

[0015] For example, the distance between the sidewalls above the shielding grid where the trench is located is a first width, and the ratio of the second depth to the first width is less than 2.5.

[0016] For example, the predetermined thickness ranges from 0.1 μm to 0.3 μm.

[0017] For example, the second depth ranges from 0.7 μm to 1.3 μm.

[0018] Exemplarily, a method for forming the inter-gate dielectric layer and the control gate structure includes:

[0019] An inter-gate dielectric material layer is deposited within the trench and on the first surface of the substrate;

[0020] The inter-gate dielectric material layer on the first surface is planarized.

[0021] The inter-gate dielectric material layer within the trench is etched back to form an inter-gate dielectric layer within the trench;

[0022] The control gate structure is formed on the portion of the trench located on the inter-gate dielectric layer.

[0023] In another aspect, the present invention provides a semiconductor device manufactured using the method described above.

[0024] The semiconductor device and its fabrication method according to embodiments of the present invention reduce the trench filling depth by etching away a predetermined thickness of substrate from the first surface of the substrate while etching away part of the shielding gate. This effectively reduces the filling aspect ratio of the inter-gate dielectric material layer, thereby increasing the filling window, reducing the occurrence of filling voids, improving the filling effect, and enhancing the device's electrical properties and yield. Attached Figure Description

[0025] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0026] In the attached image:

[0027] Figure 1A-1B A schematic cross-sectional view of a semiconductor device obtained by implementing a conventional semiconductor device fabrication method is shown.

[0028] Figure 1C A schematic diagram of the morphology of voids produced by an existing semiconductor device fabrication method is shown.

[0029] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown;

[0030] Figures 3A-3E The diagram shows a cross-sectional schematic of a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of the present invention. Detailed Implementation

[0031] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0037] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0038] When shielded gate trenches are applied to metal-oxide-semiconductor field-effect transistors, the following fabrication processes are typically employed: (e.g.) Figure 1AAs shown, a trench 102 is formed in a substrate 100. A shielding dielectric material layer is formed on the sidewalls, bottom, and first surface of the substrate 100 of the trench 102. A shielding gate 103 is partially filled in the trench 102. A portion of the shielding dielectric material layer is removed by etching back to form a shielding dielectric layer 101. A portion of the shielding dielectric material layer on the sidewalls of the trench is retained to prevent the etching from damaging the sidewalls of the trench. The etching back also makes the thickness of the shielding dielectric layer 101 on the upper sidewall of the trench 102 less than the thickness of the shielding dielectric layer 101 on the lower sidewall adjacent to the shielding gate 103. The top surface of the shielding gate 103 is higher than the top surface of the shielding dielectric layer 101 inside the trench 102. At this time, the distance between the sidewalls inside the trench 102 above the shielding gate 103 is W0 (that is, the distance between the opposing shielding dielectric layers 101 on the sidewalls of the trench 102 above the shielding gate 103), and the distance between the top surface of the shielding dielectric layer 101 inside the trench 102 and the top surface of the shielding dielectric layer 101 on the first surface of the substrate 100 is L0; subsequently, as Figure 1B As shown, an inter-gate dielectric material layer 104 is deposited to fill the trench 102, for example, by a high-density plasma (HDP) deposition process.

[0039] The inventors of this application discovered that: because back etching causes the top surface of the shielding dielectric layer 101 inside the trench 102 to be lower than the top surface of the shielding gate 103, the filling depth of the inter-gate dielectric material layer increases; and because the shielding dielectric layer 101 is retained on the upper sidewall of the trench 102 before the inter-gate dielectric material layer is deposited, the filling width of the inter-gate dielectric material layer is less than the critical dimension of the trench 102. Therefore, this leads to an increase in the fill aspect ratio of the inter-gate dielectric material layer deposition process. An excessively large fill aspect ratio will result in insufficient filling windows during the filling of the inter-gate dielectric material layer, making it easy for voids 105 to appear during the filling process, such as... Figure 1C As shown, this can affect the electrical properties of the product and reduce the product yield.

[0040] Therefore, in view of the aforementioned technical problems, the present invention proposes a method for fabricating a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:

[0041] Step S1: Provide a substrate, form a trench extending from a first surface of the substrate into the interior of the substrate, form a shielding dielectric layer at the bottom and part of the sidewalls of the trench, and form a shielding gate in the trench, the shielding gate filling a portion of the depth of the trench, the top surface of the shielding gate being higher than the top surface of the shielding dielectric layer, and the distance from the top surface of the shielding dielectric layer to the first surface being a first depth;

[0042] Step S2: Etch away a portion of the shielding gate so that the top surface of the shielding gate is flush with the top surface of the shielding dielectric layer, and etch away a substrate of a predetermined thickness from the first surface so that the distance from the top surface of the shielding dielectric layer to the first surface is a second depth, wherein the first depth is greater than the second depth.

[0043] Step S3: An inter-gate dielectric layer is formed in the trench, and a control gate structure is formed on the portion of the trench located on the inter-gate dielectric layer.

[0044] By etching away part of the shielding gate while simultaneously etching away a substrate of a predetermined thickness from the first surface of the substrate, the filling depth of the trench is reduced, thereby effectively reducing the filling aspect ratio of the inter-gate dielectric material layer, increasing the filling window, reducing the occurrence of filling voids, improving the filling effect, and enhancing the device's electrical properties and yield.

[0045] Example 1

[0046] Below, for reference Figures 2 to 3E The method for fabricating the semiconductor device of the present invention is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown. Figures 3A-3E The diagram shows a cross-sectional schematic of a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of the present invention.

[0047] Exemplarily, the method for fabricating the semiconductor device of the present invention includes the following steps:

[0048] First, step S1 is performed, a substrate is provided, and a trench is formed extending from a first surface of the substrate into the interior of the substrate. A shielding dielectric layer is formed at the bottom and part of the sidewalls of the trench, and a shielding grid is formed in the trench. The shielding grid fills a portion of the depth of the trench, and the top surface of the shielding grid is higher than the top surface of the shielding dielectric layer. The distance from the top surface of the shielding dielectric layer to the first surface is a first depth.

[0049] In some embodiments, the substrate 300 includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Optionally, the semiconductor substrate and the epitaxial layer may have the same conductivity type. In other embodiments, the substrate 300 may also include only a semiconductor substrate without forming an epitaxial layer.

[0050] Specifically, such as Figure 3AAs shown, substrate 300 includes a semiconductor substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the semiconductor substrate may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form a semiconductor substrate have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this invention. Furthermore, substrate 300 may be divided into active regions, and / or doped wells (not shown) may be formed in substrate 300, etc.

[0051] In one example, such as Figure 3A As shown, a trench 302 is formed extending from the first surface of the substrate 300 into the interior of the substrate 300. A shielding dielectric layer 301 is formed at the bottom and part of the sidewalls of the trench 302, and a shielding gate 303 is formed in the trench 302. The shielding gate 303 fills a portion of the depth of the trench 302, and the top surface of the shielding gate 303 is higher than the top surface of the shielding dielectric layer 301. At this time, the distance from the shielding dielectric layer 301 to the first surface of the substrate 300 is a first depth L1, the distance between the sidewalls of the trench 302 above the shielding gate 303 is a first width W1, and the first depth L1 is greater than the first width W1. Figure 1A The distance L0 shown is (i.e., the distance between the top surface of the shielding medium layer on the first surface and the top surface of the shielding medium layer retained in the trench), and the first width W1 is greater than Figure 1A The distance W0 shown (i.e., the distance between the outer surfaces of the opposing shielding dielectric layers within the trench) indicates that as the trench width increases and the depth decreases, the trench depth-to-width ratio decreases. This reduces the depth-to-width ratio of the inter-gate dielectric material deposition process, thereby reducing the occurrence of voids during filling and improving the filling effect.

[0052] Exemplarily, the method of forming a shielding medium layer 301 at the bottom and part of the sidewalls of the trench 302 and forming a shielding grid 303 in the trench 302 includes:

[0053] A shielding dielectric material layer is formed at the bottom, sidewalls, and first surface of the substrate 300 of the trench 302;

[0054] A shielding grid 303 is formed to fill a portion of the depth of the trench 302;

[0055] Etching removes part of the shielding dielectric material layer on the sidewall of trench 302 and exposes part of the sidewall of trench 302. At the same time, etching removes the shielding dielectric material layer on the first surface of substrate 300 to form shielding dielectric layer 301.

[0056] For example, a wet etching process is used to etch away a portion of the shielding dielectric layer 301 on the sidewall of the trench 302 and to etch away the shielding dielectric layer 301 on the first surface of the substrate 300. In this embodiment, the wet etching process etches only the shielding dielectric layer 301 and hardly etches the shielding gate 303 and the substrate 300.

[0057] In one example, the shielding dielectric layer 301 may include a silicon oxide layer, or a stack of silicon oxide and silicon nitride layers, or a stack of two silicon oxide layers with a silicon nitride layer sandwiched in between.

[0058] Exemplarily, the material of the shielding gate 303 includes polycrystalline silicon or other suitable materials. Exemplarily, the polycrystalline silicon can be formed using a low-pressure chemical vapor deposition (LPCVD) process. The process conditions for forming polycrystalline silicon include: the reactant gas is silane (SiH4), the flow rate of which can be in the range of 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature inside the reaction chamber can be in the range of 700-750 degrees Celsius; the pressure inside the reaction chamber can be in the range of 250-350 millimeter-hectares (mTorr), such as 300 mTorr; the reactant gas may also include a buffer gas, which can be helium (He) or nitrogen, and the flow rate of which can be in the range of 5-20 liters per minute (slm), such as 8 slm, 10 slm, or 15 slm.

[0059] Subsequently, step S2 is performed to etch away a portion of the shielding gate so that the top surface of the shielding gate is flush with the top surface of the shielding dielectric layer, and to etch away a predetermined thickness of the substrate from the first surface so that the distance from the top surface of the shielding dielectric layer to the first surface is a second depth, wherein the first depth is greater than the second depth.

[0060] In one example, such as Figure 3B As shown, a portion of the shielding gate 303 is etched away to make the top surface of the shielding gate 303 flush with the top surface of the shielding dielectric layer 301. A predetermined thickness of the substrate 300 is etched away from the first surface of the substrate 300 so that the distance from the top surface of the shielding dielectric layer 301 to the first surface is the second depth L2. Since the predetermined thickness of the substrate 300 is etched away, the second depth L2 is less than the first depth L1, which further reduces the filling depth of the subsequent deposition process. At this time, the distance W2 between the sidewalls of the trench 302 above the shielding gate 303 is equal to the first width W1, and W2 is still greater than W0 mentioned above. Therefore, the aspect ratio of the trench is reduced.

[0061] For example, a dry etching process can be used to etch away part of the shielding gate 303 and the substrate 300 of a predetermined thickness, or other suitable etching processes can be used to etch the shielding gate 303 and the substrate 300.

[0062] For example, the ratio of the second depth L2 to the first width W1 (i.e., the second width W2) is less than 2.5. For example, the ratio of the second depth L2 to the first width W1 can be 2.47, 2.36, 2.25, 2.18, 2.15, 2.1, 2.05, 2.0, etc.

[0063] For example, the predetermined thickness ranges from 0.1μm to 0.3μm. For instance, the predetermined thickness can be 0.1μm, 0.15μm, 0.2μm, 0.25μm, 0.3μm, etc., or it can be other suitable thicknesses.

[0064] For example, the second depth L2 ranges from 0.7μm to 1.3μm. For instance, the second depth L2 can be 0.7μm, 0.8μm, 0.9μm, 0.95μm, 1.0μm, 1.05μm, 1.1μm, 1.2μm, 1.3μm, etc.

[0065] Finally, step S3 is performed to form an inter-gate dielectric layer in the trench and to form a control gate structure on the portion of the trench located on the inter-gate dielectric layer.

[0066] In one example, such as Figure 3C As shown, an inter-gate dielectric material layer 304 is deposited in trench 302. In this embodiment, the inter-gate dielectric material layer 304 is formed using an HDP (high-density plasma) deposition process. In this embodiment, the morphology of the inter-gate dielectric material layer 304 is chamfered due to plasma bombardment, resulting in a triangular shape at the top. In some embodiments, the inter-gate dielectric material layer can also be bombarded with plasma after its formation to adjust its morphology.

[0067] Exemplarily, the inter-gate dielectric material layer 304 includes, but is not limited to, at least one of oxides, nitrides, and oxynitrides, especially oxides, nitrides, and oxynitrides of silicon.

[0068] Optionally, the inter-gate dielectric material layer 304 may fill the trench 302 and cover the first surface of the substrate 300. Alternatively, in some embodiments, the inter-gate dielectric material layer 304 may also partially fill the trench 302, for example, by covering the sidewalls of the trench 302 and covering the shielding gate 303 and the shielding dielectric layer 301.

[0069] Exemplarily, after depositing the inter-gate dielectric material layer 304, the method further includes:

[0070] The inter-gate dielectric material layer 304 on the first surface of the substrate is planarized.

[0071] The inter-gate dielectric material layer 304 in the trench is etched back to form the inter-gate dielectric layer 305 in the trench;

[0072] A control gate structure is formed on the portion of the trench located on the inter-gate dielectric layer 305. The control gate structure includes a gate dielectric layer formed on the sidewalls of the trench and a control gate 306 formed in the trench, as shown below. Figure 3E As shown.

[0073] Optionally, the inter-gate dielectric material layer 304 can be planarized using a chemical mechanical polishing (CMP) process, or other suitable processes can be used.

[0074] For example, such as Figure 3D As shown, the inter-gate dielectric material layer 304 can be etched back using a dry etching process to form the inter-gate dielectric layer 305, or the etch-back process can be performed sequentially using a dry etching process followed by a wet etching process. Optionally, after the etch-back process, the trench sidewalls above the inter-gate dielectric layer 305 and the first surface of the substrate are exposed. To avoid damage to the substrate in subsequent processes, an annealing process can be performed, for example, to form a silicon oxide layer above the sidewalls of the trench 302 above the inter-gate dielectric layer 305 and the first surface of the substrate 300. At the same time, the annealing process can also repair the etching damage caused by the aforementioned etching process.

[0075] For example, the gate dielectric layer can be silicon oxide (SiO2) or silicon oxynitride (SiON). Oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing (RTO), and in-situ steam oxidation (ISSG), can be used to form the silicon oxide gate dielectric layer. A nitriding process can be performed on the silicon oxide to form silicon oxynitride, wherein the nitriding process can be high-temperature furnace tube nitriding, rapid thermal annealing nitriding, or plasma nitriding. Of course, other nitriding processes can also be used, which will not be elaborated here.

[0076] The control gate material may include polycrystalline silicon or other suitable materials, and the polycrystalline silicon can be formed using low-pressure chemical vapor deposition (LPCVD). The process conditions for forming polycrystalline silicon include: the reactant gas is silane (SiH4), the flow rate of which can be 100–200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature inside the reaction chamber can be 700–750 degrees Celsius; the pressure inside the reaction chamber can be 250–350 millimeter-hectare (mTorr), such as 300 mTorr; the reactant gas may also include a buffer gas, which can be helium (He) or nitrogen, and the flow rate of helium and nitrogen can be 5–20 liters per minute (slm), such as 8 slm, 10 slm, or 15 slm.

[0077] This concludes the description of the key steps in the method for fabricating the semiconductor device of the present invention. Other steps may also be included in the fabrication of a complete semiconductor device, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0078] In summary, the fabrication method of this invention reduces the trench filling depth by etching away a predetermined thickness of substrate from the first surface of the substrate while removing part of the shielding gate. This effectively reduces the filling aspect ratio of the inter-gate dielectric material layer, thereby increasing the filling window, reducing the occurrence of filling voids, improving the filling effect, and enhancing the device's electrical properties and yield.

[0079] Example 2

[0080] The present invention also provides a semiconductor device prepared by the method described in Embodiment 1 above. Specifically, the semiconductor device includes a substrate 300, a trench 302 extending from a first surface of the substrate 300 into the interior of the substrate 300, a shielding dielectric layer 301 formed on the bottom and part of the sidewalls of the trench 302, a shielding gate 303 formed in the trench 302, and an inter-gate dielectric layer 305 formed in the trench 302. Since the device of this application is prepared by the aforementioned method, it has the same advantages as the aforementioned method.

[0081] Specifically, such as Figure 3AAs shown, substrate 300 includes a semiconductor substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the semiconductor substrate may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form a semiconductor substrate have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this invention. Furthermore, substrate 300 may be divided into active regions, and / or doped wells (not shown) may be formed in substrate 300, etc.

[0082] The shielding grid 303 fills the groove 302 to a certain depth, and the top of the shielding grid 303 is flush with the top of the shielding medium layer 301. It is worth mentioning that relative to being flush, due to errors in the manufacturing process, this flushness may mean that the height difference between the top of the shielding grid 303 and the top of the shielding medium layer 301 is less than a predetermined height, or that they are partially flush and partially have a certain height difference.

[0083] For example, the semiconductor device further includes a control gate structure formed on the inter-gate dielectric layer 305 of the trench, the control gate structure including a gate dielectric layer formed on the sidewall of the trench and a control gate formed in the trench.

[0084] This concludes the introduction to the structure of the semiconductor device of the present invention. The complete device may also include other components, which will not be described in detail here.

[0085] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A substrate is provided, and a trench is formed extending from a first surface of the substrate into the interior of the substrate. A shielding dielectric layer is formed at the bottom and part of the sidewalls of the trench, and a shielding grid is formed in the trench. The shielding grid fills a portion of the depth of the trench, and the top surface of the shielding grid is higher than the top surface of the shielding dielectric layer. The distance from the top surface of the shielding dielectric layer to the first surface is a first depth. The shielding gate is partially etched away so that the top surface of the shielding gate is flush with the top surface of the shielding dielectric layer. At the same time, a substrate of a predetermined thickness is etched away from the first surface so that the distance from the top surface of the shielding dielectric layer to the first surface is a second depth, and the first depth is greater than the second depth. An inter-gate dielectric layer is deposited in the trench, and a control gate structure is formed on the portion of the trench located on the inter-gate dielectric layer; The step of depositing an inter-gate dielectric layer in the trench includes: depositing an inter-gate dielectric material layer in the trench and on the first surface of the substrate using a high-density plasma deposition process.

2. The method according to claim 1, characterized in that, The method of forming the shielding medium layer at the bottom and part of the sidewalls of the trench and forming the shielding grid in the trench includes: A shielding dielectric material layer is formed at the bottom of the trench, on the sidewalls, and on the first surface of the substrate; The shielding grid is formed to fill a portion of the depth of the trench; Etching removes a portion of the shielding dielectric material layer on the sidewall of the trench and exposes a portion of the sidewall of the trench, while simultaneously etching removes the shielding dielectric material layer on the first surface to form the shielding dielectric layer.

3. The method according to claim 2, characterized in that, A wet etching process is used to etch away a portion of the shielding dielectric layer on the sidewall of the trench and to etch away the shielding dielectric layer on the first surface.

4. The method according to claim 1, characterized in that, A dry etching process is used to etch away part of the shielding gate and the substrate of a predetermined thickness.

5. The method according to claim 1, characterized in that, The distance between the sidewalls above the shielding grid where the trench is located is a first width, and the ratio of the second depth to the first width is less than 2.

5.

6. The method according to claim 1, characterized in that, The predetermined thickness is in the range of 0.1 μm - 0.3 μm.

7. The method according to claim 1, characterized in that, The second depth ranges from 0.7 μm to 1.3 μm.

8. The method according to claim 1, characterized in that, The method for forming the inter-gate dielectric layer and the control gate structure further includes: The inter-gate dielectric material layer on the first surface is planarized. The inter-gate dielectric material layer within the trench is etched back to form an inter-gate dielectric layer within the trench; The control gate structure is formed on the portion of the trench located on the inter-gate dielectric layer.

9. A semiconductor device, characterized in that, The semiconductor device is prepared using the method described in any one of claims 1-8.

Images