Etching method for removing pseudo polysilicon gate

Abstract

The application discloses an etching method for removing pseudo polysilicon gates, comprising the following steps: step one, providing a semiconductor substrate on which a zeroth layer interlayer film planarization process is completed, the zeroth layer interlayer film is filled in the interval area of the pseudo polysilicon gates, and the top surface of the pseudo polysilicon gates is exposed; step two, pre-treating the surface of the semiconductor substrate to remove the carbon-containing polymer on the surface; and step three, performing first etching to remove the pseudo polysilicon gates, and fluorine-based gas without carbon is used as the etching gas of the first etching to reduce or eliminate the first polymer defects generated by the first etching. The application can improve the polymer defects.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit manufacturing method, and more particularly to an etching method for removing dummy polysilicon gates (DPR). Background Technology

[0002] High-kJ metal gate (HKMG) technology requires the simultaneous formation of a high-kJ (HK) gate dielectric layer and a metal gate (MG). In current HKMG advanced logic chip processes, the gate width is continuously decreasing as the technology node shrinks. HKMG processes typically employ a dummy polysilicon gate (DPR). First, the DPR is removed, and then different types of work function films and the metal gate are deposited.

[0003] Typically, NMOS and PMOS are integrated on the same semiconductor substrate. The work function layer of PMOS is usually made of TiN, while that of NMOS is usually made of TiAl. In the process of forming different types of work function thin films, TiN is usually formed first, and then the TiN in the NMOS formation region is removed (NMOSE Remove Gate, NRG).

[0004] After NRG is completed, a scan will reveal pre-layer polymer defects, which are polymer defects formed during the DPR process. However, the carbon base component of these defects is not shown in failure analysis because the defects are thin and are generally not detected by the DPR process station. They only become visible after deposition (DEP) in the subsequent NRG step. This defect reduces yield by 100%. In the NRG step, a siloxane polymer (DUO) layer and photoresist are typically coated, forming the NRG layer. Figure 1A The image shown is a wafer defect map obtained after forming the NRG layer, based on the existing etching method for removing pseudo-polysilicon gates. It can be seen that large defects 102a exist on the entire wafer surface composed of the semiconductor substrate 101a; these defects 102a are all pre-polymer defects. Figure 1B As shown, is Figure 1A The magnified image of the defects shows that the front polymer defect 102a will cover the gate trench formed after DPR.

[0005] like Figures 2A to 2C The diagram shown is a schematic representation of the device structure in each step of the existing etching method for removing pseudo-polysilicon gates. The existing etching method for removing pseudo-polysilicon gates includes the following steps:

[0006] Step 1, such as Figure 2AAs shown, a semiconductor substrate 101 is provided having undergone a planarization process for a zero-layer interlayer film 104, the zero-layer interlayer film 104 filling the spacer region of a pseudo-polysilicon gate 106, and the top surface of the zero-layer interlayer film 104 being flush with the top surface of the pseudo-polysilicon gate 106, thereby exposing the top surface of the pseudo-polysilicon gate 106.

[0007] The semiconductor substrate 101 includes a silicon substrate.

[0008] A high dielectric constant layer 105 is also formed on the surface of the semiconductor substrate 101 at the bottom of the pseudo polysilicon gate 106.

[0009] A shallow trench isolation (STI) 103 is also formed on the semiconductor substrate 101. The shallow trench isolation 103 isolates an active region on the semiconductor substrate 101, and NMOS and PMOS are formed in the active region of the corresponding region. Figure 2A In the diagram, the PMOS formation region is indicated by curly braces marked 108, and the NMOS formation region is indicated by curly braces marked 109. N-wells (not shown) are formed in the PMOS formation region, and P-wells (not shown) are formed in the NMOS formation region.

[0010] Typically, the semiconductor substrate 101 includes both a core region and an input / output (IO) region. The size of the core device in the core region is smaller than the size of the input / output device in the IO region. Figure 2A Only one region of NMOS and PMOS is shown. An embedded germanium-silicon epitaxial layer 107 is also formed on both layers of the pseudo-polysilicon gate 106 of the PMOS to enhance its performance. Sidewalls (not shown) are formed on the sides of the pseudo-polysilicon gate 106, and active / drain regions (not shown) are formed in the semiconductor substrate 101 on both sides of each pseudo-polysilicon gate 106.

[0011] Step Two, as follows Figure 2B As shown, a first etching is performed to remove the pseudo-polysilicon gate 106 and form a gate trench in the removal area of ​​the pseudo-polysilicon gate 106. The etching gas used for the first etching is CF4.

[0012] The first etching step is the DRP etching. Typically, polymer defects 102 are easily formed during the first etching. However, because the polymer defects 102 are very thin, they cannot be detected after the first etching step. Therefore, subsequent processes will proceed.

[0013] Subsequent processes include:

[0014] Step 3: Form the bottom barrier layer (BBM).

[0015] The bottom barrier layer includes a first TaN layer, which is formed in step three.

[0016] The bottom barrier layer further includes a first TiN layer, which is formed on the surface of the high dielectric constant layer 105. The first TiN layer is formed before the pseudo polysilicon gate 106 is deposited. In step three, the first TaN layer is superimposed on the surface of the first TiN layer.

[0017] Step 4, as follows Figure 2C As shown, the P-type work function layer 110 is typically made of TiN.

[0018] Polymer defects 102 can be revealed after the formation of the first TaN layer and the P-type work function layer 110.

[0019] Step 5: Remove the P-type work function layer 110 from the NMOS formation region. This includes the following sub-steps:

[0020] Step 51: Sequentially coat the DUO layer and the photoresist to form the NRG layer. After the NRG layer is formed, the polymer defects 102 will be further magnified and become visible. Figure 1A The wafer defect scan map is obtained by performing a defect scan after step 51.

[0021] Step 52: Perform photolithography to open the NMOS formation region and cover the PMOS formation region;

[0022] Step 53: Etch to remove the P-type work function layer 110 in the NMOS formation region;

[0023] Step 54: Perform etching to remove the NRG layer.

[0024] Following that, it also includes:

[0025] Forming an N-type work function layer;

[0026] A layer of conductive metal material is filled in the gate trench with a metal gate. Summary of the Invention

[0027] The technical problem to be solved by the present invention is to provide an etching method for removing pseudo polysilicon gates, which can improve polymer defects.

[0028] To solve the above-mentioned technical problems, the etching method for removing pseudo-polysilicon gates provided by the present invention includes the following steps:

[0029] Step 1: Provide a semiconductor substrate that has completed the zeroth interlayer film planarization process. The zeroth interlayer film fills the spacer region of the pseudo-polysilicon gate, and the top surface of the zeroth interlayer film is flush with the top surface of the pseudo-polysilicon gate, thereby exposing the top surface of the pseudo-polysilicon gate.

[0030] Step 2: Pre-treat the surface of the semiconductor substrate to remove the carbon-containing polymer on the surface of the zeroth interlayer film and the pseudo-polycrystalline silicon gate.

[0031] Step 3: Perform a first etching to remove the pseudo-polysilicon gate and form a gate trench in the pseudo-polysilicon gate removal region. The etching gas used in the first etching is a carbon-free fluorine-based gas to reduce or eliminate the first polymer defects generated by the first etching.

[0032] A further improvement is that, in step two, the pretreatment process gas is O2.

[0033] A further improvement is that, in step three, the etching gas used for the first etching includes NF3.

[0034] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0035] A further improvement is that, in step one, a high dielectric constant layer is also formed on the surface of the semiconductor substrate at the bottom of the pseudo-polycrystalline silicon gate.

[0036] A further improvement is that, after step three is completed, the following steps are also included:

[0037] Step 4: Form the bottom barrier layer;

[0038] Step 5: P-type work function layer;

[0039] If the first polymer defect remains in step three, the first polymer defect will not be apparent in step three, but will be apparent in step five.

[0040] Step 6: Remove the P-type work function layer from the NMOS formation region.

[0041] A further improvement is that step six includes the following sub-steps:

[0042] Step 61: Sequentially coat the DUO layer and the photoresist, forming the NRG layer;

[0043] Step 62: Perform photolithography to open the NMOS formation region and cover the PMOS formation region;

[0044] Step 63: Perform etching to remove the P-type work function layer in the NMOS formation region;

[0045] Step 64: Perform etching to remove the NRG layer.

[0046] A further improvement is that the bottom barrier layer includes a first TaN layer, which is formed in step four.

[0047] A further improvement is that the bottom barrier layer further includes a first TiN layer, which is formed on the surface of the high dielectric constant layer and is formed before the pseudo polysilicon gate deposition;

[0048] In step four, the first TaN layer is superimposed on the surface of the first TiN layer.

[0049] A further improvement is that, in step five, the material of the P-type work function layer includes TiN.

[0050] A further improvement is that the number of the first polymer defects remaining in step three will not be apparent after step three is completed. The number of the first polymer defects is obtained by defect scanning after the P-type work function layer is formed in step five or after the NRG layer is formed in step 61.

[0051] A further improvement is that a natural oxide layer is formed on the surface of the pseudo-polysilicon gate. In step three, the first etching removes the natural oxide layer first, and then removes the pseudo-polysilicon gate.

[0052] This invention adds a pretreatment process before the DPR etching, i.e., the first etching. This pretreatment removes carbon-containing polymers present on the surface of the semiconductor substrate, such as the zero-layer interlayer film and the surface of the pseudo-polysilicon gate, thereby preventing these carbon-containing polymers from forming the first polymer defect. This invention also sets the etching gas for the first etching to a carbon-free fluorine-based gas, such as NF3. Since carbon-free fluorine-based gases do not contain carbon, they can prevent the further formation of carbon-containing polymers during the first etching. Therefore, the first polymer defect generated by the first etching can be reduced or eliminated, thereby improving product yield. Attached Figure Description

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0054] Figure 1A This is a wafer defect scan map obtained after the formation of the NRG layer, showing the defects of existing etching methods for removing pseudo-polysilicon gates.

[0055] Figure 1B yes Figure 1A Enlarged view of the defects in the image;

[0056] Figures 2A-2C This is a schematic diagram of the device structure in each step of the existing etching method for removing pseudo-polysilicon gates;

[0057] Figure 3 This is a flowchart of an etching method for removing pseudo polysilicon gates according to an embodiment of the present invention;

[0058] Figures 4A-4C This is a schematic diagram of the device structure in each step of the etching method for removing pseudo polysilicon gates according to an embodiment of the present invention;

[0059] Figure 5 This is a comparison chart of the etching rate of the first etching step in the etching method for removing pseudo polysilicon gates according to an embodiment of the present invention and the etching rate of existing methods.

[0060] Figure 6 This is a wafer defect scan image obtained after forming the NRG layer, showing the defects of the etching method for removing pseudo-polysilicon gates according to an embodiment of the present invention. Detailed Implementation

[0061] like Figure 3 The diagram shows a flowchart of an etching method for removing the pseudo-polysilicon gate 206 according to an embodiment of the present invention; as shown... Figures 4A to 4C The diagram shown is a schematic representation of the device structure in each step of the etching method for removing the pseudo-polysilicon gate 206 according to an embodiment of the present invention. The etching method for removing the pseudo-polysilicon gate 206 according to an embodiment of the present invention includes the following steps:

[0062] Step 1, such as Figure 4A As shown, a semiconductor substrate 201 is provided having undergone a planarization process for the zeroth interlayer film 204, which fills the spacer region of the pseudo-polysilicon gate 206, and the top surface of the zeroth interlayer film 204 is flush with the top surface of the pseudo-polysilicon gate 206, thereby exposing the top surface of the pseudo-polysilicon gate 206.

[0063] In this embodiment of the invention, the semiconductor substrate 201 includes a silicon substrate.

[0064] A high dielectric constant layer 205 is also formed on the surface of the semiconductor substrate 201 at the bottom of the pseudo polysilicon gate 206.

[0065] A shallow trench isolation (STI) 203 is also formed on the semiconductor substrate 201. The shallow trench isolation 203 isolates an active region on the semiconductor substrate 201, and NMOS and PMOS are formed in the active region of the corresponding region. Figure 4A In the diagram, the PMOS formation region is indicated by curly braces marked 208, and the NMOS formation region is indicated by curly braces marked 209.

[0066] Typically, the semiconductor substrate 201 includes both a core region and an input / output (I / O) region. The size of the core device in the core region is smaller than the size of the input / output device in the I / O region. Figure 4A Only one region of NMOS and PMOS is shown. An embedded germanium-silicon epitaxial layer 207 is also formed on both layers of the pseudo-polysilicon gate 206 of the PMOS to enhance its performance. Sidewalls (not shown) are formed on the sides of the pseudo-polysilicon gate 206, and active / drain regions (not shown) are formed in the semiconductor substrate 201 on both sides of each pseudo-polysilicon gate 206.

[0067] During the planarization process of the zeroth interlayer film 204, chemical mechanical polishing or etch-back processes are used, which can easily produce carbon-containing polymer 210.

[0068] Step Two, as follows Figure 4B As shown, the surface of the semiconductor substrate 201 is pretreated to remove carbon-containing polymer 210 from the surfaces of the zeroth interlayer film 204 and the pseudo polysilicon gate 206.

[0069] In this embodiment of the invention, the pretreatment process gas is O2.

[0070] Step 3, as follows Figure 4C As shown, a first etching is performed to remove the pseudo-polysilicon gate 206 and form a gate trench in the removal area of ​​the pseudo-polysilicon gate 206. The etching gas used in the first etching is a carbon-free fluorine-based gas to reduce or eliminate the first polymer defects generated by the first etching.

[0071] In this embodiment of the invention, the etching gas used for the first etching includes NF3.

[0072] A native oxide layer (not shown) is also formed on the surface of the pseudo polysilicon gate 206. The first etching removes the native oxide layer first, and then removes the pseudo polysilicon gate 206.

[0073] The first etching is a DRP BT (break-through) etching process. In existing processes, tetrafluoromethane (CF4) is used as the etching gas for the first etching. In this embodiment of the invention, NF3 is used instead of CF4, thereby reducing or eliminating the first polymer defect; however, this does not affect the effectiveness of the first etching. Figure 5 The figure shown is a comparison of the etching rate of the first etching step in the etching method for removing pseudo polysilicon gates according to the present invention and the etching rate of the existing method. Each etching rate is a distribution map along the entire wafer. Figure 5In the diagram, distribution diagram 301 shows the etching rate of the oxide layer when the etching gas for the first etching in the existing method is CF4, and distribution diagram 302 shows the etching rate of the oxide layer when the etching gas for the first etching in the method of the present invention is NF3. It can be seen that there is little difference between the two, and the embodiment of the present invention can also achieve good etching of the oxide layer. Distribution diagram 303 shows the etching rate of polysilicon when the etching gas for the first etching in the existing method is CF4, and distribution diagram 304 shows the etching rate of polysilicon when the etching gas for the first etching in the method of the present invention is NF3. It can be seen that there is little difference between the two, and the embodiment of the present invention can also achieve good etching of polysilicon.

[0074] After step three is completed, the following steps are also included:

[0075] Step 4: Form the bottom barrier layer (not shown).

[0076] In some embodiments, the bottom barrier layer includes a first TaN layer, which is formed in step four.

[0077] In other embodiments, the bottom barrier layer further includes a first TiN layer formed on the surface of the high-dielectric-constant layer 205, the first TiN layer being formed prior to the deposition of the pseudo-polysilicon gate 206. In step four, the first TaN layer is superimposed on the surface of the first TiN layer.

[0078] Step 5, P-type work function layer (not shown).

[0079] If the first polymer defect remains in step three, the first polymer defect will not be apparent in step three, but will be apparent in step five.

[0080] In some embodiments, the material of the P-type work function layer includes TiN.

[0081] Step Six: Remove the P-type work function layer from the NMOS formation region. In some embodiments, Step Six includes the following sub-steps:

[0082] Step 61: Sequentially coat the DUO layer and the photoresist, forming the NRG layer;

[0083] Step 62: Perform photolithography to open the NMOS formation region and cover the PMOS formation region;

[0084] Step 63: Perform etching to remove the P-type work function layer in the NMOS formation region;

[0085] Step 64: Perform etching to remove the NRG layer.

[0086] Following that, it also includes:

[0087] Forming an N-type work function layer;

[0088] A layer of conductive metal material is filled in the gate trench with a metal gate.

[0089] In this embodiment of the invention, the number of the first polymer defects remaining in step three will not be apparent after step three is completed. The number of the first polymer defects is obtained by defect scanning after the P-type work function layer is formed in step five or after the NRG layer is formed in step 61.

[0090] like Figure 6 The image shown is a wafer defect scan obtained after forming the NRG layer, illustrating the defect removal method for the pseudo-polysilicon gate according to an embodiment of the present invention. It can be seen that only a reduced number of the first polymer defects 202 are formed on the wafer surface composed of the semiconductor substrate 201a. Figure 1A compared to, Figure 6 The number of the first polymer defects 202 is greatly reduced, thereby improving product yield.

[0091] This invention adds a pretreatment process before the DPR etching, i.e., the first etching. The pretreatment removes carbon-containing polymers 210 present on the surface of the semiconductor substrate 201, such as the zero-layer interlayer film 204 and the pseudo-polysilicon gate 206, thereby preventing these carbon-containing polymers 210 from forming the first polymer defect. This invention also sets the etching gas for the first etching to a carbon-free fluorine-based gas such as NF3. Since carbon-free fluorine-based gases do not contain carbon, they can prevent the further formation of carbon-containing polymers 210 in the first etching. Therefore, the first polymer defect generated by the first etching can be reduced or eliminated, thereby improving the product yield.

[0092] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An etching method for removing a dummy polysilicon gate, characterized by, The method comprises the following steps: Step one, providing a semiconductor substrate which has completed a zeroth interlayer film planarization process, the zeroth interlayer film fills in the interval area of the pseudo polysilicon gate, and the top surface of the zeroth interlayer film is flat with the top surface of the pseudo polysilicon gate, so that the top surface of the pseudo polysilicon gate is exposed; Step two, pre-treating the surface of the semiconductor substrate, the pre-treatment removes the carbon-containing polymer on the surface of the zeroth interlayer film and the pseudo polysilicon gate; Step three, performing a first etching to remove the pseudo polysilicon gate and form a gate trench in the area where the pseudo polysilicon gate is removed, the etching gas of the first etching uses a fluorine-based gas without carbon to reduce or eliminate the first polymer defects generated by the first etching.

2. The method of claim 1, wherein the method further comprises: removing the pseudo-polysilicon gate by etching. In step two, the process gas of the pre-treatment uses O2. ​ 3. The etching method for removing pseudo-polysilicon gates as described in claim 1, characterized in that: In step three, the etching gas of the first etching includes NF3.

4. The method of claim 1, wherein the method further comprises: removing the pseudo-polysilicon gate by etching. The semiconductor substrate includes a silicon substrate. ​ 5. The method of claim 1, wherein: the etching is performed using a mixture of H2SO4 and H2O2. In step one, a high dielectric constant layer is also formed on the surface of the semiconductor substrate at the bottom of the pseudo polysilicon gate.

6. The method of claim 5, wherein the etching of the dummy polysilicon gate is performed by a dry etching process. After step three is completed, the following steps are further included: Step four, forming a bottom barrier layer; Step five, a P-type work function layer; When the first polymer defects remain in step three, the first polymer defects do not appear in step three, and the first polymer defects appear in step five; Step six, removing the P-type work function layer in the NMOS forming area.

7. The method of claim 6, wherein the etching is performed by using a mixture of H2SO4 and H2O2. Step six includes the following sub-steps: Step 61, coating a DUO layer and a photoresist in sequence to form an NRG layer composed of the DUO layer and the photoresist; Step 62, performing photolithography to open the NMOS forming area and cover the PMOS forming area; Step 63, performing etching to remove the P-type work function layer in the NMOS forming area; Step 64, performing etching to remove the NRG layer.

8. The method of claim 6, wherein the etching of the dummy polysilicon gate is performed by a dry etching process. The bottom barrier layer includes a first TaN layer, which is formed in step four.

9. The method of claim 8, wherein: the etching is performed using a mixture of H2SO4 and H2O2. The bottom barrier layer further includes a first TiN layer, which is formed on the surface of the high dielectric constant layer, and the first TiN layer is formed before the deposition of the pseudo polysilicon gate; In step four, the first TaN layer is superimposed on the surface of the first TiN layer.

10. The method of claim 6, wherein the method further comprises: removing the pseudo-polysilicon gate by etching. 10 In step five, the material of the P-type work function layer includes TiN.

11. The method of claim 7, wherein: the etching is performed using a mixture of H2SO4 and H2O2. The number of the first polymer defects remaining in step three does not appear after step three is completed, and the number of the first polymer defects is obtained by defect scanning after step five forms the P-type work function layer or after step 61 forms the NRG layer.

12. The method of claim 1, wherein: the gate is a dummy poly gate. 5 A natural oxide layer is also formed on the surface of the pseudo polysilicon gate, and in step three, the first etching removes the natural oxide layer before removing the pseudo polysilicon gate.

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