Flash memory device and method of manufacturing the same

Abstract

The application provides a flash memory device and a manufacturing method thereof. After removing a hard mask layer, a floating gate material layer is etched to form a floating gate under a first sidewall and form a floating gate tip at the top of the sidewall of the floating gate away from a source line. The application optimizes the process flow of the flash memory device, cancels the etching step of the floating gate material layer before the forming step of the first sidewall, and forms the floating gate tip at the top of the sidewall of the floating gate away from the source line, which reduces the influence of the thickness variation of the floating gate on the sharpness of the floating gate tip and facilitates the further size reduction of the flash memory device. Further, the application exposes the floating gate tip by shortening the thickness of the first sidewall, which optimizes the erasing effect of the flash memory device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a flash memory device and its manufacturing method. Background Technology

[0002] Flash memory, as a type of non-volatile memory, controls the switching of gate channels by changing the threshold voltage of transistors or memory cells, thereby achieving the purpose of storing data and ensuring that the data stored in the memory is not lost due to power interruption. In existing flash memory devices, the sharpness of the floating gate tip affects the voltage coupled to the floating gate during programming and erasing, thus affecting the performance of the flash memory device during programming and erasing. Therefore, precise control of the floating gate tip is of great practical significance for controlling the performance of flash memory.

[0003] In the manufacturing process of existing flash memory devices, the sharpness of the floating gate tip is usually related to the thickness of the floating gate layer. When the thickness of the floating gate layer is thin (i.e., the thickness of the floating gate layer is less than...), the sharpness of the floating gate tip is... For example, The subsequent floating gates have blunter tips, which negatively impacts the voltage withstand performance of flash memory devices.

[0004] To avoid the aforementioned problems, the thickness of the floating gate layer is typically increased to [amount missing]. Left and right (e.g., for example) However, the thickness limitation of the floating gate layer affects further miniaturization of flash memory devices. When the floating gate layer is too thick, it also affects the aspect ratio of the subsequently formed shallow trench isolation (STI) structure, thereby affecting the effect of material deposition in the shallow trench isolation structure, and in severe cases, even causing void defects in the material layer filling the shallow trench isolation structure. Summary of the Invention

[0005] The purpose of this invention is to provide a flash memory device and its manufacturing method, which reduces the influence of the floating gate thickness on the sharpness of the floating gate tip.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing a flash memory device, comprising:

[0007] A substrate is provided on which a floating gate material layer and a hard mask layer are sequentially formed, wherein an opening is formed in the hard mask layer to expose the floating gate material layer;

[0008] A first sidewall is formed on the sidewall of the opening, and the exposed floating gate material layer of the opening is removed to expose the substrate below the opening;

[0009] A second sidewall is formed on the sidewall and bottom of the opening, and a source line is formed within the opening;

[0010] Remove the hard mask layer to expose the floating gate material layer beneath it; and,

[0011] The exposed layer of the floating grid material is removed to form a floating grid below the first sidewall, and the top of the sidewall of the floating grid away from the source line has a floating grid tip.

[0012] Optionally, an anisotropic dry etching process can be used to remove the exposed floating gate material layer to form the floating gate and the floating gate tip.

[0013] Optionally, the anisotropic dry etching process includes two stages, wherein:

[0014] The process parameters for the first stage include: chamber pressure of 10 mTorr to 14 mTorr, source power of 250 W to 300 W, bias voltage of -195 V to -155 V, process gases including carbon tetrafluoride and difluoromethane, and the gas flow rate of the process gases is 25 sccm to 35 sccm, and the process time is 6 sec to 10 sec.

[0015] The process parameters for the second stage include: chamber pressure of 10 mTorr to 15 mTorr, source power of 180 W to 220 W, bias voltage of -280 V to -240 V, process gases including chlorine, hydrogen bromide and oxygen, wherein the gas flow rate of chlorine is 13 sccm to 17 sccm, the gas flow rate of hydrogen bromide is 95 sccm to 105 sccm, the gas flow rate of oxygen is 8 sccm to 12 sccm, and the process time is 10 sec to 14 sec.

[0016] Optionally, after forming the floating gate, the method further includes:

[0017] Reduce the width of the first sidewall so that the top of the floating gate tip is exposed;

[0018] A third sidewall is formed, the third sidewall covering the tip of the grating, the sidewall of the grating away from the source line, and at least a portion of the first sidewall; and,

[0019] A letter line is formed on the side of the third sidewall away from the floating gate.

[0020] Optionally, a wet etching process can be used to shorten the width of the first sidewall.

[0021] Optionally, after forming the second sidewall and before forming the source line, the process further includes:

[0022] A source region is formed within the substrate at the bottom of the opening.

[0023] Optionally, a floating gate dielectric layer is further formed between the substrate and the floating gate material layer, and a protective layer is further formed on the surface of the source line.

[0024] Accordingly, the present invention also provides a flash memory device, manufactured using the method for manufacturing the flash memory device, comprising:

[0025] Substrate;

[0026] The source line is disposed on the surface of the substrate;

[0027] A floating gate is disposed on the substrate surface on both sides of the source line, and the top of the sidewall of the floating gate away from the source line has a floating gate tip;

[0028] A first sidewall is disposed on the surface of the floating gate, and the first sidewall exposes the tip of the floating gate; and,

[0029] The second sidewall is disposed between the source line and the floating gate, between the source line and the substrate, and between the source line and the first sidewall.

[0030] Optionally, the flash memory device further includes:

[0031] The word line is disposed on the substrate on the side of the floating grid away from the source line, and a third sidewall is disposed between the word line and the floating grid;

[0032] The source region is disposed within the substrate below the source line;

[0033] A floating gate dielectric layer is disposed between the substrate and the floating gate;

[0034] A protective layer is disposed on the surface of the source line.

[0035] Optionally, the flash memory device is a gate-based memory. 。

[0036] In summary, this invention provides a flash memory device and its manufacturing method. After removing the hard mask layer, an etching process is performed on the floating gate material layer to form a floating gate below the first sidewall, and a floating gate tip is formed at the top of the sidewall of the floating gate away from the source line. This invention optimizes the flash memory device process flow by eliminating the etching step of the floating gate material layer before the formation of the first sidewall, and by forming the floating gate tip at the top of the sidewall of the floating gate away from the source line. This reduces the impact of the thickness variation of the floating gate on the sharpness of the floating gate tip, facilitating further reduction in the size of the flash memory device.

[0037] Furthermore, the present invention optimizes the erasure effect of the flash memory device by exposing the tip of the floating gate by shortening the thickness of the first sidewall. Attached Figure Description

[0038] Figure 1 A flowchart illustrating a method for manufacturing a flash memory device according to an embodiment of the present invention;

[0039] Figures 2 to 12 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of a flash memory device provided in an embodiment of the present invention;

[0040] Figure 13 This is a schematic diagram of the structure of a flash memory device;

[0041] The accompanying figure is labeled as follows:

[0042] 100 - Substrate; 101 - Source region; 110 - Floating gate material layer; 111 - Floating gate dielectric layer; 112 - Floating gate; 112a - Floating gate tip; 120 - Hard mask layer; 130 - Opening; 131 - First sidewall; 132 - Second sidewall; 133 - Third sidewall; 140 - Source line; 141 - Guard layer; 150 - Word line;

[0043] 10-Floating gate; 11-Floating gate tip; 20-Source line. Detailed Implementation

[0044] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] Figure 1 This is a flowchart illustrating a method for manufacturing a flash memory device according to an embodiment of the present invention. (See attached document.) Figure 1 The method for manufacturing the flash memory device described in this embodiment includes:

[0046] Step S01: Provide a substrate on which a floating gate material layer and a hard mask layer are sequentially formed, and an opening is formed in the hard mask layer to expose the floating gate material layer;

[0047] Step S02: Form a first sidewall on the sidewall of the opening and remove the exposed floating gate material layer of the opening to expose the substrate below the opening;

[0048] Step S03: Form a second sidewall on the sidewall and bottom of the opening, and form a source line inside the opening;

[0049] Step S04: Remove the hard mask layer to expose the floating gate material layer beneath the hard mask layer; and,

[0050] Step S05: Remove the exposed floating grid material layer to form a floating grid below the first sidewall, wherein the top of the sidewall of the floating grid away from the source line has a floating grid tip.

[0051] Figures 2 to 12 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of the flash memory device provided in this embodiment, and Figures 2 to 12 These are all schematic cross-sectional views of the flash memory device along the direction perpendicular to the source line. The following are combined with... Figures 2 to 12 The manufacturing method of the flash memory device described in this embodiment is explained in detail.

[0052] First, refer to Figure 2 and Figure 3 In step S01, a substrate 100 is provided, on which a floating gate material layer 110 and a hard mask layer 120 are sequentially formed, and an opening 130 is formed in the hard mask layer 120 to expose the floating gate material layer.

[0053] For example, the process of forming the opening 130 includes: (See...) Figure 2 A substrate 100 is provided, on which a floating gate material layer 110 and a hard mask layer 120 are deposited and formed, respectively; then, refer to Figure 3 The hard mask layer 120 is patterned to form a patterned photoresist layer (not shown in the figure), and the hard mask layer 120 is etched using the patterned photoresist layer as a mask to form an opening 130. Optionally, after forming the opening 130, the patterned photoresist layer is removed by a photoresist stripping process. Optionally, the floating gate material layer 110 and the hard mask layer 120 are formed using chemical vapor deposition (CVD).

[0054] In this embodiment, the substrate 100 is a silicon substrate, the floating gate material layer 110 is a polysilicon layer, and the hard mask layer is a silicon nitride layer. Optionally, a floating gate dielectric layer 111 is further formed between the substrate 100 and the floating gate material layer 110, and the floating gate dielectric layer 111 is a silicon oxide layer. In other embodiments of the present invention, the materials and structures of the substrate 100, the hard mask layer 120, and the floating gate dielectric layer 111 can be adjusted according to actual needs. For example, the hard mask layer 120 can be adjusted to a silicon oxide layer or a stacked structure composed of a silicon oxide layer and a silicon nitride layer, and the material of the floating gate dielectric layer 111 can be replaced with other oxide materials (e.g., tetraethyl orthosilicate). The present invention does not limit this.

[0055] Next, refer to Figure 4 and Figure 5Step S02 is performed to form a first sidewall 131 on the sidewall of the opening 130 and remove the exposed floating gate material layer 110 of the opening 130 to expose the substrate 100 below the opening 130.

[0056] For example, the process of forming the first sidewall 131 and removing the floating grid material layer 110 below the opening 130 includes: First, referring to Figure 4 A first sidewall material layer (not shown) is deposited within the opening 130, extending to cover the hard mask layers 120 on both sides of the opening 130. The first sidewall material layer is etched away from the bottom of the opening 130 and the surface of the hard mask layers 120 to form the first sidewall 131 on the sidewall of the opening 130; then, refer to... Figure 5 Using the hard mask layer 120 and the first sidewall 131 as masks, the floating gate material layer 110 exposed by the opening 130 and the floating gate material layer 111 below the opening 130 are etched to expose the substrate 100 below the opening 130. Optionally, the first sidewall 131 is a silicon oxide layer.

[0057] Then refer to Figures 6 to 8 Step S03 is executed, in which a second sidewall 132 is formed on the sidewall and bottom of the opening 130, and a source line 140 is formed in the opening 130.

[0058] For example, the process of forming the source line 140 includes: First, referring to... Figure 6 A second sidewall material layer (not shown) is deposited on the sidewalls and bottom of the opening 130. The second sidewall material layer extends to cover the hard mask layers 120 on both sides of the opening 130. A planarization process is then performed, and the second sidewall material layer outside the opening 130 is removed to form a second sidewall 132 covering the first sidewall 131, the sidewalls of the floating gate material layer 110, and the surface of the substrate 100. Next, refer to... Figure 7 An ion implantation process is performed to form a source region 101 within the substrate 100 at the bottom of the opening 130; subsequently, refer to... Figure 8 A polysilicon layer is deposited within the opening 130 and on the hard mask layer 120, followed by planarization. The polysilicon layer on the hard mask layer 120 is then removed, and the surface of the polysilicon layer is made flush with the surface of the hard mask layer 120, thereby forming a source line 140 within the opening 130. Optionally, chemical mechanical polishing (CMP) is used for planarization.

[0059] In this embodiment, a protective layer 141 is also formed on the surface of the source line 140 to protect the source line 140 from damage during subsequent multi-pass etching processes. Optionally, the second sidewall 132 is a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination of both. Optionally, the protective layer 141 can be a silicon oxide layer and / or a silicon nitride layer.

[0060] Next, refer to Figure 9 Step S04 is executed to remove the hard mask layer 120 to expose the floating gate material layer 110 beneath it. In this embodiment, a wet etching process is used to remove the hard mask layer 120. In other embodiments of the present invention, a dry etching process can also be used to remove the hard mask layer 120. The method for removing the hard mask layer 120 can be selected according to the actual process requirements, and the present invention does not limit it.

[0061] Then refer to Figure 10 Step S05 is performed to remove the exposed floating grid material layer 110 to form a floating grid 112 below the first sidewall 131, and the top of the sidewall of the floating grid 112 away from the source line 140 has a floating grid tip 112a.

[0062] In this embodiment, an anisotropic dry etching process is used to remove the exposed floating gate material layer 110. For example, the anisotropic dry etching process includes two stages, wherein: the process parameters of the first stage include: a chamber pressure of 10 mTorr to 14 mTorr, a source power of 250 W to 300 W, a bias voltage of -195 V to -155 V, process gases including carbon tetrafluoride and difluoromethane, and the gas flow rate of the process gases is 25 sccm to 35 sccm, and the process time is 6 sec to 10 sec; the process parameters of the second stage include: a chamber pressure of 10 mTorr to 15 mTorr, a source power of 180 W to 220 W, a bias voltage of -280 V to -240 V, process gases including chlorine, hydrogen bromide and oxygen, wherein the gas flow rate of chlorine is 13 sccm to 17 sccm, the gas flow rate of hydrogen bromide is 95 sccm to 105 sccm, the gas flow rate of oxygen is 8 sccm to 12 sccm, and the process time is 10 sec to 14 sec.

[0063] Continue reading Figure 10 In this embodiment, the tip 112a of the floating gate has an acute angle shape in the cross section perpendicular to the extension direction of the source line 140, so that the final floating gate 112 has a shape that is wider at the top and narrower at the bottom, and the sidewall of the floating gate 112 away from the source line 140 has an inwardly concave arc shape.

[0064] In addition, see Figure 11 and Figure 12 After forming the floating gate 112, the method for manufacturing the flash memory device according to this embodiment further includes: reducing the width of the first sidewall 131 to expose the top of the floating gate tip 112a; forming a third sidewall 133, the third sidewall 133 covering the floating gate tip 112a, the sidewall of the floating gate 112 away from the source line 140, and at least a portion of the first sidewall 131; and forming a word line 150 on the side of the third sidewall 133 away from the floating gate 112.

[0065] For example, the process of forming the word line 150 includes: See Figure 11 The first sidewall 131 is etched to reduce its width and expose the tip 112a of the floating gate; then, refer to Figure 12 A third sidewall material layer (not shown) is deposited on the substrate 100, the sidewall of the floating gate 112 and the surface of the floating gate tip 112a, the sidewall of the first sidewall 131 away from the source line 140, and the surface of the protective layer 141. A word line material layer (not shown) is then deposited on the third sidewall material layer. The third sidewall material layer and the word line material layer on the surface of the substrate 100 and the protective layer 141 are etched away to form the third sidewall 133 and the word line 150. Optionally, a wet etching process is used to reduce the width of the first sidewall 131, and the etchant used in the wet etching process is a hydrofluoric acid solution (HF). In other embodiments of the present invention, the specific formation method of each film layer in the flash memory device can be adjusted according to actual needs, and the present invention does not limit this.

[0066] In this embodiment, the third sidewall 133 can be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination of both, and the present invention is not limited thereto. It should be noted that the reduction in the width of the first sidewall 131 exposes the floating gate tip 112a, thereby improving the erase capability of the flash memory device and optimizing the device performance.

[0067] Accordingly, please continue to refer to Figure 12 The present invention also provides a flash memory device, manufactured using the method for manufacturing the flash memory device, comprising:

[0068] Substrate 100;

[0069] Source line 140 is disposed on the surface of the substrate 100;

[0070] A floating gate 112 is disposed on the surface of the substrate 100 on both sides of the source line 140, and the top of the sidewall of the floating gate 112 away from the source line 140 has a floating gate tip 112a.

[0071] A first sidewall 131 is disposed on the surface of the floating gate 112, and the first sidewall 131 exposes the tip 112a of the floating gate; and,

[0072] The second sidewall 132 is disposed between the source line 140 and the floating gate 112, between the source line 140 and the substrate 110, and between the source line 140 and the first sidewall 131.

[0073] In this embodiment, the cross-section in the direction perpendicular to the extension of the source line 140 (i.e. Figure 12 In this configuration, the floating gate 112 has a shape that is wider at the top and narrower at the bottom, and the sidewall of the floating gate 112 on the side away from the source line 140 is an inwardly concave arc shape. Optionally, the thickness of the floating gate 112 ranges from [specific value missing]. For example, it can be...

[0074] In this embodiment, the flash memory device further includes a word line 150, a source region 101, and a drain region (not shown in the figure). The word line 150 is disposed on a substrate 100 on the side of the floating gate 112 away from the source line 140. A third sidewall 133 is disposed between the word line 150 and the floating gate 112. The source region 101 is disposed within the substrate 100 below the source line 140, and the drain region is disposed within the substrate 100 on the side of the word line 150 away from the floating gate 112. Optionally, a floating gate dielectric layer 111 is further disposed between the substrate 100 and the floating gate 112. Optionally, a protective layer 141 is disposed on the surface of the source line 140 to protect it from damage.

[0075] In this embodiment, the flash memory device is a gate-type memory. In other embodiments of the present invention, the flash memory device can be other semiconductor devices with the same or similar structure. The manufacturing method of the flash memory device can be used to manufacture other semiconductor devices with the same or similar structure, so that the floating gate tip in the semiconductor device is formed on the top of the sidewall of the floating gate away from the source line, thereby achieving the purpose of thinning the floating gate. The present invention does not limit this.

[0076] Figure 13 This is a schematic diagram of the structure of an existing flash memory device. (See attached image.) Figure 13 In existing flash memory devices, the floating gate tip 11 is located on the surface of the floating gate 10 away from the source line 20. Therefore, as the thickness of the floating gate 10 decreases, the sharpness of the floating gate tip 11 is affected by the change in the thickness of the floating gate 10; the thinner the floating gate 10, the blunter the floating gate tip 11. (See also...) Figure 12In the flash memory device described in this embodiment, the floating gate tip 112a is located at the top of the sidewall of the floating gate 112 away from the source line 140. Therefore, the thickness variation of the floating gate 112 has a relatively small impact on the sharpness of the floating gate tip 112a. This allows for a reduction in the thickness of the floating gate 112 while ensuring that the floating gate tip 112a is sufficiently sharp, making further miniaturization of the flash memory device possible. Furthermore, the manufacturing method of the flash memory device described in this embodiment optimizes existing flash memory manufacturing methods by eliminating the etching step of the floating gate material layer before the first sidewall fabrication step, thus improving production efficiency.

[0077] In summary, this invention provides a flash memory device and its manufacturing method. After removing the hard mask layer, an etching process is performed on the floating gate material layer to form a floating gate below the first sidewall, and a floating gate tip is formed at the top of the sidewall of the floating gate away from the source line. This invention optimizes the flash memory device process flow by eliminating the etching step of the floating gate material layer before the formation of the first sidewall, and by forming the floating gate tip at the top of the sidewall of the floating gate away from the source line. This reduces the impact of the thickness variation of the floating gate on the sharpness of the floating gate tip, facilitating further reduction in the size of the flash memory device.

[0078] Furthermore, the present invention optimizes the erasure effect of the flash memory device by exposing the tip of the floating gate by shortening the thickness of the first sidewall.

[0079] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.

Claims

1. A method for manufacturing a flash memory device, characterized in that, include: A substrate is provided on which a floating gate material layer and a hard mask layer are sequentially formed, wherein an opening is formed in the hard mask layer to expose the floating gate material layer; A first sidewall is formed on the sidewall of the opening, and the exposed floating gate material layer of the opening is removed to expose the substrate below the opening; A second sidewall is formed on the sidewall and bottom of the opening, and a source line is formed within the opening; Remove the hard mask layer to expose the floating gate material layer beneath it; as well as, The exposed floating grid material layer is removed to form a floating grid below the first sidewall, and the top of the sidewall of the floating grid away from the source line has a floating grid tip, which has an acute angle shape in a cross section perpendicular to the extension direction of the source line, so that the final floating grid has a shape that is wider at the top and narrower at the bottom, and the sidewall of the floating grid away from the source line has an inwardly concave arc shape.

2. The method for manufacturing a flash memory device as described in claim 1, characterized in that, An anisotropic dry etching process is used to remove the exposed floating gate material layer to form the floating gate and the floating gate tip.

3. The method for manufacturing a flash memory device as described in claim 2, characterized in that, The anisotropic dry etching process includes two stages, wherein: The process parameters for the first stage include: chamber pressure of 10 mTorr to 14 mTorr, source power of 250 W to 300 W, bias voltage of -195 V to -155 V, process gases including carbon tetrafluoride and difluoromethane, and the gas flow rate of the process gases is 25 sccm to 35 sccm, and the process time is 6 sec to 10 sec. The process parameters for the second stage include: chamber pressure of 10 mTorr to 14 mTorr, source power of 180 W to 220 W, bias voltage of -280 V to -240 V, process gases including chlorine, hydrogen bromide and oxygen, wherein the gas flow rate of chlorine is 13 sccm to 17 sccm, the gas flow rate of hydrogen bromide is 95 sccm to 105 sccm, the gas flow rate of oxygen is 8 sccm to 12 sccm, and the process time is 10 sec to 14 sec.

4. The method for manufacturing a flash memory device as described in claim 1, 2, or 3, characterized in that, After forming the floating gate, the process also includes: Reduce the width of the first sidewall so that the top of the floating gate tip is exposed; A third sidewall is formed, the third sidewall covering the tip of the grating, the sidewall of the grating away from the source line, and at least a portion of the first sidewall; and, A letter line is formed on the side of the third sidewall away from the floating gate.

5. The method for manufacturing a flash memory device as described in claim 4, characterized in that, The width of the first sidewall is reduced by using a wet etching process.

6. The method for manufacturing a flash memory device as described in claim 1, characterized in that, After the second sidewall is formed and before the source line is formed, the process further includes: A source region is formed within the substrate at the bottom of the opening.

7. The method for manufacturing a flash memory device as described in claim 1, characterized in that, A floating gate dielectric layer is also formed between the substrate and the floating gate material layer, and a protective layer is also formed on the surface of the source line.

8. A flash memory device, manufactured using the method for manufacturing a flash memory device as described in any one of claims 1 to 7, characterized in that, include: Substrate; The source line is disposed on the surface of the substrate; A floating gate is disposed on the substrate surface on both sides of the source line. The top of the sidewall of the floating gate away from the source line has a floating gate tip. The floating gate tip has an acute angle shape in a cross section perpendicular to the extension direction of the source line, making the floating gate have a shape that is wider at the top and narrower at the bottom. The sidewall of the floating gate on the side away from the source line is an inwardly concave arc shape. A first sidewall is disposed on the surface of the floating grid, and the first sidewall exposes the tip of the floating grid; as well as, The second sidewall is disposed between the source line and the floating gate, between the source line and the substrate, and between the source line and the first sidewall.

9. The flash memory device as claimed in claim 8, characterized in that, The flash memory device also includes: The word line is disposed on the substrate on the side of the floating grid away from the source line, and a third sidewall is disposed between the word line and the floating grid; The source region is disposed within the substrate below the source line; A floating gate dielectric layer is disposed between the substrate and the floating gate; A protective layer is disposed on the surface of the source line.

10. The flash memory device as claimed in claim 8, characterized in that, The flash memory device is a gate-based memory.

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