transistor

Abstract

The transistor involved in the present disclosure comprises: a semiconductor substrate; a source pad, which is arranged on the upper surface of the semiconductor substrate; a plurality of source electrodes, which are arranged on the upper surface of the semiconductor substrate, have a first end connected to the source pad and a second end on the side opposite to the source pad, and are arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate; a plurality of drain electrodes, which are arranged on the upper surface of the semiconductor substrate and are alternately arranged with the plurality of source electrodes in the arrangement direction; a gate electrode, which is arranged on the upper surface of the semiconductor substrate; and a first wiring, which connects the second ends of a plurality of central electrodes, which are arranged in the central part of the semiconductor substrate in the arrangement direction, among the plurality of source electrodes, and is not connected to the second ends of the source electrodes other than the plurality of central electrodes among the plurality of source electrodes.

Description

Technical Field

[0001] The present disclosure relates to transistors. Background Art

[0002] Patent document 1 discloses a multi-finger transistor. The multi-finger transistor comprises: a plurality of gate fingers arranged in an active region on a semiconductor substrate, and a plurality of source fingers and a plurality of drain fingers arranged alternately in the active region across the gate fingers. A gate pad is arranged outside the active region. The gate pad is connected to the gate finger via a gate bus. A source pad is arranged outside the active region and in an area close to the gate pad side relative to the active region. The source pad is connected to the source finger. A drain pad is arranged outside the active region and in an area opposite to the gate pad across the active region. The drain pad is connected to the drain finger. The source pad is grounded through a source via. The multi-finger transistor comprises a circuit for suppressing voltage and current distribution in an area outside the active region and on the drain pad side. The circuit connects the gate finger or the source finger.

[0003] Patent Document 1: Japanese Patent No. 6067151

[0004] Transistors that amplify high-frequency signals, such as GaN HEMT (High Electron Mobility Transistor), are being pushed to high-speed operation and high gain. Along with this high gain, oscillations may sometimes occur in a transistor chip unit simply by applying a bias voltage. In the multi-finger transistor of Patent Document 1, the source fingers are connected together as a source bus for wiring. In addition, in order to avoid contact with the source bus, the drain fingers are connected to the drain pad via a drain air bridge. As a result, the voltage and current distribution generated between the source fingers can be reduced, suppressing loop oscillations.

[0005] Here, a parallel plate capacitor is formed at the intersection of the source bus line and the drain air bridge, so there is a concern that the drain-source capacitance of the high-frequency transistor may increase. Summary of the invention

[0006] An object of the present disclosure is to obtain a transistor capable of suppressing oscillation and reducing drain-source capacitance.

[0007] The transistor involved in the first disclosure comprises: a semiconductor substrate; a source pad, which is arranged on the upper surface of the semiconductor substrate; a plurality of source electrodes, which are arranged on the upper surface of the semiconductor substrate, have a first end connected to the source pad and a second end on the side opposite to the source pad, and are arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate; a plurality of drain electrodes, which are arranged on the upper surface of the semiconductor substrate and are alternately arranged with the plurality of source electrodes in the arrangement direction; a gate electrode, which is arranged on the upper surface of the semiconductor substrate; and a first wiring, which connects the second ends of a plurality of central electrodes, which are arranged in the central part of the semiconductor substrate in the arrangement direction, among the plurality of source electrodes, and is not connected to the second ends of the source electrodes other than the plurality of central electrodes among the plurality of source electrodes.

[0008] The transistor involved in the second disclosure comprises: a semiconductor substrate; a source pad, which is arranged on the upper surface of the semiconductor substrate; a plurality of source electrodes, which are arranged on the upper surface of the semiconductor substrate, have a first end connected to the source pad and a second end on the side opposite to the source pad, and are arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate; a plurality of drain electrodes, which are arranged on the upper surface of the semiconductor substrate and are alternately arranged with the plurality of source electrodes in the arrangement direction; a gate electrode, which is arranged on the upper surface of the semiconductor substrate; and a connection path, which connects the second ends of a pair of outer electrodes arranged at both ends of the arrangement direction among the plurality of source electrodes and is not connected to the second ends of source electrodes other than the pair of outer electrodes among the plurality of source electrodes.

[0009] In the transistor according to the present disclosure, the first wiring or the connection path is selectively provided at a location that strongly affects the suppression of the standing wave. Therefore, it is possible to suppress the oscillation and the drain-source capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view of the transistor involved in Embodiment 1.

[0011] Figure 2 This is a cross-sectional view of the air bridge according to the first embodiment.

[0012] Figure 3 This is a cross-sectional view of the through hole according to the first embodiment.

[0013] Figure 4 This is a diagram showing the relationship between the position of the source electrode and the potential of the second end of the source electrode.

[0014] Figure 5 This diagram shows an amplifier made by combining transistor chips in parallel.

[0015] Figure 6is a top view of a transistor according to a comparative example.

[0016] Figure 7 : is a diagram showing the relationship between the connection position of the source electrode and the resonance frequency.

[0017] Figure 8 It is a diagram showing the relationship between the connection state of the source electrode and the resonance frequency.

[0018] Fig. 9 This is a graph showing the relationship between the input power to the transistor and the power added efficiency.

[0019] Fig.10 It is a top view of the transistor involved in Embodiment 2.

[0020] Fig.11 It is a top view of the transistor involved in Embodiment 3.

[0021] Fig.12 It is a top view of the transistor involved in Embodiment 4.

[0022] Fig.13 It is a top view of the transistor involved in Embodiment 5. DETAILED DESCRIPTION

[0023] The transistors involved in each embodiment are described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and repeated descriptions may be omitted. The following "connected" includes electrical connection.

[0024] Implementation Method 1

[0025] Figure 1 1 is a top view of a transistor 100 according to Embodiment 1. The transistor 100 is a high frequency transistor chip. The transistor 100 is also called a multi-finger transistor. The transistor 100 includes a semiconductor substrate 10. As a material of the semiconductor substrate 10, silicon, silicon carbide, gallium arsenide, gallium nitride, etc. are used. A high electron mobility transistor or a metal-oxide-semiconductor field effect transistor is formed on the semiconductor substrate 10. Here, a high electron mobility transistor (GaN HEMT) using a gallium nitride substrate is taken as an example.

[0026] A source pad 12, a drain pad 16, and a gate pad 34 are provided on the upper surface of the semiconductor substrate 10. The source pad 12 and the gate pad 34 are provided on one side of the upper surface of the semiconductor substrate 10 in the first direction. The drain pad 16 is provided on the other side of the upper surface of the semiconductor substrate 10 in the first direction. In addition, an electrode pad 20 is provided on the other side of the upper surface of the semiconductor substrate 10 in the first direction.

[0027] The drain pad 16 and the gate pad 34 are provided for bonding wires. In addition, a through hole 22 is provided directly below the source pad 12. The through hole 22 connects the source pad 12 and the back metal provided on the back side of the semiconductor substrate 10 opposite to the upper surface to make them conductive. The through hole 22 is formed by a metal layer provided in a through hole formed in the semiconductor substrate 10. In addition, a through hole 24 is provided directly below the electrode pad 20.

[0028] On the upper surface of the semiconductor substrate 10, a plurality of source electrodes 14, a plurality of drain electrodes 18, and a plurality of gate electrodes 36 are provided in a region sandwiched by the source pad 12 and the drain pad 16 in a first direction. The source electrode 14, the drain electrode 18, and the gate electrode 36 are also referred to as source fingers, drain fingers, and gate fingers, respectively. The source pad 12, the drain pad 16, the gate pad 34, the electrode pad 20, the source electrode 14, the drain electrode 18, and the gate electrode 36 are formed of metal.

[0029] The plurality of source electrodes 14 have a first end connected to the source pad 12 and a second end 14a on the opposite side of the source pad 12. The source electrodes 14 extend along a first direction. The plurality of source electrodes 14 are arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate 10. The arrangement direction is, for example, a second direction perpendicular to the first direction.

[0030] The plurality of drain electrodes 18 have a first end connected to the drain pad 16 and a second end opposite to the drain pad 16. The drain electrodes 18 extend along a first direction. The plurality of drain electrodes 18 are arranged along an arrangement direction. The plurality of drain electrodes 18 are alternately arranged with the plurality of source electrodes 14 in the arrangement direction.

[0031] The plurality of gate electrodes 36 have a first end connected to the gate pad 34 and a second end opposite to the gate pad 34. The gate electrodes 36 extend along a first direction. The plurality of gate electrodes 36 are arranged along an arrangement direction. The plurality of gate electrodes 36 are respectively provided between adjacent source electrodes 14 and drain electrodes 18.

[0032] A wiring 26 made of metal is provided on the upper surface of the semiconductor substrate 10. The wiring 26 connects the second ends 14a of the plurality of central electrodes S3 and S4 provided in the central part of the arrangement direction of the semiconductor substrate 10 among the plurality of source electrodes 14. In the present embodiment, the plurality of central electrodes S3 and S4 are a pair of adjacent source electrodes 14 provided in the central part of the semiconductor substrate 10 in the arrangement direction.

[0033] In the transistor 100, an even number of source electrodes S1 to S6 are provided as a plurality of source electrodes 14. At this time, among the plurality of electrodes arranged along the second direction including the plurality of source electrodes 14, the plurality of drain electrodes 18, and the plurality of gate electrodes 36, the electrode provided in the center becomes the drain electrode 18. That is, the electrode provided on the center line extending along the first direction of the chip becomes the drain electrode 18. In such a structure, for example, two source electrodes S3 and S4 sandwiching the central drain electrode 18 become the central electrode connected by the wiring 26.

[0034] The wiring 26 is selectively provided so as to contact only the second ends 14a of the center electrodes S3 and S4 among the plurality of source electrodes 14. That is, the wiring 26 is not connected to the second ends 14a of the source electrodes 14 other than the plurality of center electrodes S3 and S4.

[0035] The wiring 26 intersects the drain electrode 18 provided between the plurality of center electrodes S3 and S4 in a plan view. An air bridge 28 is formed in a portion of the drain electrode 18 intersecting with the wiring 26. Figure 2 2 is a cross-sectional view of the air bridge 28 according to Embodiment 1. The drain electrode 18 crosses the wiring 26 via the air bridge 28. Thus, the drain electrode 18 and the drain pad 16 can be connected.

[0036] Figure 3 2 is a cross-sectional view of the through hole 24 involved in the first embodiment. A back metal 32 is provided on the back side of the semiconductor substrate 10. The through hole 24 penetrates from the upper surface of the semiconductor substrate 10 to the back side. The through hole 24 is formed by a metal layer provided in the through hole formed in the semiconductor substrate 10. The through hole 24 connects the electrode pad 20 and the back metal 32 to make them conductive. In addition, Figure 1 The plurality of vias 24 shown are connected by a backside metal 32 on the backside of the semiconductor substrate 10 .

[0037] The second ends 14a of a pair of outer electrodes S1 and S6 disposed at both ends of the arrangement direction among the plurality of source electrodes 14 are connected to the electrode pad 20 via a wiring 30 formed of metal. Thus, the second ends 14a of the pair of outer electrodes S1 and S6 are connected via the wiring 30, the electrode pad 20, the through hole 24, and the back metal 32.

[0038] In this embodiment, the connection path connecting the second ends 14a of the pair of outer electrodes S1 and S6 is composed of the wiring 30, the electrode pad 20, the through hole 24 and the back metal 32. In addition, the connection path is not connected to the second end 14a of the source electrode 14 other than the pair of outer electrodes S1 and S6.

[0039] The source electrode 14 is connected to the through hole 22 to be at the ground potential. An appropriate bias voltage is applied to the gate electrode 36 and the drain electrode 18. In addition, a high-frequency signal is input to the gate electrode 36. As a result, a high-frequency signal with high power is generated in the drain electrode 18, and an amplification effect is obtained. The application of the bias voltage to the transistor chip from the outside and the input and output of the high-frequency signal are performed via the leads connected to the gate pad 34 and the drain pad 16.

[0040] Next, oscillation that may occur in the transistor 100 when there are no wirings 26 and 30 will be described. Figure 4 1 is a diagram showing the relationship between the position of the source electrode 14 and the potential of the second end 14 a of the source electrode 14 . Figure 4 The vertical axis shows the potential of the second ends 14a of the six source electrodes S1 to S6 when the wirings 26 and 30 are not provided. The horizontal axis shows the positions of the source electrodes S1 to S6 in the chip.

[0041] Figure 4 The figure shows the standing wave of the potential inside the transistor chip at the resonant frequency, i.e., the frequency that causes oscillation. Since the source electrode 14 is connected to the through hole 22, the DC potential is fixed to the ground potential. However, since the source electrode 14 has inductance, the potential of the front end can vary in the millimeter wave band or the quasi-millimeter wave band. In particular, at the resonant frequency of the transistor chip, the potential of the front end may form a Figure 4 Standing waves as shown.

[0042] Figure 4 As an example, the waveform at the moment when the potential of the second end 14a of the source electrode S1 becomes high and the potential of the second end 14a of the source electrode S6 becomes low is shown. As time passes, the potential of the source electrode S1 decreases, the potential of the source electrode S6 increases, and the potential reverses. Such potential changes are repeated periodically. The frequency of the periodic potential change corresponds to the resonant frequency of the transistor chip. If the transistor has a gain at the resonant frequency of the millimeter wave band or the quasi-millimeter wave band, the amplitude of the voltage change may be continuously amplified. As a result, a large voltage amplitude may be generated, causing oscillation and damage to the transistor. Such oscillation of a transistor chip monomer is prone to occur in the millimeter wave band or the quasi-millimeter wave band.

[0043] Figure 5 : is a diagram showing an amplifier obtained by synthesizing transistor chips in parallel. The above oscillation occurs on the same principle as the phenomenon called odd-mode oscillation that occurs in an amplifier obtained by synthesizing multiple transistor chips in parallel. Odd-mode oscillation is an oscillation that occurs when the voltage Vds of the chips connected in parallel change in opposite phases.

[0044] As an inhibitor Figure 4As an example of a means of suppressing the oscillation shown, it is conceivable to reduce the gain of the transistor. However, this goes against the requirement of high gain of the transistor. As another method of suppressing the oscillation, it is conceivable to prevent the standing wave of the potential at the second end 14a of the source electrode 14 from being generated.

[0045] Figure 6 8 is a top view of a transistor 800 according to a comparative example. The difference between the transistor 800 and the transistor 100 is that the wiring 826 connects the second ends 14a of all the source electrodes 14. In addition, the wiring 30 is not provided in the transistor 800. In the transistor 800, the second ends 14a of the source electrodes 14 are connected to each other by the wiring 826 to be short-circuited. Thus, the potential difference between the source electrodes 14 is suppressed, and the generation of standing waves can be suppressed.

[0046] In reality, the source electrodes 14 cannot be short-circuited ideally due to the inductance of the wiring 826. However, the generation of standing waves is suppressed by the wiring 826, and the resonance frequency of the transistor chip is greatly increased. Generally, the higher the frequency, the lower the gain of the transistor. Therefore, oscillation can be suppressed.

[0047] However, the wiring 826 and the air bridge 28 form a parallel plate capacitor. Therefore, the drain-source capacitance increases. The increase in the drain-source capacitance may cause, for example, an undesirable situation that the operating frequency of an amplifier equipped with a high-frequency transistor becomes a narrow band. In particular, if the periphery of the high-frequency transistor is filled with a dielectric in order to improve moisture resistance, the electrostatic capacitance of the portion where the wiring 826 and the air bridge 28 intersect is further increased.

[0048] Furthermore, when a matching circuit appropriately designed for a high-frequency transistor is formed to obtain high power added efficiency, if dielectric filling is performed later, the drain-source capacitance may change, thereby changing the characteristics of the high-frequency transistor and causing a concern that sufficient power added efficiency may not be obtained.

[0049] Therefore, it is preferable to reduce the area of ​​the portion where the wiring 826 overlaps the air bridge 28. However, if the wiring 826 is reduced, oscillation may occur, and the use of a high-frequency transistor itself may become impossible.

[0050] On the other hand, by selectively connecting only a group of source electrodes 14 having a large potential difference, it is expected that the drain-source capacitance can be suppressed and a high oscillation suppression effect can be obtained. Figure 4 The waveform of the standing wave shown is a sine curve. Therefore, the group of source electrodes S3 and S4 disposed in the center of the chip has the largest potential difference among the groups of adjacent source electrodes 14. In addition, the group of source electrodes S1 and S6 at both ends of the chip has the largest potential difference among all the groups of source electrodes 14.

[0051] Figure 7 1 is a diagram showing the relationship between the connection position of the source electrode 14 and the resonance frequency. Figure 7 The following is a result of simulating the resonance frequency when the wiring 30 is not provided and only one pair of adjacent source electrodes 14 is connected by the wiring 26 by electromagnetic field analysis.

[0052] Figure 7 The dashed line shows the calculated resonant frequency when the second ends 14a of all source electrodes 14 are in a released state without connecting the second ends 14a of the source electrodes 14. The simulation revealed that a high resonant frequency is obtained by connecting the source electrodes S3 and S4 among the five connection location candidates.

[0053] Furthermore, the resonance frequency when the source electrodes S1 and S6 are connected without the wiring 26 is calculated by electromagnetic field analysis. Fig.12 At this time, the second end 14 a of the source electrode S1 is connected to the second end 14 a of the source electrode S6 via the connection path of the wiring 30 , the via 24 , the back metal 32 , the via 24 , and the wiring 30 .

[0054] The resonant frequency when the source electrodes S1 and S6 at both ends are not connected, that is, when the second ends 14a of all source electrodes 14 are in a released state, is as follows: Figure 7 The dotted line shows 28.3 GHz. In contrast, the resonant frequency when the second end 14a of the source electrodes S1 and S6 at both ends are connected is calculated to be 32.1 GHz. Fig.12 The structure shown increases the resonant frequency.

[0055] Figure 8 : is a diagram showing the relationship between the connection state of the source electrode 14 and the resonance frequency. Figure 8 In FIG. 1 , the source front end connection indicates the connection state of the second end 14a of the source electrode 14 by the wiring 26. Figure 8 In FIG. 1 , the V / H connection at both ends of the chip indicates whether or not the second ends 14 a of the source electrodes S1 and S6 at both ends are connected via the through-holes 24 .

[0056] In the structure of the transistor 800 in which the second ends 14a of all source electrodes 14 are connected, the resonant frequency is estimated to be 46.2 GHz, and the highest resonant frequency is obtained. The resonant frequency of the structure in which the second ends 14a of all source electrodes 14 are released is 28.3 GHz. In contrast, in the case where the second ends 14a of the source electrodes 14 in the center of the chip are connected and there is no V / H connection at both ends of the chip, the resonant frequency is 34.5 GHz. In addition, in the case where there is no source front end connection and there is a V / H connection at both ends of the chip, the resonant frequency is 32.1 GHz. That is, the resonant frequency is increased by connecting the second ends 14a of the source electrodes 14 in the center of the chip or connecting the second ends 14a of the source electrodes 14 at both ends of the chip.

[0057] In addition, as in the transistor 100 , by using the connection of the second end 14 a of the source electrode 14 in the center of the chip and the connection of the second end 14 a of the source electrode 14 at both ends of the chip in combination, a resonance frequency of about 40 GHz can be obtained.

[0058] It is worth noting that when the front ends of all source electrodes 14 are connected, the resonance frequency does not change even if the front ends of the source electrodes 14 at both ends are further connected to the through holes 24. Figure 6 In the state shown, if the second ends 14a of the source electrodes S1 and S6 at both ends are further connected to the through-holes 24, the number of through-holes connected to the source electrodes 14 increases, and the source inductance decreases, which has been confirmed by both experiments and calculations. However, although the source inductance decreases, the resonant frequency and the ease of oscillation do not change. This is because when the front ends of all the source electrodes 14 are connected to each other, the front ends of the source electrodes S1 and S6 at both ends are also connected on the upper surface of the semiconductor substrate 10. This means that even if the source electrodes S1 and S6 at both ends are further connected through the through-holes 24 and the back metal 32 from this state, no meaningful effect will occur.

[0059] On the other hand, in a structure where the front ends of all source electrodes 14 are in a released state or where the front ends of source electrodes 14 are only partially connected to each other, it was found that the resonance frequency can be increased by connecting the front ends of source electrodes S1 and S6 at both ends to the through hole 24.

[0060] The increase in drain-source capacitance caused by the provision of wiring 26, 826 was estimated by electromagnetic field analysis when the second ends 14a of all source electrodes 14 were in a released state. Here, it was assumed that the surroundings of the transistors were filled with a normal dielectric material. Figure 6In the case of the transistor 800 shown, the calculation result shows that the drain-source capacitance increases by 49 femtofarads due to the wiring 826. In contrast, in the case of the transistor 100 of this embodiment, the increase in the drain-source capacitance due to the wiring 26 is 8 femtofarads.

[0061] Thus, the drain-source capacitance can be suppressed by reducing the area of ​​the portion where the wiring 26 and the air bridge 28 intersect. As described above, in the transistor 100 of this embodiment, the resonance frequency can be increased to suppress oscillation and the drain-source capacitance can be suppressed.

[0062] Fig. 9 1 is a diagram showing the relationship between the input power to the transistor 100 and the power added efficiency. Fig. 9 The vertical axis represents the PAE (Power-Added Efficiency) of the transistor, and the horizontal axis represents the power Pin of the high-frequency signal input to the transistor. Fig. 9 The dotted line represents the calculation result of transistor 800, and the solid line represents the calculation result of transistor 100. Even if the matching circuit is properly designed and manufactured in transistor 800, if the dielectric material is filled later, the characteristics of transistor 800 will change, and the maximum value of the power added efficiency will drop to about 75%. In contrast, in transistor 100 of this embodiment, by suppressing the drain-source capacitance, the characteristic change caused by the filling of the dielectric material is suppressed, and a high power added efficiency of 80% can be maintained. Therefore, the degradation of the performance of transistor 100 can be suppressed.

[0063] Figure 1 to Figure 3 The structure of the transistor 100 shown is an example. For example, the number of source electrodes 14, drain electrodes 18, and gate electrodes 36 is not limited to Figure 1 The shape, position, and number of the source pad 12, the drain pad 16, the gate pad 34, and the electrode pad 20 are not limited. In addition, as described later, the plurality of center electrodes may be any electrodes disposed in the center of the semiconductor substrate 10 in the arrangement direction among the plurality of source electrodes 14, and may be three or more.

[0064] These modifications can be appropriately applied to transistors according to the following embodiments. In addition, since transistors according to the following embodiments have many commonalities with Embodiment 1, the transistors according to the following embodiments will be described centering on the differences from Embodiment 1.

[0065] Implementation Method 2

[0066] Fig.102 is a top view of a transistor 200 according to Embodiment 2. The transistor 200 includes source electrodes S1 to S11 as a plurality of source electrodes 14. Fig.10 The gate electrode 36 is omitted. In the transistor 200 of this embodiment, the electrode provided in the center among the plurality of electrodes arranged along the second direction including the plurality of source electrodes 14, the plurality of drain electrodes 18, and the plurality of gate electrodes 36 is the source electrode S6. Therefore, the source electrode S6 in the center is connected to the second ends 14a of the source electrodes S5 and S7 on both sides by the wiring 26.

[0067] In this embodiment, the standing wave of the potential at the second end 14a of the source electrode 14 is also as follows: Figure 4 Therefore, similarly to the first embodiment, by connecting the second ends 14a of the plurality of source electrodes S5, S6, and S7 provided at the center of the semiconductor substrate 10 in the second direction via the wiring 26, the resonance frequency can be increased to suppress oscillation.

[0068] Implementation 3

[0069] Fig.11 FIG. 3 is a top view of a transistor 300 according to Embodiment 3. The transistor 300 is different from the transistor 100 in that the wiring 30 is not provided. Figure 7 , Figure 8 As shown, even if the source electrodes S1 and S6 at both ends are not connected to the through-hole 24 , the resonance frequency can be increased and the oscillation can be suppressed by connecting the second ends 14 a of the source electrodes 14 at the center.

[0070] This structure can be used when the gain of the transistor 300 is low and oscillation can be suppressed only by increasing the resonance frequency of the wiring 26. In addition, the structure of this embodiment is effective when connection with a through hole is difficult due to the absence of a through hole near the source electrode 14 at both ends of the chip.

[0071] In addition, as in the second embodiment, when the electrode provided at the center of the plurality of electrodes arranged along the second direction is the source electrode 14, Fig.10 As shown, the second ends 14 a of the three source electrodes 14 including the central source electrode 14 and the source electrodes on both sides may also be connected.

[0072] Implementation 4

[0073] Fig.12 FIG. 4 is a top view of a transistor 400 according to Embodiment 4. The transistor 400 is different from the transistor 100 in that the wiring 26 is not provided. Fig.12As shown, even if the second ends 14a of the source electrodes 14 in the center of the chip are not connected to each other, the second ends 14a of the source electrodes 14 at both ends can be connected to the through-holes 24 to increase the resonance frequency and suppress oscillation. In the case where the gain of the transistor 400 is low and oscillation can be suppressed only by connecting the source electrodes 14 at both ends to the through-holes 24, such a structure can be adopted.

[0074] This embodiment can be adopted particularly when an increase in drain-source capacitance due to the intersection of the wiring 26 and the air bridge 28 becomes a problem.

[0075] Implementation method 5

[0076] Fig.13 1 is a top view of a transistor 500 according to Embodiment 5. The difference between the transistor 500 and the transistor 400 lies in the connection path connecting the second ends 14a of a pair of outer electrodes S1 and S6 disposed at both ends in the second direction among the plurality of source electrodes 14. The transistor 500 includes a wiring 530 disposed on the upper surface of the semiconductor substrate 10 and connecting the second ends 14a of the pair of outer electrodes S1 and S6. The wiring 530 is formed of metal.

[0077] The wiring 530 connects the second ends 14a of the pair of outer electrodes S1 and S6 by bypassing other metal layers disposed on the upper surface of the semiconductor substrate 10. Here, the other metal layers include the source pad 12, the drain pad 16, the gate pad 34, the electrode pad 20, the source electrode 14, the drain electrode 18, and the gate electrode 36. Even in such a structure, the resonance frequency can be increased and the oscillation can be suppressed.

[0078] In addition, the wiring 530 is not connected to the second end 14a of the source electrode 14 other than the pair of outer electrodes S1 and S6. In addition, the wiring 530 passes around the periphery of the chip. Therefore, it is possible to avoid crossing with the drain electrode 18 and to avoid the formation of a parallel plate capacitor. Thus, oscillation can be suppressed and the drain-source capacitance can be suppressed. This embodiment can be adopted, for example, when the area restriction of the transistor chip is loose.

[0079] In the transistor 500 , a wiring 26 may be further provided.

[0080] The technical features described in each embodiment may be used in combination as appropriate.

[0081] Description of Reference Numerals

[0082] 10…semiconductor substrate; 12…source pad; 14…source electrode; 14a…second end; 16…drain pad; 18…drain electrode; 20…electrode pad; 22…through hole; 24…through hole; 26…wiring; 28…air bridge; 30…wiring; 32…back metal; 34…gate pad; 36…gate electrode; 100, 200, 300, 400, 500…transistor; 530…wiring; 800…transistor; S1~S11…source electrode.

Claims

1. A transistor, characterized in that: have: Semiconductor substrates; A source pad, disposed on the upper surface of the semiconductor substrate; A plurality of source electrodes, disposed on the upper surface of the semiconductor substrate, having a first end connected to the source pad and a second end on a side opposite to the source pad, and arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate; A plurality of drain electrodes are disposed on the upper surface of the semiconductor substrate and are alternately arranged with the plurality of source electrodes in the arrangement direction; A gate electrode, disposed on the upper surface of the semiconductor substrate; as well as The first wiring connects the second ends of a plurality of central electrodes among the plurality of source electrodes disposed in the central portion of the semiconductor substrate in the arrangement direction, and is not connected to the second ends of source electrodes other than the plurality of central electrodes among the plurality of source electrodes.

2. The transistor according to claim 1, characterized in that The plurality of center electrodes are a pair of adjacent source electrodes provided at a center portion of the semiconductor substrate in the arrangement direction, among the plurality of source electrodes.

3. The transistor according to claim 1 or 2, characterized in that: The first wiring intersects with a drain electrode provided between the plurality of center electrodes among the plurality of drain electrodes in a plan view.

4. The transistor according to any one of claims 1 to 3, characterized in that A connection path is provided for connecting the second ends of a pair of outer electrodes provided at both ends of the arrangement direction among the plurality of source electrodes, The connection path is not connected to the second end of the source electrode other than the pair of outer electrodes among the plurality of source electrodes.

5. The transistor according to claim 4, characterized in that have: A back metal, disposed on the back side of the semiconductor substrate opposite to the upper surface; and a plurality of first through holes extending from the upper surface of the semiconductor substrate to the back surface and connected through the back surface metal on the back surface side of the semiconductor substrate; The second ends of the pair of outer electrodes are connected through the back metal and the plurality of first vias.

6. The transistor according to claim 4, characterized in that A second wiring is provided, the second wiring being provided on the upper surface of the semiconductor substrate and connecting the second ends of the pair of outer electrodes.

7. The transistor according to claim 6, characterized in that The second wiring is connected to the second ends of the pair of outer electrodes by bypassing another metal layer disposed on the upper surface of the semiconductor substrate.

8. The transistor according to any one of claims 1 to 7, characterized in that A second through hole is provided, and the second through hole connects the source pad and a back surface metal provided on the back surface of the semiconductor substrate on the side opposite to the upper surface.

9. A transistor, characterized in that: have: Semiconductor substrates; A source pad, disposed on the upper surface of the semiconductor substrate; A plurality of source electrodes, disposed on the upper surface of the semiconductor substrate, having a first end connected to the source pad and a second end on a side opposite to the source pad, and arranged along an arrangement direction parallel to the upper surface of the semiconductor substrate; A plurality of drain electrodes are disposed on the upper surface of the semiconductor substrate and are alternately arranged with the plurality of source electrodes in the arrangement direction; A gate electrode, disposed on the upper surface of the semiconductor substrate; as well as The connection path connects the second ends of a pair of outer electrodes arranged at both ends of the arrangement direction among the multiple source electrodes, and is not connected to the second ends of source electrodes other than the pair of outer electrodes among the multiple source electrodes.

10. The transistor according to claim 9, characterized in that have: A back metal, disposed on the back side of the semiconductor substrate opposite to the upper surface; and a plurality of first through holes extending from the upper surface of the semiconductor substrate to the back surface and connected through the back surface metal on the back surface side of the semiconductor substrate; The second ends of the pair of outer electrodes are connected through the back metal and the plurality of first vias.

11. The transistor according to claim 9, characterized in that A second wiring is provided, the second wiring being provided on the upper surface of the semiconductor substrate and connecting the second ends of the pair of outer electrodes.

12. The transistor according to claim 11, characterized in that The second wiring is connected to the second ends of the pair of outer electrodes by bypassing another metal layer disposed on the upper surface of the semiconductor substrate.

13. The transistor according to any one of claims 9 to 12, characterized in that: A second through hole is provided, and the second through hole connects the source pad and a back surface metal provided on the back surface of the semiconductor substrate on the side opposite to the upper surface.

Images