A segmented temperature-compensated bandgap reference circuit

Abstract

The present invention discloses a segmented temperature-compensated bandgap reference circuit, comprising an operational amplifier, a bias current source, an NMOS transistor, a PMOS transistor, an NPN crystal, and a resistor. The circuit utilizes the negative temperature characteristics of the base-emitter voltage of a BJT tube and the negative temperature characteristics of the threshold voltage of an NMOS tube, and by reasonably setting segmentation points, performs segmented temperature compensation on a traditional reference temperature curve, thereby realizing a high-order temperature compensation function, obtaining a bandgap reference output voltage with a lower temperature coefficient, and greatly improving the temperature range of the bandgap reference.

Description

Technical Field

[0001] The invention belongs to the technical field of analog circuits, and in particular relates to a segmented temperature-compensated bandgap reference circuit. Background Art

[0002] As the core of the entire circuit, the reference source needs to provide stable and accurate bias for other modules. Its performance has a crucial impact on the performance of the entire circuit or system. Currently, the mainstream reference source on the market is the bandgap reference structure. This adds the base-emitter voltage of a negative temperature coefficient transistor with the base-emitter voltage difference of two positive temperature coefficient transistors to produce a reference output that is approximately independent of temperature.

[0003] A traditional standard bandgap reference circuit typically consists of an amplifier, several bipolar transistors, and resistors. A bipolar transistor with a forward-biased base-emitter has a base-emitter voltage with a negative temperature characteristic. The base-emitter voltage difference between the two bipolar transistors has a first-order positive temperature coefficient. The base-emitter voltage of the bipolar transistor with a negative temperature coefficient is summed with the base-emitter voltage difference between the two bipolar transistors with a positive temperature coefficient. By setting an appropriate compensation coefficient using the resistor ratio, the temperature coefficient of the summed reference voltage is approximately zero. A typical bandgap reference output voltage is V ref =(1+R A / R B )·V T lnN+V BE , where N is a constant proportional to the emitter junction area of the two bipolar transistors, V T is the thermal voltage coefficient.

[0004] Further taking the first-order partial derivative of the bandgap reference output voltage with respect to temperature T, we get the following equation:

[0005]

[0006] Where V g0 is the base-emitter voltage of the bipolar transistor when the temperature is 0K; T R is a fixed temperature; η is a constant related to the process and has nothing to do with temperature; α is the exponent of the collector current to the absolute temperature T; k is the Boltzmann constant; q is the charge of the electron. As can be seen from the formula, except for the last term, the rest are constants that are independent of the temperature T. Therefore, the traditional bandgap reference structure often ignores the influence of the last term and only performs first-order temperature compensation to obtain a bandgap reference output voltage with approximately zero temperature drift. However, after Taylor expansion, the last term of the equation is a multi-order term related to temperature T. The first-order temperature compensation cannot eliminate the influence of the high-order terms of temperature T. Therefore, the bandgap reference output voltage often presents a downward-opening parabola, such as Figure 1 As shown, the actual temperature drift is larger.

[0007] As integrated circuits continue to increase in speed and precision, the performance requirements for reference sources are becoming increasingly stringent. Traditional bandgap reference structures with first-order temperature compensation are no longer able to meet these demands. Therefore, it is necessary to develop a higher-order temperature compensation circuit structure to achieve a bandgap reference output voltage with a lower temperature coefficient. Summary of the Invention

[0008] In order to overcome the shortcomings of the existing technology, the present invention provides a segmented temperature-compensated bandgap reference circuit, including an operational amplifier, a bias current source, an NMOS transistor, a PMOS transistor, an NPN crystal and a resistor; the circuit of the present invention utilizes the negative temperature characteristics of the base-emitter voltage of a BJT tube and the negative temperature characteristics of the threshold voltage of an NMOS tube, and through the reasonable setting of segmentation points, performs segmented temperature compensation on the traditional reference temperature curve, realizes a high-order temperature compensation function, obtains a bandgap reference output voltage with a lower temperature coefficient, and greatly improves the temperature range of the bandgap reference.

[0009] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0010] A segmented temperature-compensated bandgap reference circuit includes an operational amplifier U1, a bias current source I1, NMOS transistors N1, N2, N3, and N4, PMOS transistors P1, P2, P3, P4, P5, P6, and P7, NPN transistors Q1, Q2, Q3, and Q4, and resistors R1, R2, and R3;

[0011] The source of the PMOS transistor P1 is connected to the power supply VCC, the gate is powered by the bias voltage Vb1, and the drain is interconnected with the collector and base of the NPN transistor Q1 and the base of the NPN transistor Q2;

[0012] The emitter of the NPN transistor Q1 is connected to the collector and base of the NPN transistor Q3 at the same time;

[0013] The emitter of the NPN transistor Q3 is grounded;

[0014] The emitter of the NPN transistor Q2 is connected to one end of the resistor R1, and the collector is interconnected with the gate and drain of the PMOS transistor P2 and the gate of the PMOS transistor P3;

[0015] The other end of the resistor R1 is grounded;

[0016] The source of the PMOS transistor P2 is connected to the power supply VCC;

[0017] The source of the PMOS transistor P3 is connected to the power supply VCC, and the drain is connected to the source of the PMOS transistor P4;

[0018] The gate of the PMOS transistor P4 and the gate of the PMOS transistor P7 are both powered by the bias voltage Vb2; the drain of the PMOS transistor P4 is interconnected with the first input terminal of the bias current source I1, the source of the NMOS transistor N1, the drain and gate of the NMOS transistor N3, and the gate of the NMOS transistor N4;

[0019] The second input terminal of the bias current source I1 is grounded;

[0020] The gate of the NMOS transistor N1 is connected to the gate of the NMOS transistor N2, powered by the bias voltage Vb3, and the drain is interconnected with the drain of the NMOS transistor N2, the gate and drain of the PMOS transistor P5, and the gate of the PMOS transistor P6;

[0021] The source of the NMOS transistor N3 is grounded;

[0022] The drain of the NMOS transistor N4 is connected to the source of the NMOS transistor N2, and the source of the NMOS transistor N4 is grounded;

[0023] The source of the PMOS transistor P5 is connected to the power supply VCC;

[0024] The source of the PMOS transistor P6 is connected to the power supply VCC, and the drain is connected to the source of the PMOS transistor P7;

[0025] The drain of the PMOS transistor P7 is simultaneously interconnected with one end of the resistor R2, one end of the resistor R3, and the positive input terminal of the operational amplifier U1;

[0026] The other end of the resistor R2 is interconnected with the negative input terminal and the output terminal of the operational amplifier U1;

[0027] The other end of the resistor R3 is connected to the collector and base of the NPN transistor Q4;

[0028] The emitter of the NPN transistor Q4 is grounded.

[0029] Preferably, the positive and negative input terminals of the operational amplifier U1 are formed by two NPN pairs of transistors inside the operational amplifier, and the emitter junction areas of the two NPN pairs of transistors inside the operational amplifier are set to be 1:8.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention utilizes the negative temperature characteristics of the BJT tube base-emitter voltage and the negative temperature characteristics of the NMOS tube threshold voltage, and through reasonable setting of segmentation points, performs segmented temperature compensation on the traditional reference temperature curve, realizes high-order temperature compensation function, obtains a bandgap reference output voltage with a lower temperature coefficient, and greatly improves the temperature range of the bandgap reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of the traditional bandgap reference output voltage waveform.

[0033] Figure 2 The present invention provides a schematic structural diagram of a segmented temperature compensation bandgap reference circuit.

[0034] Figure 3 The present invention provides a schematic diagram of the output voltage waveform of a segmented temperature-compensated bandgap reference circuit. DETAILED DESCRIPTION

[0035] The present invention will be further described below with reference to the accompanying drawings and examples.

[0036] The object of the present invention is to provide a segmented temperature-compensated bandgap reference circuit to solve the problem of large temperature drift in conventional bandgap reference circuits.

[0037] The present invention provides a segmented temperature-compensated bandgap reference circuit, comprising an operational amplifier U1, a bias current source I1, NMOS transistors N1 to N4, PMOS transistors P1 to P7, NPN transistors Q1 to Q4, and resistors R1 to R3. The source of PMOS transistor P1 is connected to a power supply VCC, the gate is powered by a bias voltage Vb1, and the drain is interconnected with the collector and base of NPN transistor Q1 and the base of NPN transistor Q2. The emitter of NPN transistor Q1 is connected to the collector and base of NPN transistor Q3. The emitter of NPN transistor Q3 is grounded. The emitter of NPN transistor Q2 is connected to a first input terminal of resistor R1, and the collector is interconnected with the gate and drain of PMOS transistor P2 and the gate of PMOS transistor P3. The second input terminal of resistor R1 is grounded. The source of PMOS transistor P2 is connected to power supply VCC. The source of PMOS transistor P3 is connected to power supply VCC, and the drain is connected to the source of PMOS transistor P4. The gate of PMOS transistor P4 is connected to the gate of PMOS transistor P7 and is powered by bias voltage Vb2. Its drain is interconnected with the first input terminal of bias current source I1, the source of NMOS transistor N1, the drain and gate of NMOS transistor N3, and the gate of NMOS transistor N4. The second input terminal of bias current source I1 is grounded. The gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2 and is powered by bias voltage Vb3. Its drain is interconnected with the drain of NMOS transistor N2, the gate and drain of PMOS transistor P5, and the gate of PMOS transistor P6. The source of NMOS transistor N3 is grounded. The drain of NMOS transistor N4 is connected to the source of NMOS transistor N2, and the source of NMOS transistor N4 is grounded. The source of PMOS transistor P5 is connected to power supply VCC. The source of PMOS transistor P6 is connected to power supply VCC, and its drain is connected to the source of PMOS transistor P7. The drain of PMOS transistor P7 is connected to the second input terminal of resistor R2, the first input terminal of resistor R3, and the positive input terminal of op amp U1. The first input terminal of resistor R2 is connected to the negative input terminal and output terminal of op amp U1. The second input terminal of resistor R3 is connected to the collector and base of NPN transistor Q4. The emitter of NPN transistor Q4 is grounded. Specific embodiment:

[0039] The present invention provides a segmented temperature compensation bandgap reference circuit, the circuit structure of which is as follows: Figure 2As shown. It includes op amp U1, bias current source I1, NMOS transistors N1 to N4, PMOS transistors P1 to P7, NPN transistors Q1 to Q4, and resistors R1 to R3. The source of PMOS transistor P1 is connected to power supply VCC, the gate is powered by bias voltage Vb1, and the drain is interconnected with the collector and base of NPN transistor Q1 and the base of NPN transistor Q2. The emitter of NPN transistor Q1 is connected to the collector and base of NPN transistor Q3. The emitter of NPN transistor Q3 is grounded. The emitter of NPN transistor Q2 is connected to the first input terminal of resistor R1, and the collector is interconnected with the gate and drain of PMOS transistor P2 and the gate of PMOS transistor P3. The second input terminal of resistor R1 is grounded. The source of PMOS transistor P2 is connected to power supply VCC. The source of PMOS transistor P3 is connected to power supply VCC, and the drain is connected to the source of PMOS transistor P4. The gate of PMOS transistor P4 is connected to the gate of PMOS transistor P7 and is powered by bias voltage Vb2. Its drain is interconnected with the first input terminal of bias current source I1, the source of NMOS transistor N1, the drain and gate of NMOS transistor N3, and the gate of NMOS transistor N4. The second input terminal of bias current source I1 is grounded. The gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2 and is powered by bias voltage Vb3. Its drain is interconnected with the drain of NMOS transistor N2, the gate and drain of PMOS transistor P5, and the gate of PMOS transistor P6. The source of NMOS transistor N3 is grounded. The drain of NMOS transistor N4 is connected to the source of NMOS transistor N2, and the source of NMOS transistor N4 is grounded. The source of PMOS transistor P5 is connected to power supply VCC. The source of PMOS transistor P6 is connected to power supply VCC, and its drain is connected to the source of PMOS transistor P7. The drain of PMOS transistor P7 is connected to the second input terminal of resistor R2, the first input terminal of resistor R3, and the positive input terminal of op amp U1. The first input terminal of resistor R2 is connected to the negative input terminal and output terminal of op amp U1. The second input terminal of resistor R3 is connected to the collector and base of NPN transistor Q4. The emitter of NPN transistor Q4 is grounded.

[0040] The positive and negative input terminals of the operational amplifier U1 are composed of two NPN pairs of tubes inside the operational amplifier. If the emitter junction area of the two NPN pairs of tubes inside the operational amplifier is set to 1:8, then according to the working principle of the operational amplifier, the voltage difference between the positive and negative input terminals is V T ln8, so the output voltage V ref =(1+R3 / R2)V T ln8+V BE4 +I X R3, where V BE4 is the base-emitter voltage of NPN transistor Q4, I Xis the compensation current flowing through P7 and R3. Figure 3 At low temperatures, the base-emitter voltage of Q3 is large, and the current flowing through P3 is V BE3 / R1, its value is greater than the bias current I1, the difference current flows into N3, and after being mirrored by N4 and P5, forms a negative temperature characteristic compensation current I X , that is I X =V BE3 / R1-I1(T<Ts). As the temperature rises, the compensation current decreases. When the compensation current is zero, the drain voltage of P4 is pulled down, N3 is turned off, and N1 is turned on. Due to the threshold voltage V th The negative temperature characteristic of the current forms a positive temperature characteristic compensation current after passing through N1, P5, and P6, that is, I X =μ n C OX W N1 (Vb3-V th ) 2 / 2L N1 (T>Ts), where μ n is the carrier mobility; C OX is the gate oxide capacitance per unit area; W N1 / L N1 is the width-to-length ratio of the N1 tube, V th is the threshold voltage of N1 tube.

[0041] It can be seen that by adjusting the value of R1, T S By adjusting the aspect ratio of P5 and P6, the maximum value of the compensation current can be changed. Therefore, under the CMOS process, high-order temperature compensation of the bandgap reference output voltage is achieved, and a temperature drift coefficient of less than 10ppm is obtained, realizing the low temperature drift performance of the bandgap reference.

Claims

1. A segmented temperature compensated bandgap reference circuit, characterized in that: Including operational amplifier U1, bias current source I1, NMOS transistors N1, N2, N3, N4, PMOS transistors P1, P2, P3, P4, P5, P6, P7, NPN transistors Q1, Q2, Q3, Q4, resistors R1, R2, R3; The source of the PMOS transistor P1 is connected to the power supply VCC, the gate is powered by the bias voltage Vb1, and the drain is interconnected with the collector and base of the NPN transistor Q1 and the base of the NPN transistor Q2; The emitter of the NPN transistor Q1 is connected to the collector and base of the NPN transistor Q3 at the same time; The emitter of the NPN transistor Q3 is grounded; The emitter of the NPN transistor Q2 is connected to one end of the resistor R1, and the collector is interconnected with the gate and drain of the PMOS transistor P2 and the gate of the PMOS transistor P3; The other end of the resistor R1 is grounded; The source of the PMOS transistor P2 is connected to the power supply VCC; The source of the PMOS transistor P3 is connected to the power supply VCC, and the drain is connected to the source of the PMOS transistor P4; The gate of the PMOS transistor P4 and the gate of the PMOS transistor P7 are both powered by the bias voltage Vb2; the drain of the PMOS transistor P4 is interconnected with the first input terminal of the bias current source I1, the source of the NMOS transistor N1, the drain and gate of the NMOS transistor N3, and the gate of the NMOS transistor N4; The second input terminal of the bias current source I1 is grounded; The gate of the NMOS transistor N1 is connected to the gate of the NMOS transistor N2, powered by the bias voltage Vb3, and the drain is interconnected with the drain of the NMOS transistor N2, the gate and drain of the PMOS transistor P5, and the gate of the PMOS transistor P6; The source of the NMOS transistor N3 is grounded; The drain of the NMOS transistor N4 is connected to the source of the NMOS transistor N2, and the source of the NMOS transistor N4 is grounded; The source of the PMOS transistor P5 is connected to the power supply VCC; The source of the PMOS transistor P6 is connected to the power supply VCC, and the drain is connected to the source of the PMOS transistor P7; The drain of the PMOS transistor P7 is simultaneously interconnected with one end of the resistor R2, one end of the resistor R3, and the positive input terminal of the operational amplifier U1; The other end of the resistor R2 is interconnected with the negative input terminal and the output terminal of the operational amplifier U1; The other end of the resistor R3 is connected to the collector and base of the NPN transistor Q4; The emitter of the NPN transistor Q4 is grounded.

2. The segmented temperature compensated bandgap reference circuit according to claim 1, characterized in that: The positive and negative input terminals of the operational amplifier U1 are composed of two NPN pairs of transistors inside the operational amplifier, and the emitter junction area of the two NPN pairs of transistors inside the operational amplifier is set to 1:8.

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