Methods, circuits, and electronic devices for frequency division clock phase synchronization

Abstract

This invention provides a method for synchronizing the phase of a divided clock in a multi-frequency clock system, a related synchronization control circuit, a synchronization control sub-circuit, and an electronic device. The method may include: performing a frequency division operation based on a source clock to generate a first divided clock and a second divided clock; performing a phase relationship detection on the first divided clock based on the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting either the second divided clock or an inverted signal of the second divided clock based on the second phase selection result output signal for further use by a physical layer circuit.

Description

Technical Field

[0001] This invention relates to the synchronization of a divided / frequency-divided clock, and more particularly to a method for synchronizing the phase of a divided / frequency-divided clock in a multi-divided-clock system, a related synchronization control circuit, a related synchronization control sub-circuit, and related electronic devices. Background Technology

[0002] According to related technologies, a single clock can be used by multiple circuits in an electronic device, and in particular, it can be converted into multiple frequency-divided clocks for further use in these circuits. However, some problems may occur. For example, the multiple frequency-divided clocks may not be synchronized with each other, which may cause the electronic device to malfunction or fail to operate properly. Some suggestions have been proposed in related technologies to attempt to solve this problem, but these may lead to additional problems such as certain side effects. Therefore, a novel method and related architecture are needed to realize an electronic device with reliable frequency-divided clock synchronization control without or with a low probability of causing side effects. Summary of the Invention

[0003] One object of the present invention is to provide a method for synchronizing the phase of a divided clock in a multi-frequency clock system, a related synchronization control circuit, a synchronization control sub-circuit, and related electronic devices to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for performing frequency division clock phase synchronization in a frequency division clock system. The method may include: using a first frequency divider in a first synchronization control sub-circuit to perform a first frequency division operation based on a source clock to generate a first frequency division clock; using a second frequency divider in a second synchronization control sub-circuit to perform a second frequency division operation based on the source clock to generate a second frequency division clock; outputting the first frequency division clock to the second synchronization control sub-circuit using the first synchronization control sub-circuit; outputting a first phase selection result output signal to the second synchronization control sub-circuit using the first synchronization control sub-circuit, wherein the logic value carried in the first phase selection result output signal indicates a first phase selection result of the first synchronization control sub-circuit; and using a phase relationship detection circuit in the second synchronization control sub-circuit to perform a first phase selection operation based on the first frequency division clock. The second-divided clock performs a phase relationship detection on the first-divided clock to generate a phase relationship detection result signal, wherein the logic value carried in the phase relationship detection result signal indicates a phase relationship detection result of the second synchronization control sub-circuit; a logic gate in the second synchronization control sub-circuit performs a logic operation on the first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal, wherein the logic value carried in the second phase selection result output signal indicates a second phase selection result of the second synchronization control sub-circuit; and the second synchronization control sub-circuit outputs one of the second-divided clock and an inverted signal of the second-divided clock according to the second phase selection result output signal, for further use by a physical layer circuit equipped with the second synchronization control sub-circuit.

[0005] According to certain embodiments, the present invention further provides a synchronization control circuit operating according to the above method, wherein the synchronization control circuit may include a plurality of synchronization control sub-circuits. For example, the plurality of synchronization control sub-circuits may have the same circuit architecture and be coupled to each other, and in particular, may be used to synchronize the frequency division clocks generated by the respective frequency dividers of the plurality of synchronization control sub-circuits, wherein the plurality of synchronization control sub-circuits includes the first synchronization control sub-circuit and the second synchronization control sub-circuit.

[0006] At least one embodiment of the present invention provides a synchronization control sub-circuit, wherein the synchronization control sub-circuit is one of a plurality of synchronization control sub-circuits in a synchronization control circuit. The synchronization control sub-circuit may include a frequency divider, a phase relationship detection circuit coupled to the frequency divider, a logic gate coupled to the phase relationship detection circuit, and a synchronized divided output clock pin. For example, the frequency divider can be used to perform a frequency division operation based on a source clock to generate a divided clock; the phase relationship detection circuit can be used to perform phase relationship detection on another divided clock output by another synchronization control sub-circuit based on the divided clock to generate a phase relationship detection result signal, wherein the logic value carried by the phase relationship detection result signal indicates a phase relationship detection result of the synchronization control sub-circuit; the logic gate can be used to perform a logic operation on a first phase selection result output signal output by the other synchronization control sub-circuit and the phase relationship detection result signal to generate a second phase selection result output signal, wherein the logic value carried by the first phase selection result output signal indicates a first phase selection result of the other synchronization control sub-circuit, and the logic value carried by the second phase selection result output signal indicates a second phase selection result of the synchronization control sub-circuit; and through the synchronization divided clock output pin, the synchronization control sub-circuit outputs one of the divided clock and an inverted signal of the divided clock based on the second phase selection result output signal, for further use by a physical layer circuit having the synchronization control sub-circuit.

[0007] According to certain embodiments, the present invention further provides an electronic device including the above-described synchronization control sub-circuit, wherein the electronic device may include a memory and a plurality of physical layer circuits coupled to the memory. For example, the memory may be used to temporarily store information for the electronic device; and the plurality of physical layer circuits may be used to access the memory to perform operations on the electronic device, wherein each of the plurality of physical layer circuits includes a corresponding synchronization control sub-circuit among the plurality of synchronization control sub-circuits.

[0008] One advantage of this invention is that, through a carefully designed control mechanism, the method of this invention can avoid any phase inversion errors in the respective frequency division clocks of the multiple sub-circuits of the electronic device, and thus ensures that the electronic device operates correctly under various conditions. Furthermore, when the skew between the frequency division clocks is greater than 1T of the reference clock, the method of this invention can avoid false lock-up problems. Compared to related technologies, the method of this invention can realize an electronic device with robust frequency division clock synchronization control without or with a low likelihood of side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an electronic device with frequency division clock synchronization control function according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of an electronic device with frequency division clock synchronization control function according to another embodiment of the present invention.

[0011] Figure 3 According to an embodiment of the present invention, a synchronization result staticizing and automatic configuration control scheme for a method of performing frequency division clock phase synchronization in a frequency division clock system is illustrated.

[0012] Figure 4 Illustration based on an embodiment of the present invention Figure 3 The synchronization result shown is the in-phase detection result involved in the static and automatic configuration control scheme.

[0013] Figure 5 Illustration based on an embodiment of the present invention Figure 3 The synchronization result shown is static and the phase-reversal detection result involved in the automatic configuration control scheme.

[0014] Figure 6 A first configurable synchronization line control scheme of the method is illustrated according to an embodiment of the present invention.

[0015] Figure 7 A second configurable synchronization line control scheme of the method is illustrated according to an embodiment of the present invention.

[0016] Figure 8 A third configurable synchronization line control scheme of the method is illustrated according to an embodiment of the present invention.

[0017] Figure 9 A workflow of the method is illustrated according to an embodiment of the present invention. Detailed Implementation

[0018] Figure 1This is a schematic diagram of an electronic device 100 with frequency division clock synchronization control function according to an embodiment of the present invention. The electronic device 100 may include a memory such as a Dynamic Random Access Memory (DRAM) 110 and multiple physical layer circuits such as PHY(0), PHY(1), and PHY(2). The memory, such as DRAM 110, can be used to temporarily store information for the electronic device, while the multiple physical layer circuits, such as PHY(0), PHY(1), and PHY(2), can access the memory, such as DRAM 110, to perform operations of the electronic device 100. For example:

[0019] (1) The physical layer circuit PHY(0) may include a synchronization control sub-circuit (SCSC) with a frequency divider DIV(0), such as a synchronization module SM(0), and include a clock generator CG(0).

[0020] (2) The physical layer circuit PHY(1) may include a synchronization control sub-circuit with a frequency divider DIV(1), such as a synchronization module SM(1), and include a clock generator CG(1).

[0021] (3) The physical layer circuit PHY(2) may include a synchronization control sub-circuit with a frequency divider DIV(2), such as a synchronization module SM(2), and include a clock generator CG(2); and so on;

[0022] Each of the multiple physical layer circuits PHY(0), PHY(1), PHY(2), etc., may include a corresponding synchronization control sub-circuit from among the multiple synchronization control sub-circuits of a synchronization control circuit of the electronic device 100, but the present invention is not limited thereto. In addition, the clock generators CG(0), CG(1), CG(2), etc., may generate additional clocks based on the frequency division clocks output by the synchronization modules SM(0), SM(1), SM(2), etc., for further use by the physical layer circuits PHY(0), PHY(1), PHY(2), etc.

[0023] For ease of understanding, assume that the symbol “X” represents a positive integer greater than one. The synchronization control circuit of the electronic device 100 may include X synchronization control sub-circuits such as X synchronization modules {SM(0),…,SM(X-1)}, and the X physical layer circuits {PHY(0),…,PHY(X-1)} of the electronic device 100 may each include the X synchronization control sub-circuits having X frequency dividers {DIV(0),…,DIV(X-1)}, such as X synchronization modules {SM(0),…,SM(X-1)}, and each including X clock generators {CG(0),…,CG(X-1)}. In particular, the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),...,SM(X-1)}, may have the same circuit architecture, and the synchronization control sub-circuit is configurable to allow the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),...,SM(X-1)}, to be coupled to each other to form the synchronization control circuit for synchronizing the frequency division clock generated by the respective frequency dividers {DIV(0),...,DIV(X-1)} of the X synchronization control sub-circuits. For example, in the synchronization control circuit, any two adjacent synchronization control sub-circuits of the X synchronization control sub-circuits, such as any two adjacent synchronization modules SM(x0) and SM(x0+1) of the X synchronization modules {SM(0),...,SM(X-1)}, can exchange signals in a manner similar to the respective synchronization control sub-circuits of the physical layer circuits PHY(0) and PHY(1) (e.g., synchronization modules SM(0) and SM(1)) or similar to the respective synchronization control sub-circuits of the physical layer circuits PHY(1) and PHY(2) (e.g., synchronization modules SM(1) and SM(2)).

[0024] Figure 2 This is a schematic diagram of an electronic device 200 with frequency division clock synchronization control function according to another embodiment of the present invention. Figure 2 The electronic device 200 shown can be used as Figure 1In the example of the electronic device 100 shown, in particular, among the aforementioned X physical layer circuits {PHY(0),...,PHY(X-1)}, physical layer circuit PHY(0) can be implemented as a Command / Address ("address" may also be referred to as "address") physical layer circuit APHY, and subsequent physical layer circuits such as (X-1) physical layer circuits {PHY(1),PHY(2),...,PHY(X-1)} can be implemented as data physical layer circuits {DPHY(1),DPHY(2),...,DPHY(X-1)} respectively, but the present invention is not limited thereto. In some embodiments, the number of the X physical layer circuits {PHY(0),...,PHY(X-1)} can be very small, for example, X = 3. In this case, the (X-1) physical layer circuits {PHY(1),PHY(2),...,PHY(X-1)} can represent (2-1) physical layer circuits {PHY(1),PHY(2)}, where the physical layer circuits {PHY(1),PHY(2)} can be implemented as data physical layer circuits {DPHY(1),DPHY(2)} respectively.

[0025] Figure 3 According to an embodiment of the present invention, a synchronization result staticizing and automatic configuration control scheme for a method of performing frequency division clock phase synchronization in a frequency division clock system is illustrated. Figure 3 The synchronization module 300 shown can be used as an example of the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)}. In particular, the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)} can have the same circuit architecture as the synchronization module 300.

[0026] The synchronization module 300 may include a frequency divider such as a divide-by-2 frequency divider 310 (denoted as "DIV÷2" for simplicity), multiple delay line circuits 320L and 320R, multiple phase relationship detection circuits 330L and 330R, and a configurable phase control circuit 340. For example, each delay line circuit in the delay line circuits 320L and 320R may include multiple delay units such as an even number of inverters, but the invention is not limited thereto. Additionally, the phase relationship detection circuits 330L and 330R may be implemented using delay circuits (denoted as "delay" for simplicity), D-type flip-flops, etc., wherein the phase relationship detection circuit 330L may include a delay circuit 331L and a D-type flip-flop 332L, and the phase relationship detection circuit 330R may include a delay circuit 331R and a D-type flip-flop 332R. Furthermore, the configurable phase control circuit 340 may include multiplexer circuits 341, 342, and 345, an XOR gate 343, and an inverter 344. For example... Figure 3 As shown, the synchronization module 300 may also include multiple terminals such as multiple pins, and Table 1 shows the pin names of these multiple pins, along with descriptions of these pins and / or their signals.

[0027] Table 1

[0028]

[0029] For ease of understanding, the signals transmitted through these multiple pins can have the same name printed in italics, and the related operations can be explained as follows:

[0030] (1) The input reference clock pin i_ref_clk (which can be written as i_ref_clk(x0), i_ref_clk(x0+1), and i_ref_clk(x0+2) in the synchronization modules SM(x0), SM(x0+1), and SM(x0+2), respectively) is used to receive an input reference clock signal i_ref_clk (for example, Figure 1 The source clock CLK shown SOURCE The half-frequency divider 310 can divide the input reference clock signal i_ref_clk by one to generate a divided clock at its output terminal, which can be input to the delay line circuits 320L and 320R and the configurable phase control circuit 340.

[0031] (2) The reset pin i_rstb (which can be written as i_rstb(x0), i_rstb(x0+1) and i_rstb(x0+2) in the synchronization modules SM(x0), SM(x0+1) and SM(x0+2) respectively) is used to receive a reset signal i_rstb for resetting the half-frequency divider 310;

[0032] (3) The previous stage phase selection result input pin i_sync_pre_result (which can be written as i_sync_pre_result(0), i_sync_pre_result(1), i_sync_pre_result(2), i_sync_pre_result(x0), i_sync_pre_result(x0+1), and i_sync_pre_result(x0+2) respectively in the synchronization modules SM(0), SM(1), SM(2), SM(x0), SM(x0+1), and SM(x0+2)) is used to receive a previous stage phase selection result input signal i_sync_pre_result, such as the previous stage phase selection result input signal, where i_sync_pre_result is the input signal of the previous stage phase selection result. Figure 1 Taking the connection method shown as an example, if the current level (that is, the synchronization module 300) represents the synchronization module SM(1), then the previous level can represent the synchronization module SM(0), or if the current level (that is, the synchronization module 300) represents the synchronization module SM(2), then the previous level can represent the synchronization module SM(1), and so on.

[0033] (4) The current stage phase selection result output pin o_sync_result (which can be written as o_sync_result(0), o_sync_result(1), o_sync_result(2), o_sync_result(x0), o_sync_result(x0+1), and o_sync_result(x0+2) respectively in the synchronization modules SM(0), SM(1), SM(2), SM(x0), SM(x0+1), and SM(x0+2)) is used to output a current stage phase selection result output signal o_sync_result, such as the current stage phase selection result input signal, where... Figure 1 Taking the connection method shown as an example, the current level (that is, the synchronization module 300) can represent any one of the synchronization modules SM(0), SM(1), SM(2), etc.;

[0034] (5) The automatic synchronization enable pin i_sync_auto is used to receive an automatic synchronization enable signal i_sync_auto. The logic value carried by the automatic synchronization enable signal i_sync_auto controls the multiplexer circuit 342 to enable or disable the automatic synchronization of the synchronization module 300. Multiple candidate logic values ​​0 and 1 (e.g., 1'b0 and 1'b1) can respectively indicate whether automatic synchronization is enabled or disabled. Specifically, ... Figure 1 Taking the connection method shown as an example, if the current level (that is, the synchronization module 300) represents the synchronization module SM(0), then this logic value can be set to the candidate logic value 0 to control the multiplexer circuit 342 to select the input from the phase selection manual control pin i_phase_sel as the current level phase relationship detection result signal current_rst; otherwise, this logic value can be set to the candidate logic value 1 to control the multiplexer circuit 342 to select the input from the multiplexer circuit 341 as the current level phase relationship detection result signal current_rst.

[0035] (6) The phase selection manual control pin i_phase_sel is used to receive a phase selection manual control signal i_phase_sel, so as to manually control (e.g., force set) the logic value of the current phase relationship detection result signal current_rst by means of the logic value carried by the phase selection manual control signal i_phase_sel. The multiple candidate logic values ​​0 and 1 (e.g. 1'b0 and 1'b1) of the logic value carried by the phase selection manual control signal i_phase_sel can indicate in-phase and out-of-phase respectively, so as to control the multiplexer circuit 345 to select the corresponding input to control the phase of the frequency division clock output by the synchronous frequency division output clock pin by2_clk;

[0036] (7) The synchronization source selection control pin i_sync_source_sel is used to receive a synchronization source selection control signal i_sync_source_sel, so as to automatically control (e.g., automatically set) the logic value of the current stage phase relationship detection result signal current_rst to be equal to the data output signal Q by using the logic value carried by the synchronization source selection control signal i_sync_source_sel. L Or data output signal Q R The logic value, wherein multiple candidate logic values ​​0 and 1 (e.g., 1'b0 and 1'b1) carried by the synchronization source selection control signal i_sync_source_sel can respectively indicate the left side (e.g., the synchronization source is the left module) and the right side (e.g., the synchronization source is the right module), to control the multiplexer circuit 341 to select the corresponding input (e.g., the data output signal Q).L Or Q R The current_rst signal serves as the current-level phase relationship detection result signal.

[0037] (8) The synchronous frequency division output clock pin by2_clk (which can be written as by2_clk(0), by2_clk(1), by2_clk(2), by2_clk(x0), by2_clk(x0+1) and by2_clk(x0+2) respectively in the synchronous modules SM(0), SM(1), SM(2), SM(x0), SM(x0+1) and SM(x0+2)) is used to output the corresponding input selected by the multiplexer circuit 345, such as the frequency division clock generated by the half-frequency divider 310 or the inverted signal generated by the inverter 344, as a synchronous frequency division output clock by2_clk, wherein the inverter 344 can perform an inverting operation on the frequency division clock generated by the half-frequency divider 310 to generate the inverted signal;

[0038] (9) The left-side divided clock input pin i_sync_left (which can be written as i_sync_left(x0), i_sync_left(x0+1), and i_sync_left(x0+2) in the synchronization modules SM(x0), SM(x0+1), and SM(x0+2), respectively) is used to receive a left-side divided clock input signal i_sync_left from the left-side module as an external clock CLK. EXTERNAL_L When the current level is located to the left of the current level, the previous level can be regarded as the module to the left.

[0039] (10) The right-side frequency divider clock input pin i_sync_right (which can be written as i_sync_right(0), i_sync_right(1), i_sync_right(2), i_sync_right(x0), i_sync_right(x0+1), and i_sync_right(x0+2) respectively in the synchronization modules SM(0), SM(1), SM(2), SM(x0), SM(x0+1), and i_sync_right(x0+2) respectively) is used to receive a right-side frequency divider clock input signal i_sync_right from the right-side module as an external clock CLK. EXTERNAL_R When the current level is located to the right of the current level, the previous level can be regarded as the module to the right;

[0040] (11) The left-side frequency divider clock output pin o_sync_left (which can be written as o_sync_left(0), o_sync_left(1), o_sync_left(2), o_sync_left(x0), o_sync_left(x0+1) and o_sync_left(x0+2) respectively in the synchronization modules SM(0), SM(1), SM(2), SM(x0), SM(x0+1) and SM(x0+2) respectively) is used to output a local clock CLK generated by the delay line circuit 320L. LOCAL_L The left-side divided clock output signal o_sync_left is used as a left-side divided clock output signal. Specifically, the left-side divided clock output signal o_sync_left is output to the left-side module through the left-side divided clock output pin o_sync_left. The delay line circuit 320L can delay the divided clock generated by the half-frequency divider 310 to generate the local clock CLK. LOCAL_L And when the next level is to the left of the current level, the next level can be considered as the module to the left; and

[0041] (12) The right-side frequency divider clock output pin o_sync_right (which can be written as o_sync_right(x0), o_sync_right(x0+1), and o_sync_right(x0+2) in the synchronization modules SM(x0), SM(x0+1), and SM(x0+2), respectively) is used to output the local clock CLK generated by the delay line circuit 320R. LOCAL_R The right-side divided clock output signal o_sync_right is used as a right-side divided clock output signal. Specifically, the right-side divided clock output signal o_sync_right is output to the right-side module through the right-side divided clock output pin o_sync_right. The delay line circuit 320R can delay the divided clock generated by the half-frequency divider 310 to generate the local clock CLK. LOCAL_R Furthermore, when the next level is located to the right of the current level, the next level can be considered as the module to the right.

[0042] Based on this synchronization result staticization and automatic configuration control scheme, the electronic device 100 (e.g., the synchronization control circuit therein) can utilize the X synchronization control sub-circuits having the same circuit architecture (e.g., the circuit architecture of the synchronization module 300), such as the X synchronization modules {SM(0),...,SM(X-1)}, to automatically synchronize the frequency division clock phases of the X frequency dividers {DIV(0),...,DIV(X-1)}. The synchronization module 300 can utilize the phase relationship detection circuits 330L and 330R to staticize the synchronization result of the current stage (i.e., the synchronization module 300) relative to the previous stage, in particular, making the synchronization result a static signal, thereby facilitating digital timing closure. Furthermore, the electronic device 100 (e.g., the synchronization control circuit therein) can eliminate the need for a synchronized reset signal for the X frequency dividers {DIV(0),...,DIV(X-1)}. Because the electronic device 100 (e.g., the synchronization control circuit therein) has a programmable architecture suitable for various scenarios, the electronic device 100 (e.g., the synchronization control circuit therein) can be flexibly and infinitely expanded when needed.

[0043] by Figure 2 Taking the connection method shown as an example, in this configuration, the synchronization module SM(0) in the instruction / address physical layer circuit APHY can be regarded as a master module, while the synchronization modules SM(1), SM(2), etc. in the data physical layer circuits DPHY(1), DPHY(2), etc. can be regarded as slave modules. The phase information can be propagated from the synchronization module SM(0) to all subsequent synchronization modules SM(1), SM(2), etc. Thus, the operation of the data physical layer circuits DPHY(1), DPHY(2), etc. is automatically synchronized with the operation of the instruction / address physical layer circuit APHY. After automatic synchronization, the respective synchronous frequency division output clocks by2_clk(0), by2_clk(1), by2_clk(2), etc. of the synchronization modules SM(0), SM(1), SM(2), etc. will be in phase.

[0044] Another Figure 1Taking the connection method shown as an example, in this configuration, the synchronization module SM(0) in the physical layer circuit PHY(0) can be regarded as the master module, while the synchronization modules SM(1), SM(2), etc. in the physical layer circuits PHY(1), PHY(2), etc. can be regarded as the slave modules. The phase information can be propagated from the synchronization module SM(0) to all subsequent synchronization modules SM(1), SM(2), etc. Thus, the operation of the physical layer circuits PHY(1), PHY(2), etc. is automatically synchronized with the operation of the physical layer circuit PHY(0). After automatic synchronization, the respective synchronous frequency division output clocks by2_clk(0), by2_clk(1), by2_clk(2), etc. of the synchronization modules SM(0), SM(1), SM(2), etc. will be in phase.

[0045] In a system with a single-source clock, all the divided clocks of the single-source clock must be synchronized with each other without any phase errors to allow all operations to proceed normally (as required by the original circuit design). Therefore, operating the electronic device 100 (e.g., the synchronization control circuit within it) based on this synchronization result static and automatic configuration control scheme ensures the correctness of all functions of the electronic device 100. Furthermore, when the system is in a newer application, designing a synchronization reset signal for the multiple dividers used to generate the multiple divided clocks may become more difficult, for example, due to high frequencies and on-chip variation (OCV). Implementing the electronic device 100 (e.g., the synchronization control circuit within it) based on this synchronization result static and automatic configuration control scheme ensures that the electronic device 100 avoids such problems, and is particularly suitable for various high-frequency applications.

[0046] The details regarding the candidate logic values ​​0 and 1 (e.g., 1'b0 and 1'b1) carried by the synchronization source selection control signal i_sync_source_sel can be further explained below. The aforementioned synchronization source may represent the preceding stage (e.g., the left module or the right module). When the synchronization source selection control signal i_sync_source_sel is configured to carry a candidate logic value of 0 to indicate the left side (e.g., the synchronization source is the left module), it controls the multiplexer circuit 341 to select the corresponding input (e.g., the data output signal Q). L When the current_rst signal is used as the current stage phase relationship detection result signal, the left-side divider clock input pin i_sync_left can be configured to receive the left-side divider clock input signal i_sync_left from the left-side module as an external clock CLK. EXTERNAL_L Additionally, the phase relationship detection circuit 330L can utilize the delay circuit 331L to delay the external clock CLK. EXTERNAL_LTo generate a delayed external clock CLK EXTERNAL_L D is used as the data input signal L Furthermore, it utilizes a D-type flip-flop 332L based on the local clock CLK. LOCAL_L Sampling external clock CLK EXTERNAL_L To generate data output signal Q L As a first static synchronization result corresponding to the phase relationship detection circuit 330L, it is used for phase control of the synchronous frequency division output clock by2_clk by the configurable phase control circuit 340 (e.g., XOR gate 343).

[0047] When the synchronization source selection control signal i_sync_source_sel is configured to carry a candidate logic value of 1 to indicate the right side (e.g., the synchronization source is the right module), it controls the multiplexer circuit 341 to select the corresponding input (e.g., the data output signal Q). R When the current_rst signal is used as the current-level phase relationship detection result signal, the right-side divider clock input pin i_sync_right can be configured to receive the right-side divider clock input signal i_sync_right from the right-side module as an external clock CLK. EXTERNAL_R Additionally, the phase relationship detection circuit 330R can utilize the delay circuit 331R to delay the external clock CLK. EXTERNAL_R To generate a delayed external clock CLK EXTERNAL_R D is used as the data input signal R Furthermore, it utilizes a D-type flip-flop 332R based on the local clock CLK. LOCAL_R Sampling external clock CLK EXTERNAL_R To generate data output signal Q R This serves as a second static synchronization result corresponding to the phase relationship detection circuit 330R, for the configurable phase control circuit 340 (e.g., XOR gate 343) to perform phase control on the synchronous frequency division output clock by2_clk.

[0048] Figure 4 Illustration based on an embodiment of the present invention Figure 3 The synchronization result static and automatic configuration control scheme shown illustrates the in-phase detection results involved. For the phase relationship detection circuit 330L, the external clock CLK... EXTERNAL_L / R Local clock CLK LOCAL_L / R Data input signal D L / R and data output signal Q L / R They can represent the external clock CLK respectively. EXTERNAL_L Local clock CLK LOCAL_L Data input signal D L and data output signal Q LFor the phase relationship detection circuit 330R, the external clock CLK EXTERNAL_L / R Local clock CLK LOCAL_L / R Data input signal D L / R and data output signal Q L / R They can represent the external clock CLK respectively. EXTERNAL_R Local clock CLK LOCAL_R Data input signal D R and data output signal Q R .

[0049] For example, the phase relationship detection circuit 330L can use the delay circuit 331L to delay the external clock CLK. EXTERNAL_L To generate data input signal D L To ensure that the D-type flip-flop 332L correctly operates according to the local clock CLK LOCAL_L Sampling external clock CLK EXTERNAL_L To generate data output signal Q L And avoid using an external clock CLK. EXTERNAL_L Any sampling operation is performed at any state transition edge to ensure the correctness of the first static synchronization result. This is due to the external clock CLK. EXTERNAL_L and local clock CLK LOCAL_L The phase relationship between them is that they are in phase (labeled as "0°" for simplicity), therefore the data output signal Q... L It may carry a second predetermined logical value such as the candidate logical value 0 (e.g., 1'b0, in...). Figure 4 (This can be plotted as a low voltage level) to indicate that the first static synchronization result represents the in-phase detection result.

[0050] To give another example, the phase relationship detection circuit 330R can use the delay circuit 331R to delay the external clock CLK. EXTERNAL_R To generate data input signal D R To ensure that the D-type flip-flop 332R correctly operates according to the local clock CLK LOCAL_R Sampling external clock CLK EXTERNAL_R To generate data output signal Q R And avoid using an external clock CLK. EXTERNAL_R Any sampling operation is performed at any state transition edge to ensure the correctness of the second static synchronization result. This is due to the external clock CLK. EXTERNAL_R and local clock CLK LOCAL_R The phase relationship between them is that they are in phase (labeled as "0°" for simplicity), therefore the data output signal Q... R It may contain the second predetermined logical value, such as the candidate logical value 0 (e.g., 1'b0, in...). Figure 4(This can be illustrated as the low voltage level) to indicate that the second static synchronization result represents the in-phase detection result. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0051] Figure 5 Illustration based on an embodiment of the present invention Figure 3 The synchronization result staticization and automatic configuration control scheme shown involves the phase inversion detection result. For example, the phase relationship detection circuit 330L can use the delay circuit 331L to delay the external clock CLK. EXTERNAL_L To generate data input signal D L To ensure that the D-type flip-flop 332L correctly operates according to the local clock CLK LOCAL_L Sampling external clock CLK EXTERNAL_L To generate data output signal Q L And avoid using an external clock CLK. EXTERNAL_L Any sampling operation is performed at any state transition edge to ensure the correctness of the first static synchronization result. This is due to the external clock CLK. EXTERNAL_L and local clock CLK LOCAL_L The phase relationship between them is out of phase (labeled "180°" for simplicity), therefore the data output signal Q L It may carry a first predetermined logical value such as the candidate logical value 1 (e.g., 1'b1, in...). Figure 5 (This can be plotted as a high voltage level) to indicate that the first static synchronization result represents the inverted detection result.

[0052] To give another example, the phase relationship detection circuit 330R can use the delay circuit 331R to delay the external clock CLK. EXTERNAL_R To generate data input signal D R To ensure that the D-type flip-flop 332R correctly operates according to the local clock CLK LOCAL_R Sampling external clock CLK EXTERNAL_R To generate data output signal Q R And avoid using an external clock CLK. EXTERNAL_R Any sampling operation is performed at any state transition edge to ensure the correctness of the second static synchronization result. This is due to the external clock CLK. EXTERNAL_R and local clock CLK LOCAL_R The phase relationship between them is out of phase (labeled "180°" for simplicity), therefore the data output signal Q R It may contain the first predetermined logical value such as the candidate logical value 1 (e.g., 1'b1, in...). Figure 5 (This can be illustrated as the high voltage level) to indicate that the second static synchronization result represents the inversion detection result. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0053] Figure 6 According to an embodiment of the present invention, a first configurable synchronization line control scheme of the method is illustrated. For ease of understanding, the x-th synchronization control sub-circuit of the X synchronization control sub-circuits can represent the x-th synchronization module SM(x) of the X synchronization modules {SM(0),…,SM(X-1)}, such as synchronization module 300, where the index x can represent any integer in the interval [0,(X-1)]. For example, when x = x0 (e.g., the symbol “x0” can represent any integer in [0,(X-2)]), the x-th synchronization module SM(x), such as synchronization module 300, can be illustrated as follows: Figure 6 The left half of the diagram shows the synchronization module SM(x0). As another example, when x = (x0 + 1), the x-th synchronization module SM(x), such as synchronization module 300, can be drawn as... Figure 6 The right half of the diagram shows the synchronization module SM(x0+1). Furthermore, the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),…,SM(X-1)}, can be configured as a synchronization line circuit so that the x0th and (x0+1th)th synchronization control sub-circuits, such as the x0th and (x0+1th)th synchronization modules SM(x0) and SM(x0+1), can be used... Figure 6 Signal exchange is performed as shown. In particular, the left-side divider clock input pin i_sync_left(x0+1) and the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0+1) can be coupled to the right-side divider clock output pin o_sync_right(x0) and the current stage phase selection result output pin o_sync_result(x0), respectively. For the sake of simplicity, similar details will not be repeated in this embodiment.

[0054] exist Figure 6 In the configuration shown, synchronization modules SM(x0) and SM(x0+1) can respectively serve as examples of the preceding and current stages in the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)}, or respectively as examples of the current and next stages in the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)}. Synchronization modules SM(x0) and SM(x0+1) can be considered as the left-hand module of synchronization module SM(x0+1) and the right-hand module of synchronization module SM(x0), respectively, but the invention is not limited thereto. In some embodiments, the relative positions of synchronization modules SM(x0) and SM(x0+1) can be changed, and / or the related connections (along with related signal exchanges) can be changed. For the sake of simplicity, similar details in these embodiments will not be repeated here.

[0055] Figure 7 A second configurable synchronization line control scheme of the method is illustrated according to an embodiment of the present invention. According to this embodiment, Figure 6 The positions of the synchronization modules SM(x0) and SM(x0+1) shown can be interchanged so that the synchronization modules SM(x0) and SM(x0+1) become located at... Figure 7 The right and left halves of the synchronization module SM(x0) and the connection between the synchronization modules SM(x0) and SM(x0+1) can be reconfigured. In particular, the right-side divider clock input pin i_sync_right(x0+1) and the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0) can be coupled to the left-side divider clock output pin o_sync_left(x0) and the current stage phase selection result output pin o_sync_result(x0) of the synchronization module SM(x0), respectively. Furthermore, the x0th and (x0+1th)th synchronization control sub-circuits in the X synchronization control sub-circuits, such as the x0th and (x0+1th)th synchronization modules SM(x0) and SM(x0+1), can exchange signals in a manner similar to the respective synchronization control sub-circuits of physical layer circuits PHY(0) and PHY(1) (e.g., synchronization modules SM(0) and SM(1)), or in a manner similar to the respective synchronization control sub-circuits of physical layer circuits PHY(1) and PHY(2) (e.g., synchronization modules SM(1) and SM(2)). For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0056] Figure 8 A third configurable synchronization line control scheme of the method is illustrated according to an embodiment of the present invention. According to this embodiment, the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),...,SM(X-1)}, can be configured as a tree-structured synchronization line circuit, wherein a synchronization module SM(x0) can be considered as a node in the tree structure, and synchronization modules SM(x0+1) and SM(x0+2) can be considered as two branches starting from that node; however, the present invention is not limited thereto. In some embodiments, the relative positions of synchronization modules SM(x0), SM(x0+1), and SM(x0+2) can be varied, and / or their associated connections (along with associated signal exchanges) can be varied.

[0057] For this third configurable synchronous line control scheme, please also refer to... Figure 7 and Figure 8 For ease of understanding, assume the symbol "x0" can represent any integer in the range [0, (x-3)]. For example:

[0058] (1) When x = x0, the x-th synchronization module SM(x), such as synchronization module 300, can be represented as Figure 8 The synchronization module SM(x0) shown in the left half can also be drawn as Figure 7 The right half of the diagram shows the synchronization module SM(x0);

[0059] (2) When x = (x0 + 1), the x-th synchronization module SM(x), such as synchronization module 300, can be represented as Figure 7 The left half of the diagram shows the synchronization module SM(x0+1); and

[0060] (3) When x = (x0 + 2), the x-th synchronization module SM(x), such as synchronization module 300, can be represented as Figure 8 The right half of the diagram shows the synchronization module SM(x0+2).

[0061] Furthermore, the x0th and (x0+1th)th synchronous control sub-circuits in these X synchronous control sub-circuits, such as the x0th and (x0+1th)th synchronous modules SM(x0) and SM(x0+1), can be used Figure 7 Signal exchange is performed as shown, wherein the left-side divider clock output pin o_sync_left(x0) and the current stage phase selection result output pin o_sync_result(x0) of the synchronization module SM(x0) can be coupled to the right-side divider clock input pin i_sync_right(x0+1) and the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0+1), respectively. Figure 8 These are respectively labeled "to i_sync_right(x0+1)" and "to i_sync_pre_result(x0+1)" for brevity. Furthermore, the x0th and (x0+2th)th synchronous control sub-circuits in these X synchronous control sub-circuits, such as the x0th and (x0+2th)th synchronous modules SM(x0) and SM(x0+2), can be used... Figure 8 Signal exchange is performed as shown. In particular, the left-side divider clock input pin i_sync_left(x0+2) and the previous stage phase selection result input pin i_sync_pre_result(x0+2) of the synchronization module SM(x0+2) can be coupled to the right-side divider clock output pin o_sync_right(x0) and the current stage phase selection result output pin o_sync_result(x0), respectively. For the sake of simplicity, similar details will not be repeated in this embodiment.

[0062] According to certain embodiments, Figure 6The synchronization modules SM(x0) and SM(x0+1) shown can be rearranged to become located at... Figure 6 The upper and lower halves, or rearranged to become respectively located in Figure 6 The lower half and the upper and lower halves. Furthermore, the connection between synchronization modules SM(x0) and SM(x0+1) can be selectively reconfigured, depending on the optimized wiring of synchronization modules SM(x0) and SM(x0+1), and / or one or more other synchronization modules. For example:

[0063] (1) When reconfiguration is not required, the left-side divider clock input pin i_sync_left(x0+1) and the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0+1) can be coupled to the right-side divider clock output pin o_sync_right(x0) and the current stage phase selection result output pin o_sync_result(x0) of the synchronization module SM(x0), respectively; and

[0064] (2) When reconfiguration is required, the right-side frequency divider clock input pin i_sync_right(x0+1) and the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0+1) can be coupled to the left-side frequency divider clock output pin o_sync_left(x0) and the current stage phase selection result output pin o_sync_result(x0) of the synchronization module SM(x0), respectively.

[0065] For the sake of simplicity, similar content will not be repeated here in these embodiments.

[0066] Table 2

[0067]

[0068]

[0069] Table 2 illustrates, according to an embodiment of the present invention, the phase of the respective outputs (e.g., frequency division clocks) of the X synchronization modules {SM(0),...,SM(X-1)} of the X physical layer circuits {PHY(0),...,PHY(X-1)} (e.g., physical layer circuits PHY(0), PHY(1), PHY(2), PHY(3), PHY(4), and PHY(5)) and the logic values ​​or phases of the X frequency dividers {DIV(0),...,DIV(X-1)} of the X frequency dividers {DIV(0),...,DIV(X-1)}. For example, the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),...,SM(X-1)}, can be configured as the synchronization line circuit, and any two adjacent synchronization modules SM(x0) and SM(x0+1) can be used... Figure 6 or Figure 7 Signal exchange is performed in the manner shown.

[0070] Based on this synchronization result static and automatic configuration control scheme, regardless of which possible combination of the phases of the outputs (e.g., the divided clocks) of the frequency dividers {DIV(0), ..., DIV(X-1)} of the X physical layer circuits {PHY(0), ..., PHY(X-1)} equals, the phase information can be propagated from the synchronization module SM(0) to all subsequent synchronization modules SM(1), SM(2), etc., to allow the operation of physical layer circuits PHY(1), PHY(2), etc. to be automatically synchronized with the operation of physical layer circuit PHY(0). After automatic synchronization, the respective synchronized divided clocks by2_clk(0), by2_clk(1), by2_clk(2), etc. of the synchronization modules SM(0), SM(1), SM(2), etc. will be in phase. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0071] Table 3

[0072]

[0073]

[0074] Table 3 illustrates, according to another embodiment of the present invention, the phase of the respective output (e.g., the divided clock) of the X synchronization modules {SM(0),...,SM(X-1)} of the X physical layer circuits {PHY(0),...,PHY(X-1)} (e.g., physical layer circuits PHY(0), PHY(1), PHY(2), PHY(3), PHY(4), and PHY(5)) and the logic values ​​or phases of the X frequency dividers {DIV(0),...,DIV(X-1)} of the X frequency dividers {DIV(0),...,DIV(X-1)}. For example, the X synchronization control sub-circuits, such as the X synchronization modules {SM(0),...,SM(X-1)}, can be configured as the synchronization line circuit, and any two adjacent synchronization modules SM(x0) and SM(x0+1) can be used... Figure 6 or Figure 7 Signal exchange is performed in the manner shown.

[0075] Based on this synchronization result static and automatic configuration control scheme, regardless of which possible combination of the phases of the outputs (e.g., the divided clocks) of the frequency dividers {DIV(0), ..., DIV(X-1)} of the X physical layer circuits {PHY(0), ..., PHY(X-1)} equals, the phase information can be propagated from the synchronization module SM(0) to all subsequent synchronization modules SM(1), SM(2), etc., to allow the operation of physical layer circuits PHY(1), PHY(2), etc. to be automatically synchronized with the operation of physical layer circuit PHY(0). After automatic synchronization, the respective synchronized divided clocks by2_clk(0), by2_clk(1), by2_clk(2), etc. of the synchronization modules SM(0), SM(1), SM(2), etc. will be in phase. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0076] Figure 9 A workflow of the method is illustrated according to an embodiment of the present invention. The method is applicable to electronic device 100 and its synchronization control circuit, particularly to the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)} (e.g., Figure 3 The synchronization module 300 shown. In the X synchronization control sub-circuits such as the X synchronization modules {SM(0),...,SM(X-1)}, a first synchronization control sub-circuit and a second synchronization control sub-circuit can represent synchronization modules SM(x0) and SM(x0+1), respectively.

[0077] In step S11, the electronic device 100 (e.g., the synchronization control circuit) can utilize a first frequency divider (e.g., frequency divider DIV(x0)) in the first synchronization control sub-circuit (e.g., synchronization module SM(x0)) according to the source clock CLK. SOURCE A first frequency division operation is performed to generate a first frequency division clock, such as the frequency division clock generated by the half-frequency divider 310 in the synchronization module SM(x0).

[0078] In step S12, the electronic device 100 (e.g., the synchronization control circuit) can utilize a second frequency divider (e.g., frequency divider DIV(x0+1)) in the second synchronization control sub-circuit (e.g., synchronization module SM(x0+1)) according to the source clock CLK. SOURCE A second frequency division operation is performed to generate a second frequency divided clock, such as the frequency divided clock generated by the half-frequency divider 310 in the synchronization module SM(x0+1).

[0079] In step S13, the electronic device 100 (e.g., the synchronization control circuit) can use the first synchronization control sub-circuit, such as the synchronization module SM(x0), to output the first divided clock to the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), and in particular, output a delayed version of the first divided clock, such as the local clock CLK in the synchronization module SM(x0). LOCAL_L / R This leads to the second synchronization control sub-circuit, such as the synchronization module SM(x0+1). For example, the electronic device 100 (e.g., the synchronization control circuit) can output the local clock CLK in the synchronization module SM(x0) via the left-side divided clock output pin o_sync_left(x0) of the synchronization module SM(x0). LOCAL_L This is transmitted to the synchronization module SM(x0+1). As another example, electronic device 100 (e.g., the synchronization control circuit) can output the local clock CLK in the synchronization module SM(x0) via the right-side divided clock output pin o_sync_right(x0) of the synchronization module SM(x0). LOCAL_R To the synchronization module SM(x0+1).

[0080] In step S14, the electronic device 100 (e.g., the synchronization control circuit) can use the first synchronization control sub-circuit, such as the synchronization module SM(x0), to output a first phase selection result output signal, such as the current stage phase selection result output signal o_sync_result(x0), to the second synchronization control sub-circuit, such as the synchronization module SM(x0+1). In particular, the current stage phase selection result output signal o_sync_result(x0) is output to the synchronization module SM(x0+1) through the current stage phase selection result output pin o_sync_result(x0) of the synchronization module SM(x0), so as to serve as the previous stage phase selection result input signal i_sync_pre_result(x0+1) received by the previous stage phase selection result input pin i_sync_pre_result(x0+1) of the synchronization module SM(x0+1). The logic value carried by the first phase selection result output signal can indicate a first phase selection result of the first synchronization control sub-circuit (e.g., the synchronization module SM(x0)).

[0081] In step S15, the electronic device 100 (e.g., the synchronization control circuit) may utilize a phase relationship detection circuit in the second synchronization control sub-circuit, such as phase relationship detection circuit 330L or phase relationship detection circuit 330R in the synchronization module SM(x0+1), according to the second frequency division clock (e.g., its delayed version, such as the local clock CLK in the synchronization module SM(x0+1)). LOCAL_L / R This first divided clock (e.g., its delayed version, such as the local clock CLK in the synchronization module SM(x0)) LOCAL_L / R A phase relationship detection is performed to generate a phase relationship detection result signal, such as the current_rst phase relationship detection result signal in the synchronization module SM(x0+1), wherein the logic value carried by the phase relationship detection result signal can indicate a phase relationship detection result of the second synchronization control sub-circuit (e.g., synchronization module SM(x0+1)). In particular, the phase relationship detection result can represent a phase relationship between the first divided clock and the second divided clock.

[0082] For example, when the synchronization module SM(x0+1) is configured to receive the first divided clock (e.g., the local clock CLK in the synchronization module SM(x0)) via the left-divided clock input pin i_sync_left(x0+1). LOCAL_L / R ) to serve as the external clock CLK for the synchronization module SM(x0+1) EXTERNAL_L At the same time, the electronic device 100 (e.g., the synchronization control circuit) can utilize the phase relationship detection circuit 330L in the synchronization module SM(x0+1) based on the local clock CLK in the synchronization module SM(x0+1).LOCAL_L External clock CLK EXTERNAL_L This phase relationship detection is performed to generate the data output signal Q. L This is used as the phase relationship detection result signal, such as the current_rst phase relationship detection result signal in the synchronization module SM(x0+1). For another example, when the synchronization module SM(x0+1) is configured to receive the first divided clock (e.g., the local clock CLK in the synchronization module SM(x0)) via the right-hand divided clock input pin i_sync_right(x0+1). LOCAL_L / R ) to serve as the external clock CLK for the synchronization module SM(x0+1) EXTERNAL_R At the same time, the electronic device 100 (e.g., the synchronization control circuit) can utilize the phase relationship detection circuit 330R in the synchronization module SM(x0+1) based on the local clock CLK in the synchronization module SM(x0+1). LOCAL_R External clock CLK EXTERNAL_R This phase relationship detection is performed to generate the data output signal Q. R This is used as the phase relationship detection result signal, such as the current level phase relationship detection result signal current_rst in the synchronization module SM(x0+1).

[0083] In step S16, the electronic device 100 (e.g., the synchronization control circuit) can use a logic gate in the second synchronization control sub-circuit, such as the XOR gate 343 in the synchronization module SM(x0+1), to perform a logical operation such as an XOR operation on the first phase selection result output signal (e.g., the current stage phase selection result output signal o_sync_result(x0) of the synchronization module SM(x0), that is, the previous stage phase selection result input signal i_sync_pre_result(x0+1) of the synchronization module SM(x0+1)) and the phase relationship detection result signal (e.g., the current stage phase relationship detection result signal current_rst in the synchronization module SM(x0+1)). (operation) to generate a second phase selection result output signal, such as the current phase selection result output signal o_sync_result(x0+1) of the synchronization module SM(x0+1), wherein the logic value carried by the second phase selection result output signal can indicate a second phase selection result of the second synchronization control sub-circuit (e.g., the synchronization module SM(x0+1)).

[0084] In step S17, the electronic device 100 (e.g., the synchronization control circuit) may utilize the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), to output the second divided clock (e.g., the divided clock generated by the half-frequency divider 310 in the synchronization module SM(x0+1)) and an inverted signal of the second divided clock (e.g., the inverted signal generated by the inverter 344 in the synchronization module SM(x0+1)) based on the second phase selection result output signal (e.g., the current-level phase selection result output signal o_sync_result(x0+1) output by the synchronization module SM(x0+1) through the current-level phase selection result output pin o_sync_result(x0+1)) for further use by a physical layer circuit (e.g., physical layer circuit PHY(x0+1)) having the second synchronization control sub-circuit.

[0085] According to this embodiment, the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), can use its internal inverter 344 to invert the second frequency-divided clock to generate the inverted signal. Based on the logic value carried in the second phase selection result output signal, it selects one of the second frequency-divided clock and the inverted signal as a selected frequency-divided clock, and outputs the selected frequency-divided clock for further use by the corresponding physical layer circuit PHY(x0+1). For example:

[0086] (1) When the logic value carried in the second phase selection result output signal is equal to the first predetermined logic value, such as candidate logic value 1 (e.g., 1'b1), the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), can select the inverted signal as the frequency division clock for the selection; and

[0087] (2) When the logic value carried by the output signal of the second phase selection result is equal to the second predetermined logic value such as the candidate logic value 0 (e.g., 1'b0), the second synchronization control sub-circuit such as the synchronization module SM(x0+1) can select the second frequency divider clock as the selected frequency divider clock.

[0088] However, the present invention is not limited thereto. In some embodiments, if the logic value carried by the second phase selection result output signal is equal to the first predetermined logic value, such as the candidate logic value 1 (e.g., 1'b1), then the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), can select the inverted signal as the frequency divider clock for the selection; otherwise, the second synchronization control sub-circuit, such as the synchronization module SM(x0+1), can select the second frequency divider clock as the frequency divider clock for the selection. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0089] To better understand, this method is available Figure 9 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 9 Add, delete, or modify in the workflow shown.

[0090] According to certain embodiments, the left and right sides in the above embodiments can be replaced by a first side and a second side, respectively, such as any two sides of a plurality of predetermined sides (e.g., upper side, lower side, left side, and right side) of a circuit (e.g., a synchronization module SM(x)), and the terms "left side" and "right side" in the relevant components (e.g., the left module and the right module) and the corresponding pins / signals can be replaced by "first side" and "second side," respectively. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0091] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0092] [Symbol Explanation]

[0093] 100, 200: Electronic devices

[0094] 110: Dynamic Random Access Memory (DRAM)

[0095] 300,SM(0)~SM(2),SM(x0)~SM(x0+2): Synchronization module

[0096] 310: Half-frequency crossover

[0097] 320L, 320R: Delay line circuit

[0098] 330L, 330R: Phase Relationship Detection Circuit

[0099] 331L, 321R: Delay circuits

[0100] 332L, 322R: D-type triggers

[0101] 340: Configurable phase control circuit

[0102] 341, 342, 345: Multiplexer circuits

[0103] 343: XOR gate

[0104] 344: Inverter

[0105] APHY: Instruction / Address Physical Layer Circuit

[0106] CG(0)~CG(2): Clock generator

[0107] DIV(0)~DIV(2): Frequency divider

[0108] DPHY(1), DPHY(2): Data Physical Layer Circuits

[0109] PHY(0)~PHY(2): Physical layer circuit

[0110] i_ref_clk, i_ref_clk(x0)~i_ref_clk(x0+2): Input reference clock pins

[0111] i_rstb, i_rstb(x0)~i_rstb(x0+2): Reset pins

[0112] i_sync_pre_result, i_sync_pre_result(0)~i_sync_pre_result(2), i_sync_pre_result(x0)~i_sync_pre_result(x0+2): Input pins for the previous stage phase selection result.

[0113] o_sync_result, o_sync_result(0)~o_sync_result(2), o_sync_result(x0)~o_sync_result(x0+2): Current stage phase selection result output pins

[0114] i_sync_auto: Automatic synchronization enable pin

[0115] i_phase_sel: Phase selection manual control pin

[0116] i_sync_source_sel: Synchronization source selection control pin

[0117] by2_clk,by2_clk(0)~by2_clk(2),by2_clk(x0)~by2_clk(x0+2): Synchronous frequency division output clock pins

[0118] i_sync_left, i_sync_left(x0)~i_sync_left(x0+2): Left-side divider clock input pin

[0119] i_sync_right, i_sync_right(0)~i_sync_right(2), i_sync_right(x0)~i_sync_right(x0+2): Right-side divider clock input pin

[0120] o_sync_left, o_sync_left(0)~o_sync_left(2), o_sync_left(x0)~o_sync_left(x0+2): Left-side divider clock output pin

[0121] o_sync_right, o_sync_right(x0)~o_sync_right(x0+2): Right-side divider clock output pins

[0122] CLK SOURCE Source: Clock

[0123] CLK EXTERNAL_L ,CLK EXTERNAL_R ,CLK EXTERNAL_L / R External clock

[0124] CLK LOCAL_L ,CLK LOCAL_R ,CLK LOCAL_L / R Local clock

[0125] D L D R D L / R Data input signal

[0126] Q L Q R Q L / R Data output signal

[0127] current_rst: Current phase relationship detection result signal

Claims

1. A method for synchronizing the phase of a divided clock in a multi-divided-clock system, the method comprising: A first frequency divider in a first synchronization control sub-circuit is used to perform a first frequency division operation based on a source clock to generate a first frequency divided clock; A second frequency divider in a second synchronization control sub-circuit is used to perform a second frequency division operation based on the source clock to generate a second frequency divided clock; The first frequency-divided clock is output to the second synchronization control sub-circuit using the first synchronization control sub-circuit; The first synchronization control sub-circuit outputs a first phase selection result output signal to the second synchronization control sub-circuit, wherein the logic value carried by the first phase selection result output signal indicates a first phase selection result of the first synchronization control circuit; The phase relationship detection circuit in the second synchronization control sub-circuit performs phase relationship detection on the first frequency divider clock according to the second frequency divider clock to generate a phase relationship detection result signal, wherein the logic value carried in the phase relationship detection result signal indicates a phase relationship detection result of the second synchronization control sub-circuit. A logic operation is performed on the first phase selection result output signal and the phase relationship detection result signal using a logic gate in the second synchronization control sub-circuit to generate a second phase selection result output signal, wherein the logic value carried by the second phase selection result output signal indicates a second phase selection result of the second synchronization control sub-circuit. as well as The second synchronization control sub-circuit outputs one of the second frequency division clock and an inverted signal of the second frequency division clock based on the second phase selection result, so as to be further used by a physical layer circuit equipped with the second synchronization control sub-circuit.

2. The method of claim 1, wherein the phase relationship detection result represents a phase relationship between the first frequency divider clock and the second frequency divider clock.

3. The method of claim 1, wherein the logic gate in the second synchronization control sub-circuit represents an XOR gate, and the logic operation represents an XOR operation.

4. The method of claim 1, wherein the step of outputting one of the second frequency-divided clock and the inverted signal of the second frequency-divided clock based on the second phase selection result using the second synchronization control subcircuit to be further used by the physical layer circuit having the second synchronization control subcircuit further comprises: The second frequency divider clock is inverted using an inverter in the second synchronization control sub-circuit to generate the inverted signal; Based on the logic value carried in the output signal of the second phase selection result, one of the second divided clock and the inverted signal is selected as a divided clock; and The selected frequency division clock is output using the second synchronization control sub-circuit for further use by the physical layer circuit equipped with the second synchronization control sub-circuit.

5. The method of claim 4, wherein the step of selecting one of the second divided clock and the inverted signal as the selected divided clock based on the logic value carried in the second phase selection result output signal further comprises: When the logic value carried in the output signal of the second phase selection result is equal to a first predetermined logic value, the inverted signal is selected as the frequency divider clock for the selection.

6. The method of claim 5, wherein the step of selecting one of the second divided clock and the inverted signal as the selected divided clock based on the logic value carried in the second phase selection result output signal further comprises: When the logic value carried in the output signal of the second phase selection result is equal to a second predetermined logic value, the second frequency divider clock is selected as the frequency divider clock for the selection.

7. The method of claim 4, wherein the step of selecting one of the second divided clock and the inverted signal as the selected divided clock based on the logic value carried in the second phase selection result output signal further comprises: If the logic value carried in the output signal of the second phase selection result is equal to a first predetermined logic value, then the inverted signal is selected as the frequency divider clock for the selection; otherwise, the second frequency divider clock is selected as the frequency divider clock for the selection.

8. The method of claim 1, wherein the plurality of synchronization control sub-circuits having the same circuit architecture include the first synchronization control sub-circuit and the second synchronization control sub-circuit; and the method further includes: The multiple synchronization control sub-circuits are coupled to each other to form a synchronization control circuit, which is used to synchronize the frequency divider clock generated by the frequency divider of each of the multiple synchronization control sub-circuits.

9. The method of claim 8, wherein in the synchronization control circuit, any two adjacent synchronization control sub-circuits of the plurality of synchronization control sub-circuits exchange signals in a manner similar to that of the first synchronization control sub-circuit and the second synchronization control sub-circuit.

10. A synchronization control circuit operating according to the method of claim 1, wherein the synchronization control circuit comprises: Multiple synchronization control sub-circuits, having the same circuit architecture and coupled to each other, are used to synchronize the frequency divider clock generated by the frequency divider of each of the multiple synchronization control sub-circuits, wherein the multiple synchronization control sub-circuits include the first synchronization control sub-circuit and the second synchronization control sub-circuit.

11. A synchronization control sub-circuit, which is one of a plurality of synchronization control sub-circuits in a synchronization control circuit, the synchronization control sub-circuit comprising: A frequency divider is used to divide a source clock by one to generate a divided clock. A phase relationship detection circuit, coupled to the frequency divider, is used to perform phase relationship detection on another frequency divider clock output by another synchronization control sub-circuit based on the frequency divider clock to generate a phase relationship detection result signal, wherein the logic value carried in the phase relationship detection result signal indicates a phase relationship detection result of the synchronization control sub-circuit; A logic gate, coupled to the phase relationship detection circuit, is used to perform a logic operation on a first phase selection result output signal and the phase relationship detection result signal output by the other synchronization control subcircuit to generate a second phase selection result output signal. The logic value carried by the first phase selection result output signal indicates a first phase selection result of the other synchronization control subcircuit, and the logic value carried by the second phase selection result output signal indicates a second phase selection result of the synchronization control subcircuit. A synchronized divided output clock pin is provided, through which the synchronization control sub-circuit outputs one of the divided clock and an inverted signal of the divided clock according to the second phase selection result, for further use by a physical layer circuit equipped with the synchronization control sub-circuit.

12. The synchronization control sub-circuit as claimed in claim 11, wherein the phase relationship detection result represents a phase relationship between the other frequency divider clock and the frequency divider clock.

13. The synchronous control sub-circuit as claimed in claim 11, wherein the logic gate represents an XOR gate, and the logic operation represents an XOR operation.

14. The synchronization control sub-circuit as described in claim 11, further comprising: An inverter is used to invert the divided clock signal to generate the inverted signal; and A multiplexer circuit, coupled to the logic gate, the frequency divider and the inverter, is used to select one of the frequency divider clock and the inverted signal as a selected frequency divider clock based on the logic value carried in the output signal of the second phase selection result. The synchronization control sub-circuit outputs the selected frequency division clock for further use by the physical layer circuit equipped with the synchronization control sub-circuit.

15. The synchronization control sub-circuit of claim 14, wherein when the logic value carried in the second phase selection result output signal is equal to a first predetermined logic value, the multiplexer circuit selects the inverted signal as the selected frequency division clock.

16. The synchronization control sub-circuit as claimed in claim 15, wherein when the logic value carried in the second phase selection result output signal is equal to a second predetermined logic value, the multiplexer circuit selects the frequency divider clock as the selected frequency divider clock.

17. The synchronization control sub-circuit of claim 14, wherein if the logic value carried in the second phase selection result output signal is equal to a first predetermined logic value, the multiplexer circuit selects the inverted signal as the selected frequency divider clock; otherwise, the multiplexer circuit selects the frequency divider clock as the selected frequency divider clock.

18. The synchronization control sub-circuit of claim 11, wherein the plurality of synchronization control sub-circuits have the same circuit architecture; and the synchronization control sub-circuit is configurable to allow the plurality of synchronization control sub-circuits to be coupled to each other to form the synchronization control circuit for synchronizing the frequency divider clock generated by the respective frequency dividers of the plurality of synchronization control sub-circuits.

19. The synchronization control sub-circuit of claim 18, wherein in the synchronization control circuit, any two adjacent synchronization control sub-circuits of the plurality of synchronization control sub-circuits exchange signals in a manner similar to that of the other synchronization control sub-circuit and the synchronization control sub-circuit itself.

20. An electronic device comprising the synchronization control sub-circuit as claimed in claim 11, wherein the electronic device comprises: A memory module, used to temporarily store information for the electronic device; and Multiple physical layer circuits are coupled to the memory for accessing the memory to perform operations of the electronic device, wherein each of the multiple physical layer circuits includes a corresponding synchronization control sub-circuit among the multiple synchronization control sub-circuits.

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