Placement and simulation of neighboring cells with diffusion interrupt cells

Abstract

Disclosed herein is a system and method for placing and simulating a cell near a cell having a diffusion interruption. According to one embodiment, an integrated circuit is designed to include a first cell having a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region extending from the first edge to the second edge, and the diffusion interruption separates the diffusion region. The diffusion interruption may be spaced apart from the second edge by a distance that reduces a metric (e.g., delay, slew rate, dynamic power, or leakage) of a second cell placed adjacent to the second edge by more than a threshold level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 17 / 093,457, filed on November 9, 2020, entitled “Placement and Simulation of Cell in Proximity to Cell with Diffusion Break,” which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to an integrated circuit design system. In particular, the present disclosure relates to a system and method for providing placement and simulation of a cell adjacent to another cell having a diffusion break in a continuous diffusion semiconductor process. Background Art

[0004] Semiconductor processes using continuous diffusions do not have diffusion breaks to electrically isolate different diffusions from each other. A dummy transistor with a gate connected to a power supply or ground can be used to achieve the desired electrical isolation. Cell-based designs can use cells with a small number of continuous diffusion breaks. The most common cell with diffusion breaks is the well-tap cell, which contains the n-well and substrate contacts required to prevent latch-up. Diffusion breaks have an adverse effect on the metrics of cells placed near them.

[0005] Conventional cell-based chip design flows do not use space on the chip near a diffusion interrupt to avoid considering its impact on the timing and power of cells placed near it. Diffusion interrupts have the greatest impact on cells near the interrupt, and the impact may gradually diminish as cells are placed farther away from the interrupt. If the designer wants to use space near the interrupt, the conventional approach used by the electronic design automation (EDA) flow can model the impact of cells placed within D placement grids on the left and / or right side of the diffusion interrupt with a D×D derating table. The EDA system selects the value of parameter D so that the cell's metrics do not change substantially when the cell is placed at a distance greater than D placement grids from the diffusion interrupt. The value of D is based on one or more characteristics of the semiconductor process. The derating table can capture the impact of diffusion interrupts on the metrics (e.g., delay, slew, dynamic power, and leakage) of cells placed near the diffusion interrupt. The size of the table can represent the distance of the left and right boundaries of the cell from the diffusion interrupt. The derating value can vary with different input slew and output load combinations for which the cell is characterized. Therefore, the method may include a D×D derating table for characterizing each load and slew combination in the cell model table, effectively creating a D2 timing model for each cell. This makes cell characterization and timing analysis expensive in terms of memory usage and computation time. To avoid this, cell libraries used in conventional EDA tool flows for continuous diffusion processes artificially increase the size of cells with diffusion breaks so that the diffusion breaks are larger than the D placement grid from the cell boundaries, effectively preventing the cell from being placed within the D placement grid from the diffusion break. However, this reduces the amount of space that can be used to place other cells within the integrated circuit design. Summary of the invention

[0006] Embodiments relate to systems and methods for designing integrated circuits. In one embodiment, a method includes placing a first cell on one side of a second cell, wherein the first cell includes a first edge, a second edge on an opposite side of the first edge of the first cell, and a diffusion region extending from the first edge to the second edge, wherein a diffusion interruption separates the diffusion region. The second cell may include a third edge separated from the diffusion interruption by a specified distance. A simulation model is selected from one or more simulation models, wherein each simulation model is associated with a corresponding edge of a given cell separated from a given diffusion interruption by a corresponding specified distance less than or equal to a threshold distance. A simulation of the second cell can then be performed using the selected simulation model.

[0007] In some embodiments, the simulation model includes three models: a first model including a first plurality of metrics associated with placing the third edge facing the first edge and spaced apart from the diffusion interruption by a specified distance; a second model including a second plurality of metrics associated with placing the third edge facing the second edge and spaced apart from the diffusion interruption by a specified distance; and a third model including a third plurality of metrics associated with spacing the third edge apart from the diffusion interruption by a distance greater than a threshold. The first model may be selected in response to placing the third edge facing the first edge and spaced apart from the diffusion interruption by a specified distance. The second model may be selected in response to placing the third edge facing the second edge and spaced apart from the diffusion interruption by a specified distance. The third model may be selected in response to placing the third edge spaced apart from the diffusion interruption by a distance greater than a threshold.

[0008] The distance from the diffusion interrupt to the first edge may be less than a specified distance, and wherein a third edge facing the first edge is spaced from the first edge by a separation distance corresponding to a difference between the distance and the specified distance. The first unit may be a well tap unit. The second unit may be a delay unit.

[0009] The specified distance may be one of a plurality of specified distances, and at least a first corresponding simulation model and a second corresponding simulation model are associated with each of the plurality of specified distances. The first corresponding model may include a first plurality of metrics associated with placing the third edge facing the first edge and spaced apart from the diffusion interruption by a corresponding specified distance. The second corresponding model may include a second plurality of metrics associated with placing the third edge facing the second edge and spaced apart from the diffusion interruption by a corresponding specified distance.

[0010] Embodiments also relate to a first cell for designing an integrated circuit, the integrated circuit comprising a first edge, a second edge on an opposite side of the first edge of the first cell, and a diffusion region extending from the first edge to the second edge, the diffusion region having a diffusion break separating the diffusion region. The diffusion break can be spaced a distance from the second edge that varies beyond a threshold level, the threshold level being a measure of a second cell placed adjacent to the second edge.

[0011] In one embodiment, the first cell is a well tap cell. The second cell may be adjacent to the first cell or separated from the diffusion interruption (e.g., by causing the metric of the second cell to change by a user specified distance exceeding a threshold level). The second cell may be separated from the second edge by a distance corresponding to the difference between the distance and the user specified distance. In addition, the diffusion interruption may be separated from the first edge by a predetermined threshold distance such that the metric of a given cell placed adjacent to the first edge is not substantially affected by the diffusion interruption (i.e., the metric of the second cell does not change by more than the threshold level). The second edge may be to the left or to the right of the diffusion interruption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure will be more fully understood from the detailed description given below and from the drawings of the embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the present disclosure without limiting the scope of the present disclosure to these specified embodiments. In addition, the drawings are not necessarily drawn to scale.

[0013] Figure 1 An integrated circuit placement generated from cells is shown according to one embodiment.

[0014] Figure 2 A cell with a diffusion interruption according to one embodiment is shown.

[0015] Figure 3 A cell with a diffusion interrupt separated from the cell edge by a specified amount of gate spacing is shown according to one embodiment.

[0016] Figure 4 According to one embodiment, a Figure 3 The cell placement of the cell adjacent to the cell with diffusion interruption.

[0017] Figure 5 A cell placement according to one embodiment is shown, including adjacent cells to cells having diffusion breaks.

[0018] Figure 6 A cell placement according to one embodiment is shown, including cells separated from a diffusion break, without having cells abutting the diffusion break.

[0019] Figure 7 A cell placement according to one embodiment is shown, the cell placement comprising cells that are all spaced a specified number of gate pitches from a diffusion break.

[0020] Figure 8 A cell placement according to one embodiment is shown, the cell placement comprising cells that are all separated from a diffusion break by a specified number of gate pitches.

[0021] Fig. 9 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present invention.

[0022] Fig.10 An abstract diagram of an example computer system is depicted in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to several embodiments, examples of which are shown in the accompanying drawings. It should be noted that similar or similar reference numerals may be used in the accompanying drawings wherever feasible, and similar or similar functions may be indicated. The accompanying drawings depict embodiments of the disclosed systems (or methods) for illustrative purposes only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles described herein.

[0024] Embodiments are directed to designing an integrated circuit that includes at least one cell having a diffusion interruption spaced a distance from an edge of the cell, the distance causing a metric (e.g., delay, slew, dynamic power, and leakage) of another cell placed adjacent to the second edge to change by more than a threshold level. Other cells can be placed adjacent to the cell having the diffusion interruption, at a specified distance or gate pitch from the diffusion interruption, to be affected by the diffusion interruption exceeding a threshold level, or to avoid the impact from the diffusion interruption. This placement technique reduces the number of models required to capture the impact of the diffusion interruption on cells placed near the diffusion interruption, and enables efficient use of space in the integrated circuit.

[0025] A diffusion interruption as described herein refers to an interruption in a diffusion region extending from a first edge of a cell to a second edge opposite the first edge of the cell. A diffusion interruption may change (e.g., reduce or increase) the metric of a cell located near the diffusion interruption. Such a change may reduce the accuracy of the metric for estimating the cell design. Although the embodiments described herein may refer to a reduction in the metric of a cell caused by the placement of a cell near a diffusion interruption, the metric of a cell may also be increased as an effect of a diffusion interruption. For example, a diffusion interruption may increase or decrease the delay of a cell, resulting in an undesired acceleration or deceleration of a signal that reduces the accuracy of estimating the delay of the cell design.

[0026] The cells described herein refer to logical units for performing logical functions. One or more cells may be combined to form a physical unit. For example, a single physical unit of a multi-bit cell may include multiple logical unit cells.

[0027] EDA products may include software that generates integrated circuit layouts. In one embodiment, an EDA system receives a cell library that includes a set of cells designed to be placed side by side in rows. Figure 1 An example of a cell design is shown in the description of . The set of cells may include standard cells and modified versions of standard cells. The EDA system may generate at least a portion of the layout of the integrated circuit by arranging instances of cells from the library. The EDA system may connect instances of the cells together to achieve the desired functionality of the integrated circuit.

[0028] The EDA system can generate a grid layout design. In a gridded design, the edges of a circuit component (such as a cell) are aligned with a predetermined grid. In some embodiments, the transistor gates of a layout (e.g., layout 100) have a fixed distance between adjacent gates, wherein the fixed distance is generally equal to the contacted gate pitch, generally referred to as the contacted polysilicon pitch or CPP. The gate pitch can be a plurality of gate cells in a predetermined gate. As mentioned herein, the terms "gate pitch", "CPP", "placement gate" and "gate" can be used interchangeably to describe the cell size (e.g., width) and cell placement (e.g., the distance between the cell edges) within a layout design. The cell edge can be parallel to the transistor gate. In particular, the term "gate pitch" can be used herein to quantify the distance at which a cell is placed from another cell or a portion of another cell. For example, a cell can be placed D1 from the diffusion interruption of another cell, or placed D1 gate pitches from the diffusion interruption of another cell. Mentioning distances without specifying distance units, such as E, D, D1, etc., means that there is a distance unit in the gate pitch.

[0029] Example Integrated Circuit

[0030] Figure 1 An integrated circuit layout 100 generated from cells according to one embodiment is shown. Integrated circuit layout 100 includes cells 110, 120, and 130. The cells are organized into a single row, with dummy transistors 140a spanning the edges of cells 110 and 120, and another set of dummy transistors 140b spanning the edges of cells 110 and 130. Dummy transistors may be located at the edges of cells to isolate diffusion within the cell from diffusion of adjacent cells. Cells may be defined on four sides or edges and represent any general cell, such as an inverter, a NAND gate, a NOR gate, or a flip-flop. Although layout 100 is simplified for clarity, layout 100 may include additional cells not shown.

[0031] Cell 110 is bounded on one side by edge 104 and on an opposite side by edge 106. Diffusion regions 108 and 109 span from edge 104 to edge 106. Diffusion region 108 may be a p-type diffusion region (i.e., p-diffusion) and diffusion region 109 may be an n-type diffusion region (i.e., n-diffusion). Diffusion break 102 separates diffusion regions 108 and 109. That is, diffusion region 108 is divided into two electrically isolated regions: a region from edge 104 to diffusion break 102 and another region from diffusion break 102 to edge 106. Similarly, diffusion region 109 is also divided into two electrically isolated regions. In one example, standard cell 110 may be a well tap or TAP cell that includes diffusion break 102 and components not shown (e.g., an n-well and substrate contacts required to prevent latch-up). In FIG. Figure 2 and3 Other examples of cells with diffusion interrupts are described in the description of .

[0032] A diffusion interruption may reduce a metric of a cell located near the diffusion interruption. In some embodiments, the diffusion interruption affects at least one of delay, slew rate, dynamic power, and leakage of a cell placed nearby. The degree of reduction depends on the distance between another cell and the diffusion interruption. In some embodiments, a metric of a cell is affected by the diffusion interruption and will be reduced by more than a threshold level when the cell is placed within a certain distance of the diffusion interruption. For example, a metric of a cell placed within 10 gate pitches of a diffusion interruption may be reduced by more than a threshold level. The threshold level of metric reduction refers to the smallest non-zero reduction in the metric of a cell near the diffusion interruption. For example, depending on the technology, a diffusion interruption may increase the delay of an adjacent cell by 10-15% or increase the leakage of an adjacent cell by 50%. The diffusion effect may vary with transistor characteristics (e.g., threshold voltage). The term "threshold level" is used to refer to a threshold level of reduction of at least one metric. For example, a diffusion interruption may reduce a metric of a cell by more than a threshold level because the diffusion interruption increases dynamic power consumption by a minimum non-zero amount, although other metrics, such as delay or leakage, are not affected.

[0033] The reduction of a cell metric can be modeled in a derating table. In some embodiments, the EDA system generates a model or derating table that characterizes a metric (e.g., delay) of a cell placed near a diffusion interrupt. For example, a derating table for a cell can be characterized based on different combinations of the cell's input switching and output load. Figure 4 The generation of cell placement-based models and corresponding metrics is further described in the description of FIG-7.

[0034] Figure 1 Cells 120 and 130 are shown with dummy transistors 140a and 140b placed therein, which electrically isolate cells 120 and 130 from cell 110 having diffusion interruption 102. The gates of dummy transistors 140a and 140b can be connected to a power supply or ground to provide the desired electrical isolation. Each set of dummy transistors 140a and 140b can include one or more transistors spanning between the edge of cell 110 and the edge of cell 120 or 130. Due to the electrical isolation caused by dummy transistors 140a and 140b, diffusion interruption 102 does not degrade the metrics of cells 120 and 130.

[0035] Although layout 100 is shown with dummy transistors 140a and 140b, cells 120 and 130 may avoid degradation of the metric caused by diffusion interruption 102 if they are placed at a distance from diffusion interruption 102. For example, if the edge of cell 120 adjacent edge 104 is greater than 10 gate pitches from diffusion interruption 102, the metric of cell 120 may not be affected. However, if the edge of cell 130 adjacent edge 106 is ten gate pitches away from diffusion interruption 102, the metric of cell 130 may be reduced beyond a threshold level. Figure 4 An example of cell placement close to a diffusion break is described in the description of -7.

[0036] Example cell with diffusion interruption

[0037] Figure 2 A cell 200 having a diffusion interrupt 202 is shown according to one embodiment. Cell 200 is bounded by edges 204 and 206 and includes diffusion interrupt 202 and diffusion regions 208 and 209. Diffusion regions 208 and 209 extend from edge 204 to edge 206 and are separated by diffusion interrupt 202. Edge 204 is separated from diffusion interrupt 202 by D1, and edge 206 is separated from diffusion interrupt 202 by D2. D1 and D2 can be equal or different amounts of gate spacing in distance. Both D1 and D2 are greater than D from the diffusion interrupt. D can be defined as the maximum distance of a diffusion interrupt of a first cell (e.g., cell 200) to an edge of a second cell (not shown) on either side of the diffusion interrupt such that the diffusion interrupt reduces a metric of the second cell by more than a threshold level (e.g., the metric of the second cell does not meet the threshold level). That is, D is a predetermined threshold distance such that when a cell is placed at a distance greater than D from the diffusion interrupt, the metric of the cell is not affected by the diffusion interrupt or is not substantially changed by the diffusion interrupt. Thus, the metrics of another cell placed adjacent to edge 204 or 206 will not be affected by diffusion break 202. As referred to herein, a "safety edge" is a cell edge that is separated from the cell's diffusion break by more than D. For example, edges 204 and 206 are both safety edges of cell 200. In contrast, as in Figure 3 As described in the description of , another cell placed at a gate pitch number less than or equal to D will be affected above the threshold by the diffusion interruption 202.

[0038] Figure 3A cell 300 is shown with a diffusion interrupt 302 that is separated from a cell edge 306 by a specified number of gate pitches according to one embodiment. The cell 300 is bounded by edges 304 and 306 and includes the diffusion interrupt 302 and diffusion regions 308 and 309. Diffusion regions 308 and 309 extend from edge 304 to edge 306 and are separated by the diffusion interrupt 302. Edge 304 is separated from the diffusion interrupt 302 by D3, and edge 306 is separated from the diffusion region 306 by a specified number of gate pitches E that is less than or equal to D. This distance E is referred to herein as a "user-specified distance" or "specified distance". E may be a design parameter specified by a user of an EDA system. That is, cell placement near a diffusion interrupt may be strictly limited to being separated from the diffusion interrupt by E. A cell may be placed at E to the right of the diffusion interrupt 302 so that it is greater than D from the diffusion interrupt to its right. In some embodiments, a cell may not be placed at less than or equal to D to the right of the diffusion interrupt 302 unless the distance is exactly E. Likewise, a cell may be placed at E to the left of diffusion break 302 such that it is greater than D to the right of any diffusion break to its left.

[0039] D3 is greater than D and edge 304 is a safe edge. However, E is less than or equal to D. As referred to herein, a "critical edge" is an edge of a cell that is separated from the cell's diffusion break by E less than or equal to D. Edge 306 is a critical edge of cell 300. Another cell placed adjacent edge 306 may experience a metric reduction exceeding a threshold level due to proximity to diffusion break 302. However, another cell placed adjacent edge 304 will not be affected by diffusion break 302. Figure 4 The placement of cells near diffusion break 302 is described in more detail in the description of FIG.

[0040] Integrated Circuit Design Simulation Model

[0041] The EDA system can simulate the effect of a diffusion interruption on nearby cells and provide the simulation results to an EDA user using one or more models or derating tables. The derating table can be a metric matrix, wherein each value of the matrix includes one or more metrics that characterize the effect of a diffusion interruption on a cell placed at a given distance from the diffusion interruption. In some embodiments, the size of the matrix corresponds to the maximum distance at which a cell can be placed on either side of the diffusion interruption when experiencing a reduction in the metric that exceeds a threshold level. For example, a derating table having a size of D×D includes metrics for cells with gate spacings of 1, 2, ..., and D placed from one side of the diffusion interruption (e.g., to the left side of the diffusion interruption) and metrics for cells with gate spacings of 1, 2, ..., and D placed from the other side of the diffusion interruption (e.g., to the right side of the diffusion interruption).

[0042] Metrics such as delay, slew rate, dynamic power, and leakage may be included in the derating table. For example, the values ​​located in the first row and second column of the derating table may correspond to the effect of the diffusion interrupt on the leakage of another cell placed adjacent to the critical edge, which is one gate pitch from the left side of the diffusion interrupt or two gate pitches from the right side of the diffusion interrupt.

[0043] The derating table can be assembled from one or more models that capture the effect of diffusion interruption on one or more metrics. In addition, the values ​​of the derating table for a given dimension can vary depending on the different input slew and output load combinations that the nearby units are characterized for. Due to this variation, the number of models included in the derating table may increase. That is, a D×D derating table (e.g., D 2 Model) may be sufficient to characterize the metric for a single combination of input rotation and output load, but may require D for each of the various input rotation and output load combinations. 2 This increase can result in additional memory usage and computation time for cell characterization and timing analysis. Placing cells near diffusion interrupts as described herein can reduce the number of models required to capture the effects of diffusion interrupts in integrated circuit design simulations.

[0044] In some embodiments, the EDA system implements one or more design parameters during simulation of the integrated circuit design. For example, a specified distance of the E-gate pitch is a design parameter that causes cells in the integrated circuit design to be placed at a distance from the diffusion interrupt E-gate pitch.

[0045] By applying a specified distance of E gate spacing at which cells are placed, the EDA system reduces the number of models required to capture the effects of diffusion interruptions in integrated circuit design simulations. In particular, the EDA system can force cells in the integrated circuit design to be placed at a distance E or greater than D from the diffusion interruption.

[0046] The EDA system can use one or more of three derating models to characterize the impact of diffusion interruptions. These models are used to calculate the metrics of the cell based on the location of the cell near the diffusion interruption. The first model is associated with positioning the cell at a distance E from the first side of the diffusion interruption (e.g., the left side of the diffusion interruption), where the right edge of the cell is the critical edge and the left edge is the safe edge. The second model is associated with positioning the cell at a distance E from the second side of the diffusion interruption (e.g., the right side of the diffusion interruption), where the left edge of the cell is the critical edge and the right edge is the safe edge. The third model is associated with positioning a cell having a first side and a second side opposite to the first side, both of which are greater than D from the diffusion interruption. In some embodiments, the EDA system can use a fourth model that is associated with positioning the cell at E from the corresponding adjacent diffusion interruptions on both the first side of the cell and the second side opposite to the first side of the cell (i.e., a first cell having a diffusion interruption on the left side of the cell and a second cell having a diffusion interruption on the right side of the cell).

[0047] In some embodiments, the EDA system can use multiple user-specified distances to place the cell edge away from the diffusion interruption. The number of derating models required to calculate the cell metric increases with the number of user-specified distances. As described above, for one user-specified distance E, three models are required: a first model for placing the cell at the left side E of the diffusion interruption, a second model for placing the cell at the right side E of the diffusion interruption, and a third model for placing the cell greater than D on either side of the diffusion interruption. For two user-specified distances E and E', two more models are required: a fourth model for placing the cell at the left side E' of the diffusion interruption, and a fifth model for placing the cell at the right side E' of the diffusion interruption.

[0048] The number of models required for simulation can be determined or generated based on the cell placement design (e.g., the user-specified distance from the diffusion interruption and the number of critical edges for each cell). For example, the cells within the library can be constructed so that the cell can have only one critical edge, and the cell edges are restricted to placement at a user-specified distance of E or greater than D. In this way, only three models are required. In implementations where the cells within the library can be constructed to have multiple critical edges and the cell edges are restricted to locations of E or greater than D, four models may be required (i.e., an additional fourth model for placing cells to the left and right of the corresponding diffusion interruption of E).

[0049] The EDA system can select at least one of the first, second, and third models and perform a simulation of the integrated circuit design using the selected one or more models. In some embodiments, a fourth model is included for selection with the first three models. Each model can include metrics applied during simulation of cells appropriately positioned relative to the diffusion interrupt. For example, the EDA system can select the first model to apply a corresponding metric to a cell of E located to the left of the diffusion interrupt. Figure 4 The description of -6 describes the EDA system's choice of model.

[0050] Example cell placement near a diffusion break

[0051] Figure 4 6 shows an example of cell placement near a diffusion break according to an embodiment. The effect of a diffusion break on nearby cells may depend on the distance that the edges of the nearby cells are spaced from the diffusion. Figure 4 Each of the examples of -6 is described herein with respect to the depicted placement and simulation thereof using one or more models or derating tables. Each example shows at least one cell being placed at a specified distance E from the diffusion interruption.

[0052] Figure 4 According to one embodiment, a Figure 3 4 shows a cell placement of cells with diffusion breaks adjacent to cells of 400. Cell placement 400 shows cells 420 and 430 adjacent to cell 300 with diffusion break 302. Cell 420 is adjacent to edge 304, which is a safety edge separated from diffusion break 302 by D3. The metrics of cell 420 are not affected by diffusion break 302 because it is placed near the safety edge. In contrast, the metrics of cell 430 are affected by diffusion break 302 exceeding a threshold level because cell 430 is adjacent to edge 306, which is a critical edge separated from diffusion break 302 by E. D6 is greater than D, so cell 430 is not affected by diffusion break 452 in cell 450 placed to its right. D4 is greater than D, and edge 436 of cell 430 is a safety edge. Another cell placed adjacent to edge 436 will not be affected by diffusion break 302, but it may be affected by diffusion break 452 in cell 450 if its right edge is less than D from diffusion break 452. As shown in FIG. Figure 4 As shown, cell 430 is placed adjacent to cell 300 and E away from diffusion interruption 302. However, cells may be placed separated from the edge by E instead of being adjacent to E (i.e., not adjacent to the edge). Figure 6 Such an example is described in the description of .

[0053] In addition, cell placement 400 includes cell 440 with diffusion break 442 and cell 450 with diffusion break 452. Both D5 and D6 are greater than D. Edge 424 of cell 420 is spaced D5 from diffusion break 442 and thus maintains a safety margin greater than D from diffusion breaks 442 and 302. Likewise, edge 436 of cell 430 maintains a safety margin greater than D from diffusion breaks 452 and 302. Therefore, diffusion breaks 442 and 452 do not affect the metrics of cells 420 and 430, respectively. Since edge 306 is a critical edge, cell 430 is still affected by diffusion break 302.

[0054] Cell placement 400 can be simulated by the EDA system using two models. The EDA system can select a third model for simulation, where the third model includes metrics associated with positioning cell 420 at a distance greater than D from diffusion interruption 302. Additionally, the EDA system can select a second model for simulation, where the second model includes metrics associated with positioning cell 430 at a distance E to the right of diffusion interruption 302.

[0055] In some embodiments, although not in Figure 4 , but cell 440 may be positioned so that diffusion interruption 442 is away from edge 424, so that cell 420 has a critical edge (edge ​​424) and a safe edge (edge ​​304). In this cell placement, the EDA system may simulate cells 420 and 430 using a second model, wherein the second model includes metrics associated with positioning cells 420 and 430 at the right side E from diffusion interruption 442 and 302, respectively.

[0056] In some embodiments, unit placement 400 may include a physical unit formed from one or more logical units. For example, units 300 and 430 may be logical units that are merged to form a single physical unit. The functionality of the physical unit is equivalent to Figure 4 300 and 430 are shown. That is, the physical cell includes a diffusion region having diffusion break 302 and includes a logic function (e.g., an AND function) from cell 430. Just as the left edge of cell 300 and the right edge of cell 430 are each separated from diffusion break 302 by more than D, the left and right edges of the physical cell are also separated from diffusion break 302 by more than D. Therefore, cells placed adjacent to the physical cell are not affected by diffusion break 302 and therefore do not experience performance changes that exceed a threshold level.

[0057] Figure 5A cell placement according to one embodiment is shown, including cells adjacent to a cell with a diffusion break. Cell placement 500 shows cells 520 and 530 adjacent to cell 510 with a diffusion break 502. Cell 520 is adjacent to edge 504, which is a critical edge separated from diffusion break 502 by E. The metric of cell 520 is affected by diffusion break 502 exceeding a threshold level because it is placed near the critical edge. However, the metric of cell 530 is not affected by diffusion break 502 because cell 530 is adjacent to edge 506, which is a safety edge separated from diffusion break 502 by D3, where D3 is greater than D. Edge 524 of cell 520 is a safety edge. Another cell placed adjacent to edge 524 will not be affected by diffusion break 502. Although not shown, additional cells with diffusion breaks can be placed to the left of cell 520 or to the right of cell 530 so that the diffusion breaks of the additional cells are separated from edges 524 or 536 by more than D.

[0058] In addition, cell placement 500 includes cell 540 with diffusion break 542 and cell 550 with diffusion break 552. Both D5 and D6 are greater than D. Edge 524 of cell 520 is a safety margin that is separated from diffusion breaks 542 and 502 by greater than D. Similarly, edge 536 of cell 530 is separated from diffusion breaks 552 and 502 by greater than D, thus maintaining a safety margin. Therefore, diffusion breaks 542 and 552 do not affect the metrics of cells 520 and 530, respectively. However, since edge 504 is a critical edge, cell 520 is still affected by diffusion break 502.

[0059] Cell placement 500 can be simulated by an EDA system using two models. The EDA system can select a first model for simulation, where the first model includes metrics associated with positioning cell 520 at a distance E to the left of diffusion interruption 502. Additionally, the EDA system can select a third model for simulation, where the third model includes metrics associated with positioning cell 530 at a distance greater than D from diffusion interruption 502.

[0060] Figure 6A cell placement according to one embodiment is shown that includes a cell separated from a diffusion break without abutting the cell with the diffusion break. Cell placement 600 includes cell 620 that is not abutting edge 604, which is a critical edge separated from diffusion break 602 by e gate pitch, where E gate pitch is the number of gate pitches less than E gate pitch. In some embodiments, the EDA system can determine to place cell 620 at a separation distance away from edge 604 that corresponds to the gate pitch difference between E and e (i.e., E-e). The metrics of cell 620 are affected by diffusion break 602 exceeding a threshold level because it is separated from diffusion break 602 by a specified distance E. However, the metrics of cell 630 are not affected by diffusion break 602 because cell 630 abuts edge 606, which is a safe edge separated from diffusion break 602 by D3, where D3 is greater than D. Edge 624 of cell 620 is a safe edge. Another cell placed adjacent to edge 624 will not be affected by diffusion break 602. In some embodiments, an additional cell having a diffusion break can be placed to the left of cell 620 or to the right of cell 630 such that the diffusion break of the additional cell is separated from edge 624 or 636 by more than D. For example, cell 640 is placed to the left of cell 620 such that diffusion break 642 of cell 640 is separated from edge 624 by D5, where D5 is greater than D.

[0061] Although edge 604 is separated from diffusion break 602 by e, the EDA system can implement design parameters that force cell 620 to be placed separated from diffusion break 602 by E instead of e. In this way, the EDA system only needs to select a first model for simulation, where the first model includes metrics associated with positioning cell 620 at E to the left of diffusion break 602, rather than selecting another model associated with positioning cell 620 at E to the left of diffusion break 602. In addition, the EDA system can select a third model for simulation, where the third model includes metrics associated with positioning cell 630 at a distance greater than D from diffusion break 602. This reduces the number of models required for simulation.

[0062] Figure 7A cell placement according to one embodiment is shown, which includes cells that are each separated from a diffusion interruption by a specified distance of E-gate pitch. Cell placement 700 includes cells 720 and 730 that are adjacent to edges 704 and 706, respectively, of cell 710 having a diffusion interruption 702. Edges 704 and 706 are both critical edges because edges 704 and 706 are separated from diffusion interruption 702 by a specified number of E-gate pitches. Therefore, cells 720 and 730 are affected by diffusion interruption 702 exceeding a threshold level. Edge 724 of cell 720 and edge 736 of cell 730 are safe edges. Cells placed adjacent to edge 724 or edge 736 will not be affected by diffusion interruption 702. Cell 740 with diffusion interruption 742 can be placed on the left side of cell 720, while cell 750 with diffusion interruption 752 can be placed on the right side of cell 730. Diffusion break 742 is separated from edge 724 by D5, and diffusion break 752 is separated from edge 736 by D6, where both D5 and D6 are greater than D. Therefore, the EDA system can select a first model and a second model for simulation, where the first model includes metrics associated with positioning cell 720 at E from the left side of diffusion break 702 and the second model includes metrics associated with positioning cell 730 at E from the right side of diffusion break 702.

[0063] Figure 8 A cell placement according to one embodiment is shown, which includes cells that are each separated from a diffusion interruption by a specified distance of E gate pitches. Cell placement 800 includes cells 820 and 830 that are adjacent to edges 804 and 806 of cell 810 having diffusion interruption 802, respectively. Edges 804 and 806 are critical edges because edges 804 and 806 are separated from diffusion interruption 802 by E gate pitches. Similarly, edges 824 and 836 are critical edges because they are separated from diffusion interruptions 842 and 852 by E gate pitches, respectively. Therefore, the EDA system can select a fourth model to simulate cell placement 800 with cells 820 and 830, each with two critical edges. The fourth model can include metrics associated with positioning cell 820 at E from diffusion interruptions 842 and 802 at its two edges and positioning cell 830 at E from diffusion interruptions 852 and 802 at its two edges.

[0064] Example Electronic Design Automation System and Workflow

[0065] Fig. 9A set of exemplary processes 900 are shown for use during the design, verification, and manufacture of an article such as an integrated circuit to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" represents the term "electronic design automation". These processes begin with the creation of a product concept 910 with information provided by a designer, which is transformed to create an article using a set of EDA processes 912. When the design is complete, the design is taped out 934, which is when the graphics (e.g., geometric patterns) of the integrated circuit are sent to a manufacturing facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die 936 are manufactured, and packaging and assembly processes 938 are performed to produce a completed integrated circuit 940.

[0066] The specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description languages. High-level abstractions can be used to design circuits and systems using hardware description languages ​​("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be converted into a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction, as a less abstract description, adds more useful details to the design description, for example, more details of the modules that comprise the description. Abstract descriptions with a lower degree of abstraction can be computer-generated, derived from a design library, or created by another design automation process. An example of a lower-level specification language for specifying a more detailed abstract language is SPICE, which is used for detailed descriptions of circuits with many simulation components. The description of each abstraction layer can be used by the corresponding tools (e.g., formal verification tools) for that layer.

[0067] During system design 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. The design can be divided into different types of modules or components at this stage.

[0068] During logic design and functional verification 916, modules or components in a circuit are specified in one or more description languages ​​and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the designed circuit or system. Functional verification can use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a specified system of components referred to as a "simulator" or "prototype system" is used to accelerate functional verification.

[0069] During synthesis and design of test 918, the HDL code is converted to a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the completed integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0070] During netlist verification 920, the netlist is checked for compliance with timing constraints and compliance with the HDL code. During design planning 922, an overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0071] During layout or physical implementation 924, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) occur, and selection of cells from the library can be performed to enable specified logic functions. The cell design and placement techniques described herein can be applied by EDA products during layout or physical implementation 924. As used herein, the term "cell" can specify a group of transistors, other components and interconnections that provide Boolean logic functions (e.g., AND, OR, INV, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and simulations. Parameters are specified for the selected cell (based on the "cell"), such as size, and made accessible in a database for use by the EDA product.

[0072] During analysis and extraction 926, circuit functionality is verified at the layout level, which allows the layout design to be improved. During physical verification 928, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit device functionality matches the HDL design specifications. During resolution enhancement 930, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0073] During tape-out, data is created for producing lithographic masks (after applying lithographic enhancements, if appropriate).During mask data preparation 932, the "tape-out" data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0074] The storage subsystem of a computer system (such as Fig.10 The computer system 1000 may be used to store programs and data structures used by some or all of the EDA products described herein, and for developing units of the library and physical and logical design products using the library.

[0075] General computer system applications

[0076] Fig.10 An exemplary machine of computer system 1000 is shown in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0077] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be understood to include a collection of any machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0078] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018 that communicate with each other via a bus 1030.

[0079] The processing device 1002 represents one or more processors such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1002 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1002 can be configured to execute instructions 1026 for performing the operations and steps described herein.

[0080] The computer system 1000 may also include a network interface device 1008 for communication with a network interface device 1008. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generating device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0081] The data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software implementing any one or more of the methods or functions described herein. During execution of the instructions 1026 by the computer system 1000, the instructions 1026 may also reside completely or at least partially within the main memory 1004 and / or within the processing device 1002, which also constitute machine-readable storage media.

[0082] In some implementations, the instructions 1026 include instructions that implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 1024 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 1002 to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0083] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0084] It should be remembered, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from this disclosure, it should be understood that throughout the specification certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0085] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays provided herein do not inherently relate to any specified computer or other device. According to the teachings herein, various other systems may be used together with the program, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is described without reference to any specified programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present invention described herein.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0088] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to its specified example implementation. Obviously, various modifications may be made thereto without departing from the broader spirit and scope of the implementation of the present disclosure as set forth in the following claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings are considered to be illustrative rather than restrictive.

[0089] Additional Configuration Considerations

[0090] Example benefits and advantages of the disclosed configuration include improved efficiency in terms of increased design space utilization, memory usage, and processing consumption. The disclosed cell design and placement techniques were implemented in an experimental semiconductor process to utilize space around cells (e.g., TAP cells) with diffusion interruptions. Compared to conventional methods that do not use space near the TAP cell or increase the size of the cell with diffusion interruptions, the cell design and placement techniques disclosed herein increase the available area for cell placement by more than 1.5%, with minimal reduction in design performance. For example, the placement techniques described herein can avoid the need to pad the edges of the TAP cell with dummy transistors (e.g., at least 10 dummy transistors) to isolate other cells from its diffusion interruption, but will occupy space. Therefore, the techniques described herein allow for efficient use of space within an integrated circuit design. In addition, compared to conventional methods that use complex models that result in large cell model sizes (e.g., increasing the model size by two orders of magnitude), the cell design and placement techniques disclosed herein only double the model size. By reducing the model size required to capture the diffusion interruption effect, the techniques described herein effectively use the memory and processing resources of the EDA tool.

[0091] In addition, the placement techniques described herein can increase the intentional delay introduced by the delay cell. In some embodiments, space near the critical edge can be reserved specifically for the delay cell in the initial design phase, which can correct the hold time violation. Alternatively, the space can be reserved for any cell inserted during the later timing closure. In these embodiments, during the initial design phase (e.g., physical synthesis and pre-routing design phase), the reserved space near the critical edge (i.e., restricted area) is blocked and opened for holding fixed or later timing closure changes. In the case of a hold time change, there may be an additional benefit, that is, when adjacent to the critical edge, the delay cell has a larger delay, which is desirable for a fixed hold time violation.

[0092] Throughout the specification, multiple instances can be implemented as components, operations or structures described as single instances. Although the individual operations of one or more methods are shown and described as separate operations, one or more of the individual operations can be performed simultaneously, and these operations are not required to be performed in the order shown. The structure and function presented as a separate component in the example configuration can be implemented as a combined structure or component. Similarly, the structure and function presented as a single component can be implemented as a separate component. These and other changes, modifications, additions and improvements fall within the scope of this paper theme.

[0093] Certain embodiments are described herein as including logic or multiple components, modules, or mechanisms. Modules may constitute software modules (e.g., code contained on a machine-readable medium or in a transmission signal) or hardware modules. A hardware module is a tangible unit capable of performing certain operations and may be configured or placed in a certain manner. In an example embodiment, one or more computer systems (e.g., stand-alone, client or server computer systems) or one or more hardware modules of a computer system (e.g., a processor or a group of processors) may be configured by software (e.g., an application or application portion) as a hardware module that operates to perform certain operations as described herein.

[0094] In various embodiments, hardware modules can be implemented mechanically or electronically. For example, a hardware module may include dedicated circuits or logic that are permanently configured (e.g., as a dedicated processor, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)) to perform certain operations. A hardware module may also include programmable logic or circuits (e.g., included in a general purpose processor or other programmable processor) that are temporarily configured by software to perform certain operations. It should be understood that the decision to implement a hardware module mechanically, in a dedicated and permanently configured circuit, or in a temporarily configured circuit (e.g., configured by software) may be driven by cost and time considerations.

[0095] Therefore, the term "hardware module" should be understood to include a tangible entity, that is, an entity that is physically constructed, permanently configured (e.g., hardwired) or temporarily configured (e.g., programmed), to operate in a certain manner or perform certain operations described herein. As used herein, a "hardware-implemented module" refers to a hardware module. Considering an embodiment in which a hardware module is temporarily configured (e.g., programmed), each hardware module need not be configured or instantiated at any one time. For example, in the case where the hardware module includes a general-purpose processor configured using software, the general-purpose processor can be configured as different hardware modules at different times. The software can configure the processor accordingly, for example, to constitute a specified hardware module at one time and to constitute a different hardware module at a different time.

[0096] Hardware modules can provide information to other hardware modules and receive information from other hardware modules. Therefore, the described hardware modules can be considered to be communicatively coupled. In the case where multiple such hardware modules exist at the same time, communication can be achieved by signal transmission (e.g., through appropriate circuits and buses) connecting the hardware modules. In an embodiment where multiple hardware modules are configured or instantiated at different times, communication between such hardware modules can be achieved, for example, by storing and retrieving information in a memory structure accessible to multiple hardware modules. For example, a hardware module can perform an operation and store the output of the operation in a memory device that is communicatively coupled with it. Then, another hardware module can access the memory device at a later time to retrieve and process the stored output. The hardware module can also initiate communication with an input or output device and can operate on a resource (e.g., a collection of information).

[0097] The various operations of the example methods described herein may be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform related operations. Regardless of whether they are temporarily configured or permanently configured, these processors may constitute processor-implemented modules that operate to perform one or more operations or functions. In some exemplary embodiments, the modules mentioned herein may include processor-implemented modules.

[0098] Similarly, the methods described herein may be implemented at least in part by a processor. For example, at least some of the operations of the method may be performed by one or more processors or a hardware module implemented by the processor. The performance of certain operations may be distributed among one or more processors, not only residing in a single machine, but also deployed on multiple machines. In some example embodiments, one or more processors may be located at a single location (e.g., in a home environment, an office environment, or as a server farm), while in other embodiments, the processors may be distributed at multiple locations.

[0099] The one or more processors may also be operable to support execution of related operations in a "cloud computing" environment or as "software as a service" (SAAS). For example, at least some operations may be performed by a group of computers (as an example of a machine including a processor), which may be accessed via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., an application program interface (API)).

[0100] The performance of certain operations may be distributed among one or more processors, not only residing in a single machine, but also deployed on multiple machines. In some exemplary embodiments, the one or more processors or processor-implemented modules may be located in a single geographic location (e.g., in a home environment, an office environment, or a server farm). In other exemplary embodiments, the one or more processors or processor-implemented modules may be distributed across multiple geographic locations.

[0101] Some parts of this specification are presented in the form of algorithms or symbolic representations of data stored as bits or binary digital signals in machine memory (e.g., computer memory) for operating. These algorithms or symbolic representations are examples of techniques used by those of ordinary skill in the field of data processing to convey the essence of their work to other technical personnel in the field. As used herein, an "algorithm" is a self-consistent sequence of operations or similar processes that lead to a desired result. In this context, algorithms and operations involve the physical manipulation of physical quantities. Typically, but not necessarily, these quantities can take the form of electrical, magnetic or optical signals that can be stored, accessed, transmitted, combined, compared or otherwise manipulated by a machine. Mainly for general reasons, it is sometimes convenient to use words such as "data", "content", "bit", "value", "element", "symbol", "character", "term", "number", "digital" to refer to such signals. However, these words are merely convenient labels and are associated with appropriate physical quantities.

[0102] Unless expressly stated otherwise, discussions herein using words such as "process," "compute," "calculate," "determine," "present," "display," and the like may refer to the actions or processes of a machine (e.g., a computer) that manipulates or transforms data represented as physical (e.g., electrical, magnetic, or optical) quantities within one or more memories (e.g., volatile memory, non-volatile memory, or a combination thereof), registers, or other machine components that receive, store, transmit, or display information.

[0103] As used herein, any reference to "one embodiment" or "an embodiment" means that the specified elements, features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment. The appearances of the phrase "in one embodiment" in different places in the specification do not necessarily all refer to the same embodiment.

[0104] When values ​​are described as "approximately" or "substantially" (or their derivatives), these values ​​should be interpreted as being exactly + / - 10%, unless another meaning is obvious from the context. For example, "about 10" should be understood to mean "within the range of 9 to 11".

[0105] Some embodiments may be described using the expressions "coupled" and "connected" and their derivatives. It should be understood that these terms are not intended to be synonymous with each other. For example, some embodiments may be described using the term "connected" to indicate that two or more elements are in direct physical or electrical contact with each other. In another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more elements that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments are not limited to this context.

[0106] As used herein, the terms "comprises," "comprising," "including," "containing," "having," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a series of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" refers to an inclusive or and not an exclusive or. For example, any of the following satisfies condition A or B: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0107] In addition, "a" or "an" is used to describe the elements and components of the embodiments herein. This is done only for convenience and to give a general sense of the invention. The description should be understood to include one or at least one, and the singular also includes the plural, unless otherwise clearly indicated.

[0108] After reading this disclosure, those skilled in the art will recognize additional alternative structural and functional designs for systems and processes for cell design and placement in continuous diffusion semiconductor processes through the principles disclosed herein. Therefore, although specified embodiments and applications have been illustrated and described, it should be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations that are obvious to those skilled in the art may be made to the placement, operation and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims.

Claims

1. A method comprising: Place the first unit on one side of the second unit, wherein the first cell comprises a first edge, a second edge at an opposite side of the first edge of the first cell, and a diffusion region extending from the first edge to the second edge, wherein a diffusion break separates the diffusion regions, and wherein the second cell includes a third edge, the third edge facing the first edge and spaced apart from the diffusion interruption by a specified distance, the specified distance causing the metric of the second cell to decrease beyond a threshold level; selecting from a plurality of simulation models, wherein each simulation model of the plurality of simulation models is associated with a respective edge of a given cell spaced apart from a given diffusion interruption by a corresponding specified distance less than or equal to a threshold distance; as well as A simulation of the second unit is performed using a selected simulation model from among the plurality of simulation models.

2. The method according to claim 1, wherein the plurality of simulation models comprises: a first model including a first plurality of metrics associated with positioning the third edge facing the first edge and spaced the specified distance from the diffusion interruption; a second model including a second plurality of metrics associated with positioning the third edge facing the second edge and spaced the specified distance from the diffusion interruption; as well as A third model includes a third plurality of metrics associated with placing the third edge spaced apart from the diffusion interruption by more than the threshold distance.

3. The method of claim 2, wherein selecting from the plurality of simulation models comprises: selecting the first model in response to positioning the third edge facing the first edge and spaced apart from the diffusion interruption by the specified distance; as well as The second model is selected in response to positioning the third edge facing the second edge and spaced the specified distance from the diffusion interruption.

4. The method of claim 1 , wherein a distance from the diffusion interruption to the first edge is less than the specified distance, and wherein the third edge facing the first edge is spaced apart from the first edge by a separation distance corresponding to a difference between the distance and the specified distance.

5. The method of claim 1 , wherein the specified distance is one of a plurality of specified distances, and at least a first corresponding simulation model and a second corresponding simulation model are associated with each of the plurality of specified distances, wherein: The first respective model includes a first plurality of metrics associated with placing the third edge facing the first edge and spaced apart from the diffusion interruption by the respective specified distance, and The second respective model includes a second plurality of metrics associated with positioning the third edge facing the second edge and spaced apart from the diffusion break by the respective specified distance. The method of claim 1 , wherein the first cell is a well tap cell and the second cell is a delay cell.

7. The method according to claim 1, wherein the first unit and the second unit are logical units included as a same physical unit.

8. A system for designing an integrated circuit design, the system comprising: a non-transitory computer-readable medium including stored instructions; as well as one or more processors coupled to the non-transitory computer-readable medium and configured to execute the stored instructions, which when executed cause the one or more processors to: Place the first unit on one side of the second unit, wherein the first cell comprises a first edge, a second edge at an opposite side of the first edge of the first cell, and a diffusion region extending from the first edge to the second edge, wherein a diffusion break separates the diffusion regions, and wherein the second cell includes a third edge, the third edge facing the first edge and spaced apart from the diffusion interruption by a specified distance, the specified distance causing the metric of the second cell to decrease beyond a threshold level; selecting from a plurality of simulation models, wherein each simulation model of the plurality of simulation models is associated with a respective edge of a given cell spaced apart from a given diffusion interruption by a corresponding specified distance less than or equal to a threshold distance; as well as A simulation of the second unit is performed using the selected simulation model from among the plurality of simulation models.

9. The system of claim 8, wherein the plurality of simulation models comprises: a first model including a first plurality of metrics associated with positioning the third edge facing the first edge and spaced the specified distance from the diffusion interruption; a second model including a second plurality of metrics associated with positioning the third edge facing the second edge and spaced the specified distance from the diffusion interruption; as well as A third model includes a third plurality of metrics associated with placing the third edge spaced apart from the diffusion interruption by more than the threshold distance.

10. The system of claim 9, wherein selecting from the plurality of simulation models comprises: selecting the first model in response to positioning the third edge facing the first edge and spaced apart from the diffusion interruption by the specified distance; as well as The second model is selected in response to positioning the third edge facing the second edge and spaced the specified distance from the diffusion interruption.

11. The system of claim 8, wherein a distance from the diffusion interruption to the first edge is less than the specified distance, and wherein the third edge facing the first edge is spaced apart from the first edge by a separation distance corresponding to a difference between the distance and the specified distance.

12. The system of claim 8, wherein the specified distance is one of a plurality of specified distances, and at least a first corresponding simulation model and a second corresponding simulation model are associated with each of the plurality of specified distances, wherein: The first respective model includes a first plurality of metrics associated with placing the third edge facing the first edge and spaced apart from the diffusion interruption by the respective specified distance, and The second respective model includes a second plurality of metrics associated with placing a third edge facing the second edge and spaced apart from the diffusion interruption by the respective specified distance.

13. The system of claim 8, wherein the first cell is a well tap cell and the second cell is a delay cell.

14. The system of claim 8, wherein the first unit and the second unit are logical units included as a same physical unit.

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