A semiconductor packaging structure and a method for preparing the same

Abstract

The present disclosure embodiment discloses a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having an exposed first surface, the first surface having a silicon-containing surface; a second semiconductor chip structure located on the first surface of the first semiconductor chip; the second semiconductor chip structure having a second surface opposite to the first surface; a first packaging compound structure, the first packaging compound structure having a bonding surface, the bonding surface at least covering the first surface of the first semiconductor chip and the second surface of the second semiconductor chip structure; wherein the bonding surface has a silicon-containing surface.

Description

Technical Field

[0001] The present disclosure relates to the field of three-dimensional process technology, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] In the existing packaging structure, molding material is used for packaging. However, the thermal expansion coefficient of the molding material is significantly different from that of the silicon substrate in the chip, which makes it impossible to reduce the thickness of the chip. When the DRAM chips are stacked higher and higher, problems such as warping or damage will occur, affecting the performance of the device. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor package structure, including:

[0005] substrate;

[0006] A first semiconductor chip is located on the substrate, the first semiconductor chip has an exposed first surface, and the first surface has a silicon-containing surface;

[0007] A second semiconductor chip structure is located on the first surface of the first semiconductor chip; the second semiconductor chip structure has a second surface opposite to the first surface;

[0008] A first encapsulation compound structure has a bonding surface, the bonding surface at least covers the first surface of the first semiconductor chip and the second surface of the second semiconductor chip structure; wherein the bonding surface has a silicon-containing surface.

[0009] In some embodiments, the second semiconductor chip structure includes a plurality of stacked second semiconductor chips, and the package structure further includes:

[0010] a second packaging compound structure; the second packaging compound structure is bonded to the first packaging compound structure to encapsulate the second semiconductor chip structure; wherein,

[0011] The second encapsulation compound structure includes a silicon-containing compound.

[0012] In some embodiments, it also includes:

[0013] A conductive bump is located between the first semiconductor chip and the second semiconductor chip structure, and between two adjacent layers of the second semiconductor chips;

[0014] The first potting compound structure and the second potting compound structure encapsulate the conductive bump.

[0015] In some embodiments, an outer surface of the conductive bump has a silicon-containing surface.

[0016] In some embodiments, the number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of the second semiconductor chip structures are arranged in parallel on the first surface of the first semiconductor chip.

[0017] In some embodiments, it also includes:

[0018] The filling layer is located at the periphery of the second semiconductor chip structure and / or between two adjacent second semiconductor chip structures; wherein,

[0019] The Young's modulus of the filling layer is greater than the Young's modulus of the potting compound structure.

[0020] In some embodiments, the material of the filling layer includes glass fiber or carbon fiber.

[0021] In some embodiments, a Young's modulus of the first potting compound structure is less than a Young's modulus of the second potting compound structure.

[0022] In some embodiments, the second encapsulation compound structure includes multiple layers of second encapsulation compound stacked in sequence, each layer of the second encapsulation compound encapsulating a layer of the second semiconductor chip;

[0023] Along the direction from the first semiconductor chip to the second semiconductor chip structure, the Young's modulus of each layer of the second encapsulation compound gradually increases.

[0024] According to a second aspect of an embodiment of the present disclosure, there is provided a method for preparing a semiconductor package structure, comprising:

[0025] providing a substrate;

[0026] A first semiconductor chip is formed on the substrate; the first semiconductor chip has an exposed first surface, and the first surface has a silicon-containing surface;

[0027] forming a first layer of second semiconductor chips on the first surface of the first semiconductor chip; the first layer of second semiconductor chips having a second surface opposite to the first surface;

[0028] A first packaging compound structure is formed between the first semiconductor chip and the first layer second semiconductor chip by spin coating; the first packaging compound structure has a bonding surface, and the bonding surface at least covers the first surface of the first semiconductor chip and the second surface of the first layer second semiconductor chip; wherein the bonding surface has a silicon-containing surface.

[0029] In some embodiments, it also includes:

[0030] forming one or more layers of second semiconductor chips on the first layer of second semiconductor chips to form a second semiconductor chip structure;

[0031] A second packaging compound structure encapsulating the second semiconductor chip structure is formed by spin coating, and the second packaging compound structure is bonded to the first packaging compound structure; wherein,

[0032] The second encapsulation compound structure includes a silicon-containing compound.

[0033] In some embodiments, it also includes:

[0034] forming a first layer of second encapsulation compound encapsulating the first layer of second semiconductor chips by spin coating;

[0035] forming a second layer of second semiconductor chips on the first layer of second semiconductor chips;

[0036] forming a second layer of second packaging compound encapsulating the second layer of second semiconductor chip by spin coating;

[0037] Repeating in sequence until an Nth layer of the second packaging compound is formed to encapsulate the last layer of the second semiconductor chip; wherein N is greater than or equal to 2;

[0038] The multiple layers of second potting compound form a second potting compound structure including a silicon-containing compound.

[0039] In some embodiments, the multiple layers of the second semiconductor chip form a second semiconductor chip structure;

[0040] The number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of second semiconductor chip structures are formed in parallel on the first surface of the first semiconductor chip.

[0041] In some embodiments, after forming the second encapsulation compound structure, the method further comprises:

[0042] Etching to form a through hole at the periphery of the second semiconductor chip structure and / or between two adjacent second semiconductor chip structures;

[0043] The through hole is filled to form a filling layer; wherein the Young's modulus of the filling layer is greater than the Young's modulus of the first encapsulation compound structure and the second encapsulation compound structure.

[0044] In some embodiments, the material of the filling layer includes glass fiber or carbon fiber.

[0045] In some embodiments, a Young's modulus of the first potting compound structure is less than a Young's modulus of the second potting compound structure.

[0046] In the disclosed embodiment, the bonding surface of the first packaging compound structure and the surface of the chip both contain silicon elements, that is, they are both silicon surfaces. Compared with packaging with molding compound, the bonding performance of the interface can be improved, thereby improving problems such as warping and damage of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1a A schematic diagram of the structure of a semiconductor package provided by an embodiment of the present disclosure;

[0049] Figure 1b A schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure;

[0050] Figure 2 A schematic structural diagram of a semiconductor package structure provided by yet another embodiment of the present disclosure;

[0051] Figure 3 A schematic diagram of a process for preparing a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0052] Figure 4a to Figure 4g A schematic diagram of the structure of a semiconductor packaging structure during the preparation process provided by an embodiment of the present disclosure;

[0053] Figure 5a to Figure 5e A schematic structural diagram of a semiconductor packaging structure during the preparation process provided by another embodiment of the present disclosure.

[0054] Description of reference numerals:

[0055] 10-substrate; 20-adhesion layer;

[0056] 30-first semiconductor chip; 311-first surface;

[0057] 40 - second semiconductor chip structure; 41 - first layer second semiconductor chip; 42 - second layer second semiconductor chip; 43 - third layer second semiconductor chip; 44 - fourth layer second semiconductor chip; 411 - second surface;

[0058] 51-first packaging compound structure; 52-second packaging compound structure; 521-first layer of second packaging compound; 522-second layer of second packaging compound; 523-third layer of second packaging compound; 524-fourth layer of second packaging compound;

[0059] 60 - conductive bump; 611 - silicon-containing surface of the conductive bump;

[0060] 70-filling layer. DETAILED DESCRIPTION

[0061] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0063] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0065] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0068] An embodiment of the present disclosure provides a semiconductor packaging structure. Figure 1a A schematic diagram of the structure of a semiconductor package provided in an embodiment of the present disclosure.

[0069] See also Figure 1a The semiconductor packaging structure includes: a substrate 10; a first semiconductor chip 30, located on the substrate 10, the first semiconductor chip 30 having an exposed first surface 311, the first surface 311 having a silicon-containing surface; a second semiconductor chip structure 40, located on the first surface 311 of the first semiconductor chip 30; the second semiconductor chip structure 40 having a second surface 411 opposite to the first surface 311; a first packaging compound structure 51, the first packaging compound structure 51 having a bonding surface, the bonding surface at least covering the first surface 311 of the first semiconductor chip 30 and the second surface 411 of the second semiconductor chip structure 40; wherein the bonding surface has a silicon-containing surface.

[0070] In the disclosed embodiment, the bonding surface of the first packaging compound structure and the surface of the chip both contain silicon elements, that is, they are both silicon surfaces. Compared with packaging with molding compound, the bonding performance of the interface can be improved, thereby improving problems such as warping and damage of the packaging structure.

[0071] The material of the silicon-containing surface of the first encapsulation compound structure 51 may be spin-on glass (SOG), spin-on dielectric (SOD) containing silicon, or other spin-on materials containing silicon.

[0072] The substrate 10 may be a single semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material silicon germanium (SiGe) substrate, etc., or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0073] In one embodiment, the first semiconductor chip 30 is a logic chip.

[0074] In one embodiment, the semiconductor package structure further includes: an adhesive layer 20, located between the substrate 10 and the first semiconductor chip 30, for bonding the substrate 10 and the first semiconductor chip 30. The adhesive layer 20 can bond the substrate 10 and the first semiconductor chip 30 together, enhance the adhesion between them, and thus improve the firmness of the semiconductor package structure.

[0075] The number of stacked second semiconductor chips in the second semiconductor chip structure 40 may be multiple, including but not limited to two, four, eight, twelve or sixteen. Figure 1a As shown, the number of the stacked second semiconductor chips in the second semiconductor chip structure 40 is four.

[0076] The second semiconductor chip may be a DRAM chip, an SRAM chip, an EEPROM chip or a PCM chip.

[0077] In one embodiment, the second semiconductor chip structure 40 includes a plurality of stacked second semiconductor chips, and the packaging structure further includes: a second packaging compound structure 52; the second packaging compound structure 52 is bonded to the first packaging compound structure 51 to encapsulate the second semiconductor chip structure 40; wherein the second packaging compound structure 52 includes a silicon-containing compound.

[0078] The silicon-containing compound may be spin-on glass (SOG), spin-on dielectric (SOD) containing silicon, or other spin-on materials containing silicon.

[0079] By forming a second packaging compound structure 52 that encapsulates the second semiconductor chip structure 40 and the material of the second packaging compound structure 52 includes a silicon-containing compound, the warping problem of the second semiconductor chip structure 40 can be improved, thereby further improving the warping problem of the entire packaging structure.

[0080] In one embodiment, the semiconductor packaging structure further includes: a conductive bump 60 located between the first semiconductor chip 30 and the second semiconductor chip structure 40 , and between two adjacent layers of the second semiconductor chips; the first packaging compound structure 51 and the second packaging compound structure 52 wrap the conductive bump 60 .

[0081] The first semiconductor chip 30 is electrically connected to the first layer of second semiconductor chips 41 via the conductive bumps 60 , and two adjacent layers of the second semiconductor chips may also be electrically connected via the conductive bumps 60 .

[0082] In some embodiments, Figure 2 As shown, the outer surface of the conductive bump 60 has a silicon-containing surface 611. The silicon-containing surface 611 of the conductive bump can improve the bonding performance between the package structure and the conductive bump, and can further improve the warping problem of the package structure.

[0083] Specifically, to ensure the electrical connection performance of the conductive bump, the silicon-containing surface may be formed only on the sidewall of the conductive bump, while the surface of the conductive bump that is bonded to the upper and lower chips does not have a silicon-containing surface.

[0084] The material of the silicon-containing surface 611 of the conductive bump 60 may be silicon dioxide.

[0085] In some other embodiments, such as Figure 1a and Figure 1b As shown, the outer surface of the conductive bump 60 may not have a silicon-containing surface.

[0086] In one embodiment, the number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of the second semiconductor chip structures are arranged in parallel on the first surface of the first semiconductor chip. Figure 1a As shown, the number of the second semiconductor chip structures is 2.

[0087] The semiconductor packaging structure further includes: a filling layer 70, located at the periphery of the second semiconductor chip structure 40, and / or located between two adjacent second semiconductor chip structures 40; wherein the Young's modulus of the filling layer 70 is greater than the Young's modulus of the packaging compound structure.

[0088] exist Figure 1a In the illustrated embodiment, a filling layer 70 is formed around the periphery of the second semiconductor chip structure 40 and between two adjacent second semiconductor chip structures 40 .

[0089] In some other embodiments, the filling layer 70 may be formed only around the periphery of the second semiconductor chip structure 40 , or between two adjacent second semiconductor chip structures 40 .

[0090] Young's modulus is a physical quantity that can describe the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the ability to resist deformation. When the Young's modulus is too low, it will be difficult to maintain the rigidity of the packaging structure, and deformation, warping, or breakage may occur easily. Therefore, in the embodiment of the present disclosure, a filling layer 70 is formed on the periphery of the second semiconductor chip structure 40, or between two adjacent second semiconductor chip structures 40, and the Young's modulus of the filling layer 70 is greater than the Young's modulus of the packaging compound structure. In this way, the filling layer 70 can have sufficient strength to support the entire packaging structure, so that the packaging structure is not prone to deformation, warping, or breakage.

[0091] The filling layer 70 extends to a depth above the upper surface of the first semiconductor chip 30 .

[0092] In one embodiment, the material of the filling layer 70 includes glass fiber or carbon fiber. The Young's modulus of the glass fiber or carbon fiber is large enough to improve the warpage of the packaging structure.

[0093] In one embodiment, the Young's modulus of the first potting compound structure 51 is smaller than the Young's modulus of the second potting compound structure 52 .

[0094] In one embodiment, the second encapsulation compound structure 52 includes multiple layers of second encapsulation compound stacked in sequence, each layer of the second encapsulation compound wraps a layer of second semiconductor chip; along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40, the Young's modulus of each layer of the second encapsulation compound gradually increases.

[0095] In one embodiment, except for the second packaging compound that wraps the first layer of second semiconductor chips, each layer of packaging compound from the first layer of second semiconductor chips onwards not only wraps one layer of second semiconductor chips, but also wraps the conductive bumps 60 under the second semiconductor chips.

[0096] Materials with low Young's modulus can absorb stress and reduce the delamination and warping problem of the chip. Therefore, along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40, the number of stacked chip layers is getting smaller and smaller, and the stress to be borne is also getting smaller and smaller. In the above embodiment, the Young's modulus of the first packaging compound structure is set to be smaller than the Young's modulus of the second packaging compound structure, and the Young's modulus of each layer of packaging compound in the second packaging compound structure is set to gradually increase along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40, which can make the stress environment of the packaging structure more uniform and further improve the warping problem of the chip.

[0097] In some other embodiments, such as Figure 1b As shown, the second encapsulation compound structure 52 is a single-layer structure that encapsulates the second semiconductor chip structure 40; the Young's modulus of the second encapsulation compound structure 52 is constant along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40. In this disclosed embodiment, because the Young's modulus of the second encapsulation compound structure is constant, the second encapsulation compound structure can be formed in the same step using the same material, thereby improving the chip warpage problem and simplifying the process steps.

[0098] In the embodiment of the present disclosure, the semiconductor package structure is a high bandwidth memory (HBM) package structure.

[0099] The present disclosure also provides a method for preparing a semiconductor packaging structure. Figure 3 , as shown in the figure, the method comprises the following steps:

[0100] Step 301: providing a substrate;

[0101] Step 302: forming a first semiconductor chip on the substrate; the first semiconductor chip has an exposed first surface, and the first surface has a silicon-containing surface;

[0102] Step 303: forming a first layer of second semiconductor chips on the first surface of the first semiconductor chip; the first layer of second semiconductor chips having a second surface opposite to the first surface;

[0103] Step 304: Form a first packaging compound structure between the first semiconductor chip and the first layer of the second semiconductor chip by spin coating; the first packaging compound structure has a bonding surface, and the bonding surface at least covers the first surface of the first semiconductor chip and the second surface of the first layer of the second semiconductor chip; wherein the bonding surface has a silicon-containing surface.

[0104] The method for preparing the semiconductor packaging structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments.

[0105] Figure 4a to Figure 4g A schematic diagram of the structure of a semiconductor packaging structure during the preparation process provided by an embodiment of the present disclosure; Figure 5a to Figure 5e A schematic structural diagram of a semiconductor packaging structure during the preparation process provided by another embodiment of the present disclosure.

[0106] It should be noted that Figure 4a to Figure 4g The embodiments shown and Figure 5a to Figure 5e The second encapsulation compound structure in the illustrated embodiment is different, and the remaining structures are the same. Figure 5a to Figure 5e In the embodiment shown, the previous steps are Figures 4a to 4d Consistent, that is Figure 5a Then Figure 4d The following steps continue the preparation.

[0107] First of all, Figure 4a to Figure 4g The illustrated embodiment is described in further detail.

[0108] Specifically, see Figure 4a , execute step 301 and provide a substrate 10.

[0109] The substrate 10 may be a single semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material silicon germanium (SiGe) substrate, etc., or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0110] Next, see Figure 4b, perform step 302 to form a first semiconductor chip 30 on the substrate 10; the first semiconductor chip 30 has an exposed first surface 311, and the first surface 311 has a silicon-containing surface.

[0111] In one embodiment, the first semiconductor chip 30 is a logic chip.

[0112] Continue to see Figure 4b Before executing step 302, an adhesive layer 20 is first formed on the substrate 10, and the adhesive layer 20 is located between the substrate 10 and the first semiconductor chip 30 to bond the substrate 10 and the first semiconductor chip 30. The adhesive layer 20 can bond the substrate 10 and the first semiconductor chip 30 together, enhance the adhesion between them, and further improve the firmness of the semiconductor packaging structure.

[0113] Next, see Figure 4c , perform step 303 to form a first layer of second semiconductor chips 41 on the first surface 311 of the first semiconductor chip 30 ; the first layer of second semiconductor chips 41 has a second surface 411 opposite to the first surface 311 .

[0114] It can be understood that the second surface of the first-layer second semiconductor chip 41 is also the second surface of the second semiconductor chip structure.

[0115] The second semiconductor chip may be a DRAM chip, an SRAM chip, an EEPROM chip or other memory chips.

[0116] In actual operation, before forming the first layer of second semiconductor chips 41 , a conductive bump 60 is first formed on the first semiconductor chip 30 , and then the first layer of second semiconductor chips 41 is formed on the conductive bump 60 .

[0117] The first semiconductor chip 30 is electrically connected to the first-layer second semiconductor chip 41 through a conductive bump 60 .

[0118] In some embodiments, Figure 2 As shown, the outer surface of the conductive bump 60 has a silicon-containing surface 611. The silicon-containing surface of the conductive bump can improve the bonding performance between the package structure and the conductive bump, and can further improve the warping problem of the package structure.

[0119] Specifically, to ensure the electrical connection performance of the conductive bump, the silicon-containing surface may be formed only on the sidewall of the conductive bump, while the surface of the conductive bump that is bonded to the upper and lower chips does not have a silicon-containing surface.

[0120] The material of the silicon-containing surface 611 of the conductive bump 60 may be silicon dioxide.

[0121] In some other embodiments, such as Figure 4c As shown, the outer surface of the conductive bump 60 may not have a silicon-containing surface.

[0122] Next, see Figure 4d , execute step 304, form a first packaging compound structure 51 between the first semiconductor chip 30 and the first layer second semiconductor chip 41 by spin coating; the first packaging compound structure 51 has a bonding surface, and the bonding surface at least covers the first surface 311 of the first semiconductor chip 30 and the second surface 411 of the first layer second semiconductor chip 41; wherein the bonding surface has a silicon-containing surface.

[0123] The material of the silicon-containing surface of the first encapsulation compound structure 51 may be spin-on glass (SOG), spin-on dielectric (SOD) containing silicon, or other spin-on materials containing silicon.

[0124] In the embodiment of the present disclosure, the bonding surface of the first packaging compound structure and the surface of the chip both have silicon elements, that is, they are both silicon surfaces. Compared with packaging with molding compound, the bonding performance of the interface can be improved, thereby improving problems such as warping and damage of the packaging structure.

[0125] Next, see Figure 4e and Figure 4f The method also includes: forming one or more layers of second semiconductor chips on the first layer of second semiconductor chips 41 to form a second semiconductor chip structure 40; forming a second packaging compound structure 52 wrapping the second semiconductor chip structure 40 by spin coating, and the second packaging compound structure 52 is bonded to the first packaging compound structure 51; wherein the second packaging compound structure 52 includes silicon-containing oxide.

[0126] The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0127] Specifically, see Figure 4e , one or more layers of second semiconductor chips are formed on the first layer of second semiconductor chips 41 to form a second semiconductor chip structure 40. The number of second semiconductor chips in the second semiconductor chip structure 40 can be multiple, including but not limited to two, four, eight, twelve or sixteen. In the embodiment of the present disclosure, Figure 4e As shown, the number of the stacked second semiconductor chips in the second semiconductor chip structure 40 is four.

[0128] More specifically, before forming the upper layer of second semiconductor chips, the conductive bumps 60 are first formed on the lower layer of second semiconductor chips, and then the upper layer of second semiconductor chips are formed. For example, before forming the second layer of second semiconductor chips, a layer of conductive bumps 60 is first formed on the first layer of second semiconductor chips, and then the second layer of second semiconductor chips is formed on the conductive bumps 60.

[0129] Two adjacent layers of the second semiconductor chips in the second semiconductor chip structure 40 may be electrically connected via a conductive bump 60 .

[0130] In one embodiment, the number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of second semiconductor chip structures are formed in parallel on the first surface of the first semiconductor chip. Figure 4e As shown, the number of the second semiconductor chip structures is 2.

[0131] Next, see Figure 4f , a second packaging compound structure 52 is formed by spin coating to wrap the second semiconductor chip structure 40. By forming the second packaging compound structure 52 to wrap the second semiconductor chip structure 40, and the material of the second packaging compound structure 52 is silicon-containing oxide, the warping problem of the second semiconductor chip structure 40 can be improved, thereby further improving the warping problem of the entire packaging structure.

[0132] In one embodiment, the Young's modulus of the first potting compound structure 51 is smaller than the Young's modulus of the second potting compound structure 52 .

[0133] In such Figure 4f In the illustrated embodiment, the second encapsulation compound structure 52 is a single-layer structure that encapsulates the second semiconductor chip structure 40; the Young's modulus of the second encapsulation compound structure 52 is constant along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40. In the disclosed embodiment, because the Young's modulus of the second encapsulation compound structure is constant, the second encapsulation compound structure can be formed in the same step using the same material, thereby improving the chip warpage problem and simplifying the process steps.

[0134] Next, see Figure 4g After forming the second packaging compound structure 52, the method further includes: etching to form a through hole at the periphery of the second semiconductor chip structure 40 and / or between two adjacent second semiconductor chip structures 40; filling the through hole to form a filling layer 70; wherein the Young's modulus of the filling layer 70 is greater than the Young's modulus of the first packaging compound structure 51 and the second packaging compound structure 52.

[0135] exist Figure 4g In the illustrated embodiment, a filling layer 70 is formed around the periphery of the second semiconductor chip structure 40 and between two adjacent second semiconductor chip structures 40 .

[0136] In some other embodiments, the filling layer 70 may be formed only around the periphery of the second semiconductor chip structure 40 , or between two adjacent second semiconductor chip structures 40 .

[0137] Specifically, a mask layer can be first grown on the upper surface of the second encapsulation compound structure 52, and then the mask layer can be patterned to display the through-hole pattern to be etched on the mask layer, and the mask layer can be patterned by a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is patterned by steps such as exposure, development, and degumming. Then, a through hole with a certain depth is etched according to the through-hole pattern to be etched, and the depth of the through hole can extend to the upper surface of the first semiconductor chip. Here, for example, a wet or dry etching process can be used to form the through hole.

[0138] Next, the through hole is filled to form a filling layer 70 .

[0139] Young's modulus is a physical quantity that can describe the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the ability to resist deformation. When the Young's modulus is too low, it will be difficult to maintain the rigidity of the package structure, and deformation, warping, or breakage may occur easily. Therefore, in the embodiment of the present disclosure, a filling layer 70 is formed on the periphery of the second semiconductor chip structure 40, and / or between two adjacent second semiconductor chip structures 40, and the Young's modulus of the filling layer 70 is greater than the Young's modulus of the packaging compound structure. In this way, the filling layer 70 can have sufficient strength to support the entire package structure, so that the package structure is not prone to deformation, warping, or breakage.

[0140] In one embodiment, the material of the filling layer 70 includes glass fiber or carbon fiber. The Young's modulus of the glass fiber or carbon fiber is large enough to improve the warpage of the packaging structure.

[0141] Next, Figure 5a to Figure 5e The illustrated embodiment is described in further detail. Figure 5a The previous process steps and Figures 4a to 4d The same, no further elaboration here.

[0142] First, see Figure 5a to Figure 5dAfter forming the first packaging compound structure 51, the method further includes: forming a first layer of second packaging compound 521 wrapping the first layer of second semiconductor chip 41 by spin coating; forming a second layer of second semiconductor chip 42 on the first layer of second semiconductor chip 41; forming a second layer of second packaging compound 522 wrapping the second layer of second semiconductor chip 42 by spin coating; repeating in sequence until the Nth layer of second packaging compound wrapping the last layer of second semiconductor chip is formed; wherein N is greater than or equal to 2; the multiple layers of second packaging compound form a second packaging compound structure 52, and the second packaging compound structure 52 includes a silicon-containing compound.

[0143] In the actual preparation process, N can be 2, 4, 8, 12 or 16. Specifically, in Figure 5a to Figure 5d In the illustrated embodiment, N is equal to 4.

[0144] In one embodiment, except for the first layer of the second packaging compound, from the second layer of the second packaging compound to the Nth layer of the second packaging compound, each layer of the second packaging compound not only wraps a layer of the second semiconductor chip, but also wraps the conductive bumps 60 under the layer of the second semiconductor chip.

[0145] Specifically, see Figure 5a , a first layer of second packaging compound 521 wrapping the first layer of second semiconductor chip 41 is formed by spin coating.

[0146] Next, see Figure 5b First, a layer of conductive bumps 60 is formed on the first layer of second semiconductor chips 41 , and then a second layer of second semiconductor chips 42 is formed on the conductive bumps 60 .

[0147] Next, see Figure 5c A second layer of second packaging compound 522 is formed by spin coating to wrap the second layer second semiconductor chip 42 and the conductive bumps 60 under the second layer second semiconductor chip 42 .

[0148] Next, see Figure 5d , repeat in sequence Figure 5b and Figure 5c The steps of forming a third layer of second packaging compound 523 wrapping the third layer of second semiconductor chip 43 and the conductive bump 60 under the third layer of second semiconductor chip 43; and a fourth layer of second packaging compound 524 wrapping the fourth layer of second semiconductor chip 44 and the conductive bump 60 under the fourth layer of second semiconductor chip 44.

[0149] In one embodiment, the Young's modulus of the first potting compound structure 51 is smaller than the Young's modulus of the second potting compound structure 52 .

[0150] In one embodiment, from the first layer of the second encapsulation compound 521 to the Nth layer of the second encapsulation compound, the Young's modulus of each layer of the second encapsulation compound gradually increases.

[0151] Materials with low Young's modulus can absorb stress and reduce the delamination and warping problem of the chip. Therefore, along the direction from the first semiconductor chip 30 to the second semiconductor chip structure 40, the number of stacked chip layers is getting smaller and smaller, and the deformation that needs to be borne is also getting smaller and smaller. Therefore, in the above embodiment, the Young's modulus of the first packaging compound structure is set to be greater than the Young's modulus of the second packaging compound structure, and the Young's modulus of each layer of packaging compound in the second packaging compound structure is set from the first layer of the second packaging compound to the Nth layer of the second packaging compound. The Young's modulus of each layer of the second packaging compound gradually increases, which can make the stress environment of the packaging structure more uniform and further improve the warping problem of the chip.

[0152] Next, see Figure 5e , multiple layers of second semiconductor chips form a second semiconductor chip structure 40; after forming the second packaging compound structure 52, the method further includes: etching to form a through hole at the periphery of the second semiconductor chip structure 40 and / or between two adjacent second semiconductor chip structures 40; filling the through hole to form a filling layer 70; wherein the Young's modulus of the filling layer 70 is greater than the Young's modulus of the first packaging compound structure 51 and the second packaging compound structure 52.

[0153] exist Figure 5e In the illustrated embodiment, a filling layer 70 is formed around the periphery of the second semiconductor chip structure 40 and between two adjacent second semiconductor chip structures 40 .

[0154] In some other embodiments, the filling layer 70 may be formed only around the periphery of the second semiconductor chip structure 40 , or between two adjacent second semiconductor chip structures 40 .

[0155] exist Figure 5e In the embodiment shown, the method steps for forming the filling layer are as follows Figure 4g The method steps for forming the filling layer in the illustrated embodiment are consistent and will not be repeated here.

[0156] In one embodiment, the material of the filling layer 70 includes glass fiber or carbon fiber. The Young's modulus of the glass fiber or carbon fiber is large enough to improve the warpage of the packaging structure.

[0157] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; A first semiconductor chip is located on the substrate, the first semiconductor chip has an exposed first surface, and the first surface has a silicon-containing surface; A second semiconductor chip structure is located on the first surface of the first semiconductor chip, wherein the second semiconductor chip structure includes a plurality of stacked second semiconductor chips; a first layer of second semiconductor chips has a second surface opposite to the first surface; A conductive bump is located between the first semiconductor chip and the first layer second semiconductor chip; a first packaging compound structure, encapsulating the conductive bump, wherein the first packaging compound structure has a bonding surface, wherein the bonding surface at least covers the first surface of the first semiconductor chip and the second surface of the first layer of the second semiconductor chip; wherein the bonding surface has a silicon-containing surface; a second packaging compound structure; the second packaging compound structure is bonded to the first packaging compound structure to encapsulate the second semiconductor chip structure; the second packaging compound structure comprises multiple layers of second packaging compounds stacked in sequence, each layer of the second packaging compound encapsulating a layer of the second semiconductor chip; wherein the second packaging compound structure comprises a silicon-containing compound, and the Young's modulus of the first packaging compound structure is smaller than that of the second packaging compound structure; and the Young's modulus of each layer of the second packaging compound gradually increases along a direction from the first semiconductor chip to the second semiconductor chip structure.

2. The semiconductor package structure according to claim 1, wherein: The conductive bump is also located between two adjacent layers of the second semiconductor chips; The second encapsulation compound structure encapsulates the conductive bump.

3. The semiconductor package structure according to claim 1, wherein: The outer surface of the conductive bump has a silicon-containing surface.

4. The semiconductor package structure according to claim 1, wherein: The number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of the second semiconductor chip structures are arranged in parallel on the first surface of the first semiconductor chip.

5. The semiconductor package structure according to claim 4, characterized in that: Also includes: The filling layer is located at the periphery of the second semiconductor chip structure and / or between two adjacent second semiconductor chip structures; wherein, The Young's modulus of the filling layer is greater than the Young's modulus of the potting compound structure.

6. The semiconductor package structure according to claim 5, characterized in that: The material of the filling layer includes glass fiber or carbon fiber.

7. A method for preparing a semiconductor packaging structure, characterized in that: include: providing a substrate; forming a first semiconductor chip on the substrate; The first semiconductor chip has an exposed first surface, the first surface having a silicon-containing surface; forming conductive bumps on the first semiconductor chip; forming a first layer of second semiconductor chips on the conductive bumps; The first layer second semiconductor chip has a second surface opposite to the first surface; forming a first packaging compound structure between the first semiconductor chip and the first layer of second semiconductor chips by spin coating, wherein the first packaging compound structure covers the conductive bumps; The first encapsulation compound structure has a bonding surface, the bonding surface at least covers the first surface of the first semiconductor chip and the second surface of the first layer of second semiconductor chips; wherein the bonding surface has a silicon-containing surface; forming one or more layers of second semiconductor chips on the first layer of second semiconductor chips to form a second semiconductor chip structure; A second packaging compound structure wrapping the second semiconductor chip structure is formed by spin coating, the second packaging compound structure is bonded to the first packaging compound structure, the second packaging compound structure comprises multiple layers of second packaging compounds stacked in sequence, each layer of the second packaging compound wrapping a layer of the second semiconductor chip; wherein, The second packaging compound structure includes a silicon-containing compound, and the Young's modulus of the first packaging compound structure is smaller than that of the second packaging compound structure; along the direction from the first semiconductor chip to the second semiconductor chip structure, the Young's modulus of each layer of the second packaging compound gradually increases.

8. The method according to claim 7, characterized in that Forming a second packaging compound structure encapsulating the second semiconductor chip structure by spin coating, wherein the second packaging compound structure is bonded to the first packaging compound structure, comprising: forming a first layer of second encapsulation compound encapsulating the first layer of second semiconductor chips by spin coating; forming a second layer of second semiconductor chips on the first layer of second semiconductor chips; forming a second layer of second packaging compound encapsulating the second layer of second semiconductor chip by spin coating; Repeating in sequence until an Nth layer of the second packaging compound is formed to encapsulate the last layer of the second semiconductor chip; wherein N is greater than or equal to 2; Multiple layers of second potting compound form the second potting compound structure.

9. The method according to any one of claims 7 or 8, characterized in that: The number of the second semiconductor chip structures is greater than or equal to 2; and a plurality of second semiconductor chip structures are formed in parallel on the first surface of the first semiconductor chip.

10. The method according to claim 7, characterized in that After forming the second encapsulation compound structure, the method further comprises: Etching to form a through hole at the periphery of the second semiconductor chip structure and / or between two adjacent second semiconductor chip structures; The through hole is filled to form a filling layer; wherein the Young's modulus of the filling layer is greater than the Young's modulus of the first encapsulation compound structure and the second encapsulation compound structure.

11. The method according to claim 10, characterized in that The material of the filling layer includes glass fiber or carbon fiber.

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