Mask for improving warpage of trench gate IGBT (Insulated Gate Bipolar Translator) wafer

Abstract

The invention provides a mask plate for improving warpage of a trench gate IGBT wafer, and relates to the technical field of semiconductor device manufacturing, a plurality of IGBT chips are arranged on the mask plate, and the IGBT chips are the same in specification; the IGBT chips on the mask plate are arranged in a staggered mode, one part of the IGBT chips are arranged in the 0-degree direction, and the other part of the IGBT chips are arranged in the 90-degree direction after being rotated; according to the staggered arrangement mode, the IGBT chips are arranged in a staggered mode in the 0-degree direction and the 90-degree direction by adopting array layout on a mask plate. The mask plate transfers IGBT chip patterns which are arranged in a staggered mode to a wafer of a silicon base material in a photoetching machine exposure field mode, and a mask layout layout in which internal stress of trench gates cannot be overlapped between the IGBT chips which are arranged in the 0-degree direction and the 90-degree direction in a staggered mode and local area stress counteracts is formed. By means of the staggered direction arrangement mode, stress in different directions counteracts each other, and therefore warping of the wafers is effectively relieved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to a mask for improving warpage of a trench gate IGBT (insulated gate bipolar transistor) wafer. Background Art

[0002] With the continuous development of IGBT (insulated gate bipolar transistor) chip technology, especially in the manufacturing process of large-sized wafers (such as 12 inches), the design and arrangement method of trench gate IGBT chips will have a significant impact on the warping problem of wafers. Existing trench gate IGBT chips are usually arranged using strip trench gates in the same direction. This arrangement method easily causes the accumulation of internal stress on large-sized wafers, causing the wafer to warp during the etching process. Warping will not only increase the lithography alignment error in chip processing, affect the size of the pattern, and even cause pattern deformation, but also aggravate stress defects and directly affect device performance.

[0003] Among them, the trench gate is arranged using strip trench gates in the same direction. When the IGBT chip wafer is warped, it will cause lithography alignment deviation, stress defects and chip breakage. Among them, wafer warping will increase the alignment error in the lithography process, thereby affecting the accuracy of the pattern, causing pattern deformation or size deviation, and further affecting the performance of the device; wafer warping will also cause different degrees of stress in different areas of the silicon substrate. These stresses may cause potential defects in the material, thereby affecting the quality and reliability of the chip; especially in the ultra-thin chip process, wafer warping may cause the back material to be too thin, which may cause the chip to easily break during processing, further reducing the yield.

[0004] Although existing production processes, such as optimized heat treatment technology and wet etching process, can alleviate the problem of wafer warpage to a certain extent, these methods cannot fundamentally solve the problem of wafer warpage and its impact, especially on large-sized wafers (such as 12 inches), wafer warpage is still a technical problem that cannot be ignored. Therefore, how to reduce wafer warpage by improving the design, thereby improving the yield and reducing production costs, is a key issue in current semiconductor manufacturing. Summary of the invention

[0005] In view of this, the purpose of the present invention is to propose a mask for improving the warpage of trench gate IGBT wafers, and to reduce the problem of wafer warpage caused by the trench gate structure by optimizing the mask design, and to improve the yield of IGBT chips. This method does not require changing the chip design rules, nor does it require adding additional process costs. It only requires adjusting the arrangement of the IGBT chips during the mask design stage, and through the staggered arrangement, the stresses in different directions are offset each other, thereby effectively alleviating the warpage of the wafer.

[0006] To achieve the above object, the present invention provides the following technical solutions: Based on the above purpose, the present invention provides a mask for improving the warpage of a trench gate IGBT wafer, wherein a plurality of IGBT chips are arranged on the mask, and each IGBT chip has the same specification; The IGBT chips on the mask are arranged in a staggered manner, with a portion of the IGBT chips arranged in a 0° direction and another portion of the IGBT chips arranged in a 90° direction after rotation; the staggered arrangement is achieved by using an array layout on the mask to arrange the IGBT chips in a staggered manner in the 0° direction and the 90° direction; The mask plate transfers the staggered IGBT chip pattern to the silicon substrate wafer by means of the exposure field of the photolithography machine, forming a mask layout in which the internal stress of the trench gate cannot be superimposed between the staggered IGBT chips in the 0 degree and 90 degree directions and the stress is offset in the local area, thereby reducing the warping of the wafer.

[0007] As a further solution of the present invention, the 0° arrangement refers to that the strip-shaped groove gate of the IGBT chip extends in the left-right direction, and the 90° arrangement refers to that the strip-shaped groove gate of the IGBT chip extends in the up-down direction.

[0008] As a further solution of the present invention, the IGBT chip on the mask is square, and the length and width of each IGBT chip are the same.

[0009] As a further solution of the present invention, the IGBT chip consists of a cell region and a terminal region. The terminal region surrounds the outside of the cell region, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region. A strip-shaped groove gate is opened in the silicon substrate on the front side of the cell region, and an IGBT gate is also arranged on the IGBT chip. The position of the IGBT gate is set at the center of the IGBT chip to meet the design requirements of staggered arrangement of the chip direction.

[0010] As a further solution of the present invention, the mask plate adopts a 4×3 array layout, and 12 IGBT chips are arranged on the mask plate, and the IGBT chips are arranged in a staggered manner at 0 degrees and 90 degrees.

[0011] As a further solution of the present invention, the IGBT chips with the same orientation on the mask are grouped into three to form an L-shaped combination, and the L-shaped combination of the 0-degree IGBT chip and the 90-degree IGBT chip are spliced ​​together to form a rectangle; between the two groups of rectangles on the mask, the L-shaped combinations with the same orientation are not adjacent.

[0012] As a further solution of the present invention, the IGBT chips in each row and each column on the mask plate include IGBT chips arranged in a 0° direction and in a 90° direction to achieve a staggered arrangement.

[0013] As a further solution of the present invention, the mask plate transfers the IGBT chip to a wafer of a silicon substrate through a photolithography machine, and the adjacent L-shaped combinations have different orientations; so that the IGBT chips arranged in the 0° direction and the 90° direction form a mutual offset of the stress in the local area on the wafer, thereby significantly improving the warping problem of the wafer.

[0014] As a further solution of the present invention, the IGBT chips transferred to the silicon substrate wafer by a photolithography machine are arranged in sequence, and the IGBT chips on adjacent mask plates are arranged in an L-shaped combination in an interlaced manner and the IGBT chips in adjacent L-shaped combinations face different mask layouts.

[0015] Compared with the prior art, the mask for improving the warpage of the trench gate IGBT wafer proposed in the present invention has the following beneficial effects: 1. The present invention adopts a staggered arrangement on the mask, that is, the IGBT chips are arranged in the 0° direction and the 90° direction respectively, which successfully reduces the internal stress accumulation of the trench gate chip on the wafer and significantly reduces the wafer warpage. Since the internal stress in the 0° direction and the 90° direction offset each other, the warpage caused by uneven internal stress is reduced. Therefore, the warpage problem of the wafer is significantly improved, especially on large-sized (such as 12-inch) wafers.

[0016] 2. The present invention can improve the alignment accuracy during the photolithography process, ensure that the pattern transferred to the wafer is more accurate, and reduce the defect rate caused by the photolithography alignment deviation. By adopting the design of staggered arrangement in the 0° and 90° directions, the internal stress distribution is optimized, the stress in the local area offsets each other, and the stress concentration is reduced, thereby reducing warping and potential defects, effectively reducing wafer cracking and damage caused by warping, and thus improving the chip yield. Especially in the production of high-precision IGBT chips, the improvement of yield is crucial to reducing production costs and improving economic benefits.

[0017] 3. The present invention reduces wafer warping by optimizing the mask design, without changing the original design rules of the chip or adding complex processing technology. Therefore, the process cost and time cost in the production process are relatively low, and it can be easily integrated into the existing production process, improving production efficiency and avoiding unnecessary investment. Moreover, the staggered arrangement adopted by the present invention is not only suitable for large 12-inch wafers, but can also be used in the production of wafers of other sizes. Therefore, the method has strong adaptability, can meet the needs of manufacturing IGBT chips of different sizes, and has broad application prospects.

[0018] 4. Since wafer warping may cause wafer breakage or chip quality degradation in ultra-thin chip production, the present invention reduces the risk of breakage due to excessive internal stress by optimizing the chip arrangement. The staggered arrangement design effectively disperses the stress inside the chip, reduces the incidence of stress defects, and further improves the reliability of the chip. By reducing warping and improving yield, the present invention can effectively reduce the scrap rate, reduce material waste and loss caused by warping during the production process, and thus reduce the overall production cost. In addition, since no additional complex process or equipment changes are required, the adjustment cost of the production line is low.

[0019] In summary, the present invention effectively alleviates the problem of wafer warping during the manufacturing process of trench gate IGBT chips by adopting a staggered mask design, which not only improves chip yield, optimizes internal stress distribution, but also reduces production costs and production cycles. Its innovative design has a significant effect on improving chip manufacturing quality and production efficiency, and has strong practical application value and broad industry prospects.

[0020] These and other aspects of the present application will be more concise and understandable in the following description of the embodiments. It should be understood that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the exemplary embodiments or related technical descriptions. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings: Figure 1 The figure is a schematic diagram of IGBT chip arrangement in a mask for improving warpage of a trench gate IGBT wafer according to an embodiment of the present invention.

[0022] Figure 2 The diagram is a top view of an IGBT chip in a mask for improving warpage of a trench gate IGBT wafer according to an embodiment of the present invention.

[0023] Figure 3 The schematic diagram of the top view of an IGBT chip placed at 0° in a mask for improving warpage of a trench gate IGBT wafer according to an embodiment of the present invention is shown.

[0024] Figure 4 The schematic diagram of the top view of an IGBT chip placed at 90 degrees in a mask for improving warpage of a trench gate IGBT wafer according to an embodiment of the present invention.

[0025] Figure 5The figure is a schematic diagram of arrangement and placement of IGBT chips on a wafer in a mask for improving warpage of a trench gate IGBT wafer according to an embodiment of the present invention.

[0026] Description of reference numerals: 1-IGBT chip, 11-terminal region, 12-cell region, 13-strip trench gate, 14-IGBT gate, 2-mask, 3-wafer, 4-lateral L-type combination, 5-vertical L-type combination. DETAILED DESCRIPTION

[0027] Below, the present application is further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product or device that includes a series of steps or units.

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0032] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] Since all the strip-shaped trench gates extend in the same direction, the consistent directional arrangement will result in a large internal stress in the extending direction of the trench gate, thereby causing the problem of wafer warping. The present invention proposes a mask for improving the warping of trench gate IGBT wafers, which reduces the wafer warping problem caused by the trench gate structure by optimizing the mask design and improves the yield of the IGBT chip. The method does not require changing the chip design rules or adding additional process costs. It only requires adjusting the arrangement of the IGBT chip during the mask design stage, and using the staggered directional arrangement to offset the stresses in different directions, thereby effectively alleviating the warping of the wafer.

[0034] See also Figure 1 As shown, an embodiment of the present invention provides a mask for improving the warpage of a trench gate IGBT wafer, wherein a plurality of IGBT chips 1 are arranged on the mask 2, and each IGBT chip 1 has the same specifications. The IGBT chips 1 on the mask 2 are arranged in a staggered manner, with a portion of the IGBT chips 1 arranged in a 0° direction and another portion of the IGBT chips 1 arranged in a 90° direction after rotation; the staggered arrangement is to arrange the IGBT chips 1 in an array layout on the mask 2 in a staggered manner in the 0° direction and the 90° direction.

[0035] See also Figure 2 As shown, the mask plate 2 transfers the pattern of the staggered IGBT chips 1 to the wafer 3 of the silicon substrate by means of the exposure field of the photolithography machine, forming a mask layout in which the internal stress of the trench gate cannot be superimposed between the staggered IGBT chips 1 in the 0 degree and 90 degree directions and the stress is offset in the local area, thereby reducing the warping of the wafer.

[0036] See also Figure 2 As shown, the IGBT chip 1 on the mask 2 is square, and the length and width of each IGBT chip 1 are the same. The IGBT chip 1 consists of a cell region 12 and a terminal region 11. The terminal region 11 surrounds the outside of the cell region 12, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region 11; a strip-shaped trench gate 13 is opened in the silicon substrate on the front of the cell region 12, and an IGBT gate 14 is also arranged on the IGBT chip 1; the position of the IGBT gate 14 is set at the center of the IGBT chip 1 to meet the design requirements of staggered arrangement of the chip direction.

[0037] See also Figure 3 As shown, the 0° direction arrangement means that the strip-shaped trench gate 13 of the IGBT chip 1 extends in the left-right direction, see Figure 4 As shown, the 90° arrangement means that the strip-shaped trench gate 13 of the IGBT chip 1 extends in the up-down direction. Figure 3 and Figure 4The arrow in shows that the stress direction of the cell region 12 is consistent with the extending direction of the strip trench gate 13 .

[0038] In this embodiment, see Figures 1 to 4 As shown, the mask plate 2 adopts a 4×3 array layout, and 12 IGBT chips 1 are arranged on the mask plate 2, and the IGBT chips 1 are arranged in a staggered manner of 0 degrees and 90 degrees. The IGBT chips 1 with the same orientation on the mask plate 2 are grouped into three to form an L-shaped combination, and the L-shaped combination of the 0-degree IGBT chip 1 and the 90-degree IGBT chip 1 is spliced ​​to form a rectangle; between the two groups of rectangles on the mask plate 2, the L-shaped combinations with the same orientation are not adjacent.

[0039] See also Figure 5 As shown, three 0-degree IGBT chips 1 on the mask 2 form a group to form a transverse L-shaped combination 4; three 90-degree IGBT chips 1 form a group to form a longitudinal L-shaped combination 5; the transverse L-shaped combination 4 of the 0-degree IGBT chip 1 and the longitudinal L-shaped combination 5 of the 90-degree IGBT chip 1 are spliced ​​together to form a rectangle; between the two groups of rectangles on the mask 2, the L-shaped combinations in the same direction are not adjacent, that is, the transverse L-shaped combination 4 and the longitudinal L-shaped combination 5 between the two groups of rectangles on the mask 2 are adjacent, and the transverse L-shaped combination 4 between the two groups of rectangles is not adjacent, and on the wafer 3 formed in this way, the transverse L-shaped combination 4 and the longitudinal L-shaped combination 5 are arranged alternately.

[0040] The present invention adopts a staggered arrangement on the mask plate 2, that is, the IGBT chips 1 are arranged in the 0° direction and the 90° direction respectively, which successfully reduces the internal stress accumulation of the trench gate chip on the wafer 3 and significantly reduces the wafer warping. Since the internal stresses in the 0° direction and the 90° direction offset each other, the warping phenomenon caused by uneven internal stress is reduced. Therefore, the warping problem of the wafer 3 is significantly improved, especially on large-sized (such as 12-inch) wafers.

[0041] The IGBT chips 1 in each row and column on the mask plate 2 include IGBT chips 1 arranged in the 0° direction and the 90° direction to achieve a staggered arrangement, so as to offset the stress in the local area, thereby reducing the warping of the wafer 3 .

[0042] In this embodiment, see Figure 1 and Figure 5 As shown, the mask plate 2 transfers the IGBT chip 1 to the wafer 3 of the silicon substrate through a photolithography machine, and the adjacent L-shaped combinations have different directions; so that the IGBT chips 1 arranged in the 0° direction and the 90° direction form a local area stress on the wafer 3 to offset each other, thereby significantly improving the warping problem of the wafer 3.

[0043] The present invention arranges the strip-shaped trench gates 13 of the IGBT chip 1 in a staggered arrangement, that is, alternately arranged in the 0° and 90° directions. This layout can effectively balance the stress generated on the wafer 3 during the chip production process, avoids the internal stress accumulation caused by the consistent direction of the trench gates in the traditional design, and thus significantly reduces the warping of the wafer 3.

[0044] Among them, see Figure 5 As shown, the IGBT chips 1 transferred to the wafer 3 of the silicon substrate by the photolithography machine are arranged in sequence, and the IGBT chips 1 of adjacent mask plates 2 are arranged in an L-shaped combination in an interlaced manner, and the IGBT chips 1 in adjacent L-shaped combinations face different mask layouts.

[0045] In the photolithography process, after using the mask 2 of the present invention, the stress distribution on the wafer 3 is more uniform, the overall stress concentration is reduced, and the stress of the wafer 3 and the cracking or cracking problems that may occur during the heat treatment process are reduced, thereby ensuring the stability and safety of the wafer 3. Due to the staggered arrangement design of the IGBT chips 1 on the mask 2, the alignment error and pattern alignment difficulty caused by the warping of the wafer 3 can be reduced, thereby simplifying the subsequent manufacturing operations, improving the automation level of the production line, and reducing the possibility of manual intervention and errors.

[0046] The present invention reduces the warping of the wafer 3, avoids the lithography alignment deviation, pattern deformation and potential stress defects caused by the warping, reduces the defective rate, and significantly improves the yield rate of the chip. In addition, since the integrity of the wafer 3 is improved, there are fewer chip damage or breakage problems during the manufacturing process, further improving production efficiency and product qualification rate. The present invention optimizes the mask plate 2 to design an interlaced arrangement of the IGBT chip 1, so that the processing process can be more stable, reducing the processing difficulties and cost increases caused by warping. Therefore, the final production cost is reduced.

[0047] The present invention is not only suitable for large-sized wafers 3 such as 12 inches through a staggered arrangement design, but can also be flexibly applied to silicon wafers 3 of different sizes, and has strong adaptability. Even in the production of IGBT chips 1 of different sizes and types, a good stress offset effect can still be exerted. In the design of the present invention on the mask plate 2, the chip layouts arranged in the 0° and 90° directions are alternately distributed, and the chips arranged in the 90° direction are L-shaped and distributed on both sides of the chips arranged in the 0° direction along the diagonal distribution. This layout allows the stresses in the local areas where the chips are arranged on the wafer 3 to offset each other, further optimizes the stress distribution during the production process, and avoids the risk of damage caused by concentrated stress.

[0048] In summary, the present invention reduces the warping problem of the IGBT wafer 3 by designing the mask plates 2 arranged in staggered directions, significantly improves the yield, reduces production costs, and enhances the overall stability of the chip, providing an innovative solution for the efficient and stable production of the IGBT chip 1.

[0049] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0050] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0051] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A mask for improving the warpage of a trench gate IGBT wafer, characterized in that: The mask is provided with a plurality of IGBT chips, and the specifications of each IGBT chip are the same; The IGBT chips on the mask are arranged in a staggered manner, with a portion of the IGBT chips arranged in a 0° direction and another portion of the IGBT chips arranged in a 90° direction after rotation; the staggered arrangement is achieved by using an array layout on the mask to arrange the IGBT chips in a staggered manner in the 0° direction and the 90° direction; The mask plate transfers the staggered IGBT chip pattern to the silicon substrate wafer by means of a photolithography machine exposure field, forming a mask layout in which the internal stress of the trench gate cannot be superimposed between the staggered IGBT chips in the 0 degree and 90 degree directions and the stress is offset in the local area.

2. The mask for improving the warpage of the trench gate IGBT wafer according to claim 1, characterized in that: The 0° arrangement means that the strip-shaped trench gates of the IGBT chip extend in the left-right direction, and the 90° arrangement means that the strip-shaped trench gates of the IGBT chip extend in the up-down direction.

3. The mask for improving the warpage of the trench gate IGBT wafer according to claim 2, characterized in that: The IGBT chips on the mask are square, and the length and width of each IGBT chip are the same.

4. The mask for improving the warpage of the trench gate IGBT wafer according to claim 3, characterized in that: The IGBT chip consists of a cell region and a terminal region. The terminal region surrounds the outside of the cell region, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region. A strip-shaped groove gate is opened in the silicon substrate on the front side of the cell region, and an IGBT gate is also arranged on the IGBT chip. The position of the IGBT gate is arranged at the center of the IGBT chip.

5. The mask for improving the warpage of the trench gate IGBT wafer according to claim 1, characterized in that: The mask plate adopts a 4×3 array layout, and 12 IGBT chips are arranged on the mask plate, and the IGBT chips are arranged in a staggered manner of 0 degrees and 90 degrees.

6. The mask for improving the warpage of the trench gate IGBT wafer according to claim 5, characterized in that: The IGBT chips with the same orientation on the mask are grouped into three to form an L-shaped combination, and the L-shaped combination of the 0-degree IGBT chip and the 90-degree IGBT chip are spliced ​​together to form a rectangle; between the two groups of rectangles on the mask, the L-shaped combinations with the same orientation are not adjacent.

7. The mask for improving the warpage of the trench gate IGBT wafer according to claim 6, characterized in that: The IGBT chips in each row and each column on the mask plate include IGBT chips arranged in a 0° direction and in a 90° direction.

8. The mask for improving the warpage of the trench gate IGBT wafer according to claim 7, characterized in that: The mask plate transfers the IGBT chip to a wafer of a silicon substrate through a photolithography machine, and adjacent L-shaped combinations have different orientations.

9. The mask for improving the warpage of the trench gate IGBT wafer according to claim 8, characterized in that: The IGBT chips transferred to the silicon substrate wafer by the photolithography machine are arranged in sequence, and the IGBT chips on adjacent mask plates are arranged in an L-shaped combination in an interlaced manner, and the IGBT chips in adjacent L-shaped combinations face different mask layouts.

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